DE102004046429B4 - Interface means - Google Patents

Abstract

The invention relates to a method for operating an interface device (20), and an interface device (20), in particular for a microcontroller or microprocessor system (10), which is connected to a memory device (18) and to a bus system (16) can be connected, with a device (23, 20) for requesting a plurality of data to be read out from the memory device (18), characterized in that only some of the data received by the memory device (18), requested data are forwarded from the interface device (20) to the bus system (16).

Description

The invention relates to an interface device, in particular an interface device for a microcontroller or microprocessor system.

Conventional digital arithmetic circuits (eg corresponding microcontroller or microprocessor systems arranged on a microchip) have one or more (central) control or arithmetic units (Central Processing Units (CPUs) or CPU cores). ,

The CPU or the CPUs are - z. B. via a corresponding multi-master on-chip bus (and possibly one or more other bus systems) - connected to one or more (external or internal) storage facilities, eg. B. a program and a data storage device ("program memory", and "data storage").

The multi-master on-chip bus (eg the FPI bus of the company Infineon, or the AHB bus of the company ARM, etc.) can z. B. have a data bus width of 1 word (32 bits), or z. From 2 Word (64 bits), etc.

The "program memory" contains, in particular, the sequence of the commands to be processed by the CPU core (s), that is to say the program (and possibly additionally corresponding data constants to be used by the CPU core or cores).

The program memory can z. B. from an EPROM (erasable PROM or erasable PROM) or EEPROM (Electrically Erasable PROM), in particular a flash EEPROM device (for example, a burst flash EEPROM).

It can thereby be achieved that the program remains stored even if the power supply is interrupted on the corresponding memory devices.

For frequently changed programs can - alternatively - z. B. RAMs (RAM = Random Access Memory or read-write memory), in particular DRAMs are used as program memory, z. B. corresponding SDRAMs, in particular DDR SDRAMs, etc., which can be loaded from an external mass storage.

The o. G. Memory devices, in particular z. Flash EEPROMs, SDRAMs, DDR SDRAMs, etc., have the property that each first access may take a relatively long access time (in particular, more than one clock, eg, two or three clocks), directly sequentially subsequent accesses (in particular burst accesses), however, can take place with significantly less access time (for example, one clock in each case).

In o. G. "Datastore" can z. For example, the variables to be stored, in particular by the CPU cores when executing the program, may be stored.

The data store can, for. B. of one or more RAM devices, in particular z. B. a corresponding DRAM device (DRAM = Dynamic Random Access Memory), or SRAM device (SRAM = static random access memory) are formed.

The CPU or CPUs can -. B. on the o. G. Multi-master on-chip bus, and an interface device connected thereto - to be connected to one (or more) external module (s), in particular corresponding peripheral, external from o. G. Microchip arranged modules, the z. B. communicate with the interface device via corresponding further bus systems.

In order for the CPU or the CPUs, the access times to the program (more precisely: the above-mentioned program commands), and / or the o. G. In addition, so-called cache memory can be used to shorten data constants or variables.

A cache is a small, fast buffer memory that can be used, for example. B. may be integrated into the CPU itself (or may be located in the vicinity).

A cache may include one or more cache lines, e.g. B. each have a cache line width of z. B. 8 Word (256 bits), or z. B. 16 Word (512 bits), etc. may have.

In a cache memory z. As the last used - or expected to be used in the future - commands are stored (instruction cache), or the last used - or expected to be used in the future - data (Data Cache).

For most programs, the probability that - if accessed - the required commands / data are still (or already) in the cache memory (eg in the instruction cache, or in the data cache) is relatively high.

As a result, on average, lower access times can be achieved than without cache memory.

If the required commands / data are not in the cache memory (so-called "cache miss"), the corresponding data / commands from the corresponding (external or internal) data memory or program memory read, and - z. B. over the above-mentioned multi-master on-chip bus - to the respective cache memory, or the CPU transferred.

Since - as explained above - in the o. Memory devices (eg., Flash EEPROMs, SDRAMs, DDR SDRAMs, etc.) each first access can take a relatively long access time, directly followed sequentially subsequent accesses (in particular burst accesses) but with significantly lower access time can, is at a "cache miss" i. d. R. read out not only the respective required date / command from the respective memory component, but also a plurality of additional, subsequent data / commands (eg, 8, 16 or 32 at successive memory locations or addresses in the respective memory Component), and transferred to the respective cache memory - the likelihood that these data / instructions will be accessed in the near future is relatively high.

The disadvantage of this approach is u. a. That up to the time at which the actual - currently - required date or the actual - actually - required command transmitted to the cache memory, and stored is a relatively long period of time can pass.

From the US 6 021 480 A For example, a computer system is known in which a PCI bridge is connected to a memory device and a bus system.

The US Pat. No. 6,654,872 B1 shows a method in which an instruction cache line is split into two components.

In the US 5,131,083 A A method for transmitting burst data in a microprocessor is described.

The US 2004/0088490 A1 shows a prefetch system in which a buffer of a memory controller or cache controller is used to perform a prefetch operation.

According to the invention, an interface device with the features specified in claim 1 is provided, as well as a microcontroller or microprocessor system with such an interface device.

Advantageous developments of the invention are specified in the subclaims.

In the following the invention will be explained in more detail with reference to embodiments and the accompanying drawings. In the drawing shows:

1 a schematic, exemplary representation of a microcontroller or microprocessor system;

2a a schematic data flow diagram illustrating a with the in 1 a microcontroller microprocessor system executable cache load method according to an embodiment of the present invention;

2 B a schematic data flow diagram illustrating a variant of the in 1 shown microcontroller or microprocessor system feasible cache memory charging method, at different clock frequencies used by the multi-master on-chip bus and the external memory device;

3a a schematic detail representation of in 1 shown interface means of the microcontroller or microprocessor system, and the memory device connected thereto, for the purpose of illustrating the address and control data flow; and

3b a schematic detail representation of in 1 shown interface device of the microcontroller or microprocessor system, and the memory device connected thereto, for illustrating the Nutz-data flow.

In 1 is a schematic representation of a microcontroller or microprocessor system 10 shown according to an embodiment of the invention.

In the microcontroller or microprocessor system 10 can it be z. B. an 8-bit microcontroller or microprocessor system 10 or any other microcontroller or microprocessor system, e.g. B. a corresponding 16-bit or 32-bit microcontroller or microprocessor system, etc.

The microcontroller or microprocessor system 10 has one or more, on a corresponding microchip 15 arranged (central) control or computing units 11 on (Central Processing Units (CPUs), or CPU "cores").

The CPU 11 or the CPUs are - via a multi-master on-chip bus 16 (and possibly one or more other bus systems) - with one or more internal (on the same microchip 15 like the CPU 11 provided) storage facilities 17 connected, and - z. Via the multi-master on-chip bus 16 , and one or more corresponding memory controllers ("memory controller") 12 - with one or more external (on a different microchip, than the CPU 11 provided) storage facilities 18 ,

As a multi-master on-chip bus, in principle, any multi-master on-chip bus can be used, for. As the FPI bus from. Infineon, or the AHB bus Fa. ARM, etc.

The multi-master on-chip bus may have multiple sub-buses, e.g. As a data bus, a control bus, and an address bus, via which corresponding data, control and address signals can be transmitted.

The data bus can z. B. have a width of 1 word (32 bits), or z. From 2, 3 or 4 Word (64, 96, or 128 bits), etc.

The storage facilities 17 . 18 can z. B. as a program storage device, and / or data storage device ("program memory", and "data storage") act.

The "program memory" contains in particular the sequence of the CPU or CPUs 11 to be processed commands, so the program (and possibly additionally appropriate - of the or the CPUs 11 to be used - data constants).

The - z. B. from the memory device 17 , and / or the memory device 18 formed - program memory can, for. B. from an EPROM (erasable PROM or erasable PROM) or EEPROM (Electrically Erasable PROM), in particular a flash EEPROM device (for example, a burst flash EEPROM).

It can thereby be achieved that the program remains stored even if the power supply is interrupted on the corresponding memory devices.

For frequently changed programs can - alternatively - z. B. RAMs (RAM = Random Access Memory or read-write memory), in particular DRAMs (DRAM = Dynamic Random Access Memory) are used as program memory, z. B. corresponding SDRAMs (SDRAM = Static Dynamic Random Access Memory), in particular DDR SDRAMs (Double Data Rate SDRAMs or SDRAMs with double data rate), etc.

In the above -. B. from the memory device 18 , and / or the memory device 17 formed - "data storage" can z. B. the - in particular of the or the CPUs 11 Variables to be modified when the program is executed.

The data store can, for. B. of one or more RAM devices, in particular z. B. a corresponding DRAM device (DRAM = Dynamic Random Access Memory), or SRAM device (SRAM = static random access memory) are formed, etc.

The above-mentioned storage facilities 17 and or 18 may have the property that each first access can take a relatively long access time (in particular more than one clock, eg two or three clocks), directly sequentially subsequent accesses (in particular burst accesses) but with significantly less access time (For example, one clock each) can be done.

The CPU or CPUs 11 can -. B. via the above-mentioned multi-master on-chip bus 16 (and possibly one or more other bus systems), and one to the bus 16 (or the other bus systems) connected, internal, on the microchip 15 provided interface device 20 - be connected to one (or more) external module (s).

Alternatively or additionally, the CPU or the CPUs 11 - z. B. via the above-mentioned multi-master on-chip bus 16 , and a connected bridge 14 (or more such bridges) - to one or more other on-chip buses 19 be connected (eg, one or more other multi-master on-chip buses 19 ).

These can - as in 1 is shown - over one or more more, internal, on the microchip 15 provided interface devices 21 - be connected to one or more other external modules.

How out 1 further points out, to the multi-master on-chip bus 16 be connected to a DMA controller (DMA = Direct Memory Access)

In order for the CPU 11 or the CPUs the access times to the program (more precisely: the above-mentioned program commands), and / or the above-mentioned data constants or variables - on average - to keep as short as possible in the present embodiment - and as in 1 shown - one or more so-called cache memory 22a . 22b used (here: two cache memories 22a . 22b ).

For the cache memories 22a . 22b These are small, fast buffer memories, which can be B. into the CPU 11 themselves (or can be arranged in their immediate vicinity).

The cache memory 22a . 22b - where z. B. may be so-called. "Critical word first" cache memory - may each include one or more cache lines, the z. B. each have a cache line width of z. B. 8 × 1 word (256 bits), or z. 16 or 32 x 1 Word (512 bits or 1 Gbit), etc. (or, for example, 8 x 2 Word, 16 x 2 Word, etc.).

Each date stored in a corresponding cache line (which may each have, for example, a width of, for example, 1 word (or, for example, a width of 2 words each, etc.)) is a corresponding cache line. Line address assigned, z. Example, the address 0, or the address 1, or 2, 3, 4, 5, 6, 7 (or expressed as a corresponding binary number, for example, "000", or "001", or "010", "011 "," 100 ", etc.).

For example, with a cache line width of e.g. For example, a total of 8 Word at 8 different cache line addresses (eg, the addresses 0, 1, 2, 3, 4, 5, 6, 7) as a date each z. For example, a word may be stored (or, for example, 2 words each, etc.).

In the cache 22a can z. For example, the most recently used instructions, or those expected to be used in the future, are stored ("instruction cache") and in the cache memory 22b the most recently used - or the data likely to be used in the future - especially data constants or variables ("data cache").

For most programs, the probability is relatively high that - with a corresponding access - the required commands / data still (or already) in the respective cache memory 22a . 22b (eg in the instruction cache 22a , or in the data cache 22b ) stand.

As a result, on average, lower access times can be achieved than without cache memory.

If a respective required command / date is not available - at the corresponding cache line address - in the corresponding cache memory 22a . 22b ("Cache Miss"), this command / this date is from the CPU 11 - By means of a corresponding, via the control bus of the on-chip bus 16 transferred to the appropriate storage facility 17 . 18 directed control signal, z. Block read command ("Data Block Read") - requested.

At the same time or substantially simultaneously z. B. by means of a corresponding, via the address bus of the on-chip bus 16 transmitted address signal, the address of each required command / date in the corresponding memory device 17 . 18 and / or the respective cache line address at which a "cache miss" has occurred ("start address").

As explained above, the on-chip bus 16 be a multi-master bus.

The control of the bus 16 can thus - optionally - from one of several, to the bus 16 affiliated institutions are taken over, for. B. either from the CPU 11 , or from the DMA controller 13 , or one of the above-mentioned other CPUs, etc., etc.

Each possible master has one master at the bus 16 connected - possible - masters uniquely identifying identifier assigned z. For example, a corresponding Master Tag ID.

The CPU 11 assigned identifier, in particular the assigned this master tag ID is from the CPU 11 - also z. B. via the control bus of the on-chip bus 16 - in the above requirement of not in the corresponding cache memory 22a . 22b stored, respectively required command / date z. B. together with or as part of the above block read command ("Data Block Read") (with) transfer.

As a read command signal at a "cache miss" can z. For example, as already mentioned above, a so-called "block read command signal" may be used, in particular a block read command signal corresponding to the cache line width.

The block read command signal causes not only a single one - with a present "cache miss" in the respective cache memory 22a . 22b not present (a single cache line address ("Start Address") associated) date / command is requested (eg, a single word), but each several (especially at successive addresses in the respective memory device 17 . 18 stored) data / commands, in particular so many data / commands, that the cache line can be completely rewritten with these data / commands.

For example, z. B. at a cache line width of z. B. 8 Words by means of a corresponding "8 Data Block Read" command not only a single - a single cache line address (namely the above "Start Address") associated - Word are requested, but 8 × 1 Word (or z B. with a cache line width of, for example, 16 words by means of a corresponding "16 block data block read" command 16 × 1 word, etc.).

In particular, if the case of a "cache miss" not in the respective cache memory 22a existing, required command or the above with a "cache miss" not in the respective cache memory 22b existing, required date is not at the beginning of the corresponding cache line (ie not the first of the above, several cache line addresses, ie, for example, the address "0", or - in binary terms - "000" as "Start Address "Is assigned), can - as in 2a and 2 B illustrates (see the step A shown there) - the above-mentioned block read command from the CPU 11 as a so-called "wrap-around" command (eg in the form of a corresponding "8 Data Block Read Wrap Around" command (or, for example, a "16 Data Block Read Wrap Around" command)) ,

In a "wrap around read command" - starting from the "Start Address" mentioned above - not only the "Start Address", and - until the end of the cache line - the subsequent addresses of the cache line to be assigned ( at successive addresses in the respective memory device 17 . 18 stored) data / commands are requested, but - following this - also those at the beginning of the corresponding cache line (before the "Start Address") lying cache line addresses to be assigned (at corresponding (start) addresses of the respective memory Facility 17 . 18 data / instructions to be stored (eg, in the case of a "cache miss" at the cache line address "2" (or, in binary terms, "010")), and a cache line width of e.g. 8 × 1 word - the data / instructions to be assigned to the cache line addresses 2, 3, 4, 5, 6, 7, 0, 1 (in this same order)).

Receives an interface device 12 the respective memory device 17 . 18 (in particular, for example, in the exemplary embodiment explained here, the "memory controller" used above as interface device) 12 the storage facility 18 ) the above-mentioned "Data Block Read Wrap Around" command is - as will be explained in more detail below - by a there provided (first, special) prefetch buffer device 23 Check if the by the "Wrap around read command" mentioned above (for example, the above-mentioned "8 Data Block Read Wrap Around" command) from the CPU 11 requested data / instructions not already - from previous accesses - in the prefetch buffer facility 23 are stored (see, for example, the in 2a and 2 B shown step B).

If so, the corresponding data / instructions are taken from the prefetch buffer facility 23 read out, and - via the multi-master on-chip bus 16 - to the CPU 11 or the respective cache memory 22a . 22b transferred (see below).

If this is not the case, as well as in 2a and 2 B is shown - z. B. under the control of the prefetch buffer device 23 via a corresponding memory device 17 . 18 , and the interface facility 12 (here: the "memory controller" 12 ) connecting bus 25 z. B. transmitted a corresponding, further block read command, in particular z. For example, another "wrap-around" block read command (see, for example, US Pat 2a and 2 B shown step C) (or alternatively, for example, a "continuous" block read command (see below)), together with an address of the above-mentioned respectively required command / date in the corresponding memory device 17 . 18 , and / or the above "Start Address" indicating address signal.

If a "Wrap Around" block read command is used, then this one can be compared to that of the CPU 11 / the respective cache memory 22a . 22b "Wrap around" block read command will indicate a higher number of data / instructions to be read by the command (eg, data / commands to be read by more than 3 or 7) will have a higher number of data / commands to be read, e.g. a doubled or tripled number of data / instructions to be read, etc.).

For example - at one of the CPU 11 / the respective cache memory 22a . 22b received "8 Data Block Read Wrap Around" command - a "16 Data Block Read Wrap Around" command (or, for example, a "32 Data Block Read Wrap Around" command, etc.) over the bus 25 to the respective storage device 17 . 18 be transferred (or one of the CPU 11 / the respective cache memory 22a . 22b received "16 Data Block Read Wrap Around" command z. A "32 Data Block Read Wrap Around" command, etc., etc.).

It can thus be achieved that, in addition to the data / commands directly associated with the above-mentioned cache line, the data / commands associated with the next cache line (or, for example, the two next cache lines) from the corresponding memory -Facility 17 . 18 be read out.

The corresponding data / commands are from the respective memory device 17 . 18 - Starting with the above "Start-Address" or the above memory device address, where the above (in the cache memory 22a . 22b missing) command / the above (cached 22a . 22b missing) date in the appropriate storage facility 17 . 18 is stored - read out, and over the bus 25 to the interface device 12 the respective memory device 17 . 18 (here for example: the "memory controller" 12 ) (for example, a "16 Data Block Read Wrap Around" command, and a Start Address "2" or "010" which are sent to the 16 memory device setup device). Addresses 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F, 0, 1 stored data / commands (in just this order) (see, for example, the in 2a . 2 B shown step D)).

As mentioned above, instead of the Wrap Around block read command, a Continuous Block Read command is sent over the bus 25 to the appropriate storage facility 17 . 18 transferred, all - starting with the above "Start-Address" or the corresponding, above-mentioned memory device address - in the corresponding memory device 17 . 18 stored data / commands from the corresponding memory device 17 . 18 read out, and over the bus 25 to the interface device 12 the respective memory device 17 . 18 (here for example: the "memory controller" 12 ) (eg, at a "Start Address" of "2" or "010", the memory device addresses 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F, 10, 11, 12, 13, etc. stored data / commands (in just this order)).

Once the interface device 12 (eg the "memory controller" 12 ) - in particular the above-mentioned prefetch buffer device 23 - Starting from the above "Start Address" to the "Wrap Around" (relative to that of the CPU 11 to the interface device 12 originally sent "wrap-around" command (eg the above-mentioned "8 Data Block Read Wrap Around" command)) has received the corresponding data / commands (valid) (ie, for example, one from the CPU 11 originally sent "8 Data Block Read Wrap Around" command, and a "Start Address" of "2" or "010" - the data / commands associated with addresses 2, 3, 4, 5, 6, 7) - and not only after receipt of all, as explained above, from the interface device 12 (eg the "memory controller" 12 requested data / commands (eg the data / commands assigned to the addresses 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, etc.), the corresponding data / Commands via the multi-master on-chip bus 16 to the CPU 11 (or the cache memory 22a . 22b ) (see, eg, the in 2a . 2 B shown step E).

In addition to this, instead of - in relation to that of the CPU 11 to the interface device 12 originally sent out "wrap-around" command - additionally requested (possibly the interface device 12 not yet or not yet valid), z. B. the addresses "0" and "1" associated data / commands from the interface device 12 corresponding, any "dummy data" X or "dummy commands" X via the multi-master on-chip bus 16 to the CPU 11 (or the cache memory 22a . 22b ) (in total eg, for one of the CPU 11 originally sent "8 Data Block Read Wrap Around" command, and a "Start Address" of "2" - z. B. sequentially in succession for the address 2 a corresponding one of the memory device 17 . 18 received date / command D2, for the address 3 a corresponding one of the memory device 17 . 18 received date / command D3, for the address 4 a corresponding one of the memory device 17 . 18 received date / command D4, for the address 5 a corresponding one of the memory device 17 . 18 received date / command D5, for the address 6 a corresponding one of the memory device 17 . 18 received date / command D6, for the address 7 a corresponding one of the memory device 17 . 18 received date / command D7, for the address 0, a corresponding dummy date X or a corresponding dummy command X, and for the address 1 - also - a corresponding dummy date X or a corresponding dummy command X.

How out 2a can be shown - if for the multi-master on-chip bus 16 , and the storage facility 16 identical clock frequencies are used - per clock z. For example, a date / command of the above data / commands - via the bus 25 - from the storage facility 18 to the interface device 12 be transmitted, and - also - per clock z. For example, a date / command of the above data / commands - via the multi-master on-chip bus 16 - from the interface device 12 to the CPU 11 or the cache memory 22a . 22b ,

Become - like 2 B shows - for the multi-master on-chip bus 16 , and the storage facility 16 different clock frequencies used (eg for the memory device 16 a clock frequency that is only half the clock frequency of the multi-master on-chip bus 16 ) can - based on the clock of the multi-master on-chip bus 16 - z. B. only every other clock in each case a date / command of the above data / commands via the multi-master on-chip bus 16 from the interface device 12 to the CPU 11 or the cache memory 22a . 22b be transmitted.

The above, from the CPU 11 or the corresponding cache memory 22a . 22b received data / commands (eg, the above data / commands D2, D3, D4, D5, D6, D7, X, X) are - stored at the respective cache line addresses - in the appropriate cache line.

Here are the -. B. the above addresses "0" and "1" attributable - from the interface device 12 to the CPU 11 or the cache memory 22a . 22b transmit "dummy data" or "dummy commands" in the corresponding cache line by the CPU 11 or the corresponding cache memory 22a . 22b (or a corresponding cache controller) marked as "invalid" (and the other addresses, eg the addresses 2 '', 3 '', 4 '', 5 '', 6 '', 7 '' corresponding to the corresponding cache line, from the interface device 12 to the CPU 11 or the cache memory 22a . 22b transfer data / commands as "valid").

In other words, the corresponding cache line of the o. G. "Start Address" to the end of the cache line with valid data / commands described, and from the cache line start to o. G. "Start Address" with invalid data / commands.

As soon as the date / command associated with the "Start Address" mentioned above is missing, the "Cache Miss" is triggered by the CPU 11 or the cache memory 22a . 22b received, or in the corresponding cache memory 22a . 22b was saved, the CPU can 11 continue in the above program.

As explained above, the interface device 12 (More precisely, the prefetch buffer facility 23 ) due to the above, special to the memory device 17 . 18 sent "Wrap Around" block read command (eg the above-mentioned "16 Data Block Read Wrap Around" command), or the - alternatively - sent "Continuous" block read command more data / Receive commands as - initially - as explained above via the multi-master on-chip bus 16 to the CPU 11 or the cache memory 22a . 22b be transmitted.

These data / commands - or advantageously only a part thereof, z. B. the next to the above cache line cache lines (or the respective associated addresses) associated data / commands - are in the prefetch buffer device 23 stored (eg - in the example above - the addresses assigned to the next cache line addresses 8, 9, A, B, C, D, E, F) by the interface device 12 received data / commands).

If only a portion of the received data / commands are stored, the remaining received data / commands may be received from the interface device 12 can be discarded (alternatively, the corresponding transaction from the interface device 12 be aborted accordingly early, especially if the last to be stored date / the last command to be stored has been received).

Receives the interface device 12 - again (eg a new "cache miss") - from the CPU 11 a corresponding read command, the chance is relatively good that the corresponding data / instructions in the prefetch buffer facility 23 are stored.

These can then - without prior access to the storage facility 17 . 18 - directly from the prefetch buffer facility 23 and via the multi-master on-chip bus 16 to the CPU 11 or the respective cache memory 22a . 22b be transferred (and stored in the appropriate cache line).

How out 3a and 3b are apparent in the interface device 12 - In addition to the above prefetch buffer facility 23 - One or more further prefetch buffer facilities 24 intended.

Is from the interface device 12 - via the above-mentioned multi-master on-chip bus 16 - Receive a corresponding command (eg, the above or any other read command, or eg a corresponding write command, etc.) is first checked from which of the above-mentioned several master the corresponding command was sent ,

This can be done by comparing the - as explained above with a corresponding command in each case with transmitted, sent by the respective master - master identifier, in particular the above-mentioned Master Tag ID with in the interface device 12 previously stored identifiers, in particular master tag IDs.

Is determined - on the basis of the respective identifier, in particular Master Tag ID - that the respective command (in particular, for example, the above-mentioned "8 Data Block Read Wrap Around" command) from the CPU 11 was sent, takes over the prefetch buffer facility 23 (in whole or in part) control over the data or instruction read / transmit / save process (which may then be performed as described above).

On the other hand, it is determined on the basis of the respective identifier, in particular master tag ID, that the respective command (in particular, for example, a corresponding "block read" or "block read wrap around" command) is not received from the CPU 11 but another master of the multi-master on-chip bus 16 was sent, does not inherit the prefetch buffer facility 23 but the above-mentioned further prefetch buffer device 24 (in whole or in part) control over the data or instruction readout / transfer / storage operation (which, for example, is then similar or identical to that described above, or, for example, in any other way, for example, in a conventional manner).

In particular, the further prefetch buffer device 24 in reaction z. B. on a received read command, z. For example, a "Block Read" or "Block Read Wrap Around" command, and a corresponding one, over the bus 25 to the storage facility 18 transmitted read command, in particular "block read" or "block read wrap around" command - unlike the above for the prefetch buffer device 23 first wait for the complete or at least for the respective cache line complete transfer of the corresponding data / commands, and these - only then - on the multi-master on-chip bus 16 transferred (ie without the use of - invalid - "dummy data" or dummy commands ", but only using valid, from the memory device 18 received data or commands).

LIST OF REFERENCE NUMBERS

10

Microprocessor system

11

CPU

12

Memory control means

13

DMA controller

14

bridge

15

microchip

16

Multi-master on-chip bus

17

Memory means

18

Memory means

19

On-chip bus

20

Interface means

21

Interface means

22a

Cache

22b

Cache

23

Prefetch buffer device

24

Prefetch buffer device

25

bus

Claims (6)

Interface device ( 12 ) with a prefetch buffer device ( 23 ), which on the one hand to a memory device ( 18 ) and on the other hand via a bus system ( 16 ) to a cache memory of a CPU ( 11 ), the prefetch buffer device ( 23 ) of the interface device ( 12 ) in the case of a cache miss to a data request from the CPU ( 11 ) by a first wrap-around block read command, starting from one through the CPU ( 11 ) requested start address, which is not at the beginning of a cache line, not only the subsequent associated data to the end of a respective cache line but then also the data, the other at the beginning of the corresponding cache line lying cache Are assigned in this order, is configured to perform a method with the following steps: receiving the first wrap-around block read command; Check that the data requested by the first wrap-around block read command is already in the prefetch buffer ( 23 ) are stored; if the data is stored, reading out and transferring the data to the cache memory of the CPU ( 11 ); if the data is not stored, transferring another wrap-around block read command under control of the prefetch buffer device ( 23 ) via a memory device ( 18 ) and the interface device ( 12 ), with the additional wrap-around block read command compared to the CPU ( 11 received first wrap-around block read command indicating a higher number of data to be read, so that in addition to the data associated with the cache miss directly affected cache line and the data associated with the next cache line from the memory device ( 18 ), wherein the start address of the further wrap-around block read command is the same as the start address of the first wrap-around block read command, and once the prefetch buffer device ( 23 ) has received the data valid according to the addresses starting from the start address to the address at the cache line end, these data are transferred to the cache memory of the CPU and marked there as valid, and in addition instead of not yet available data requested to the first wrap-around block read command, any dummy data is transferred to the cache memory of the CPU where it is marked as invalid, the associated data of the next cache line in the prefetch buffer device ( 23 ) are stored. Interface device ( 12 ) according to claim 1, wherein the bus system ( 16 ) is a multi-master bus system. Interface device ( 12 ) according to claim 2, comprising a determining means for determining from which master of the multi-master bus system ( 16 ) Data via the bus system ( 16 ). Interface device ( 20 ) according to claim 2 or 3, wherein the multi-master bus system is an on-chip bus. Interface device ( 12 ) according to one of the preceding claims, which is a memory controller or part of a memory controller. Microcontroller or microprocessor system ( 10 ), with an interface device ( 12 ) according to one of claims 1 to 5.

Images