DE102005016751B3 - Method for producing packaged electronic components - Google Patents

Abstract

The invention relates to a method for producing packaged electronic, in particular optoelectronic components in the wafer bundle, wherein the housing is effected by applied micro-frame structures of a glass substrate and the decomposition of the composite wafer along trenches produced in the cover substrate.

Description

Description of the invention:

The The invention relates to a method for producing packaged, electronic, in particular opto-electronic components in the wafer composite.

Background of the invention:

For the production of integrated electronic, opto-electronic or other components for microsystems Technologies have been developed that are precisely structured to produce Encapsulation or Passivierungsschichten and / or cavities (cavities) allows. The housing of opto-electronic components, which are an optical sensor or optically active elements is carried out with translucent covers, which the photosensitive elements from environmental influences, such as For example, moisture or about mechanical damage protect.

there will glass for used a variety of applications, among other things because of its optical Properties and excellent passivation properties. Compared to the for the Packaging and encapsulation of semiconductor devices commonly used Plastics have glasses, for example a significantly low permeability to air and beyond also excellent protection against water, water vapor and in particular also against aggressive substances, such as acids and bases.

so packaged Micro-components are typically associated with the Example fingerprint sensors, MEMS components, CCD cameras and scanners used. Ie. These methods are particularly suitable for packaging of devices having a sensitive area, e.g. B. an optical Sensor, which must be protected by a housing, wherein however over the housing ensure that the sensor has its external, z. B. optical, accessibility reserves.

The Manufacture of the device, the housing of the components and the Production of the connection contact to the outside is either still in Composite of a wafer (wafer-level packaging) or on the isolated Component or semiconductor chip (single-size packaging).

A Gehäusung However, the components or chips after the separation has the disadvantage that the integrated circuits and / or sensitive areas of the components while the separation are open and their function by the saw up (Dicen) of the wafer resulting dirt or dust are affected.

in the Frame of wafer level packaging is therefore z. B. in an optical active area a semiconductor device, the active area by sticking a glass or a foil on the silicon wafer protected.

The finished cut components, so-called's, must however, after dicing, ie separating the dies from the wafer, new be adjusted and aligned before the housing put on can be, resulting in additional Manufacturing steps leads and accordingly slows down production and makes it more expensive.

For the production from integrated electronic and opto-electronic or other Micro-components are now mainly different wafer-level packaging Method applied.

For example, the document describes US 53 23 051 a semiconductor wafer level package used to encapsulate a device fabricated on a semiconductor substrate wafer prior to dicing the wafer into individual chips. The document US 57 98 556 shows a sensor. A filter protects the sensory element from mechanical damage and contamination during singulation and other building up procedures.

Frequently poses This is the fundamental problem that comes with the cover used materials are difficult to structure, for example therethrough Contact connections for connection contacts provide.

To the Making holes in the housing or cover material will become common conventional techniques such as e.g. Ultrasonic lobes used, in this case, however, only relatively "big" holes can produce about 0.5 mm diameter.

in the Document WO 99/40624 A1 has already been proposed that several electrical contacts each share a hole, so that thereby the number of holes can be reduced and consequently the density of the structure can be increased. Also here However, they are still very small, and thus difficult to produce holes needed in addition the leadership multiple contact connections through a hole is complicated.

The in the patent application DE 10147648 A1 described generation of "pocket-like" structures for the generation of cavities ("caves") and Holes in a glass wafer is carried out under heating of a glass plate to its deformation temperature and shaping on a negative mold with final cooling. However, the generated structures in the range of 2-5 mm do not lead to sufficiently small structures. In addition, the surface quality of the deformed glass plate is insufficient in optical quality for high-sensitivity optical components.

Besides are photopatternable glasses, like e.g. "Foturan" available, with which is about photolithography create fine structures. The disadvantage here, however, is that these glasses one of silicon, which is usually as a carrier substrate is used, have different coefficients of expansion and a housing or cover with these glasses leads to stresses between substrate and housing.

The EP 02 80 905 B1 relates to a method of manufacturing a sensor unit from a semiconductor for absolute pressure measurement using an anodic bonding method. A silicon sensor and a silicon lid are anodically bonded at the wafer level with a layer of borosilicate glass interposed therebetween. To simplify the chipping, grooves are located on the other side of the silicon lid wafer as cutting marks.

In the DE 196 19 921 A1 a method of manufacturing a semiconductor device is illustrated. On a silicon wafer, a movable gate MOS transistor is formed. On a cap-forming silicon wafer, a projecting foot region is provided, on the lower surface of which a contacting layer consisting of a gold layer is formed. The foot region is formed by locally etching the silicon substrate.

In the US 55 00 540 For example, a package and method for packaging optoelectronic or electronic components is shown in which a plurality of chips are packaged simultaneously prior to dicing the wafer into chips.

To the final one Step of the housing and / or the contact exposure, the wafer is in individual, mostly square chips (so-called "dicing"). Typically, the dicing with a saw Cut for Cut at a feed rate of about 2 to 3 mm / min performed. Therefore can the duration of the complete Dicing a wafer on the order of a whole day lie and cause correspondingly high costs. The mechanical Properties of the passivation layers and housings can also, depending on the material, especially in glassy materials, the sawing of Additional wafers complicate and slow down.

The US 2002/0115234 A1 shows devices comprising a substrate with openings which extend through the substrate and conductors in the openings to have. wells are formed in the wafer by conventional methods such as For example, glass etching. Corresponding components are thereby positioned in the cavities. In an alternative method, distance features on the wafer surface educated. Along the entire cutting lines or scattered along cavities introduced by the cutting lines reduce the mechanical Load during of wafer dicing.

general description the invention:

The Invention has therefore set itself the task of housing and easy and flexible bondable electronic, especially opto-electronic Micro-components and a simplified and economical process for their production available to deliver.

The The object is achieved by a method according to claim 1. advantageous Further developments are the subject of the respective subclaims.

• a) Bereitstellen eines Trägersubstrates und eines Coversubstrates, jeweils mit einer Oberseite und einer Unterseite,
• b) Aufbringen der Funktionselemente auf das Trägersubstrat innerhalb vorgegebener Rasterflächen auf die Oberseite des Trägersubstrates (1),
• c) Aufbringen von Bondelementen auf das Trägersubstrat innerhalb vorgegebene Rasterbänder, welche zwischen den Rasterflächen verlaufen und Herstellen der Anschlußkontakte zwischen Funktionselementen und Bondelementen,
• d) Aufbringen einer Mikrorahmenstruktur aus Glas auf die Unterseite des Coversubstrates und/oder Oberseite des Trägersubstrates, wobei Kavitäten gemäß der Rasterflächen und Kanäle gemäß der Rasterbänder erzeugt werden und wobei im Bereich eines jeden Rasterbandes (9) je ein Graben (9) eingebracht wird und wobei die Breite des je einen Grabens (9) der Breite des Rasterbandes (8) entspricht,
• e) Einbringen einer Makrostruktur zumindest auf der Oberseite des Coversubstrates durch Abtragen von Oberflächenbereichen, wobei Gräben gemäß der Rasterbänder des Trägersubstrates erzeugt werden,
• f) Zusammenfügen von Träger- und Coversubstrat zu einem Verbundsubstrat durch Anlegen der Oberseite des Trägersubstrates (1) an die Unterseite des Coversubstrates (6), wobei die Funktionselemente gehäust werden und
• g) Trennen des Verbundsubstrates entlang einer vorgegebenen Spur innerhalb der Rasterbänder, wobei das Verbundsubstrat in einzelne Bauelemente zerlegt und gleichzeitiges die Bondelemente der vereinzelten Bauelemente freigelegt werden.

The inventive method for the production of packaged electronic components with an integrated functional element comprises the steps:

• a) providing a carrier substrate and a cover substrate, each with an upper side and a lower side,
• b) applying the functional elements to the carrier substrate within predetermined grid areas on the upper side of the carrier substrate ( 1 )
• c) applying bonding elements to the carrier substrate within predetermined grid bands which extend between the grid areas and producing the connection contacts between functional elements and bonding elements,
• d) applying a microframe structure made of glass to the underside of the cover substrate and / or top side of the carrier substrate, wherein cavities are generated in accordance with the grid areas and channels according to the grid bands and wherein in the region of each grid band ( 9 ) one ditch each ( 9 ) and the width of the one trench ( 9 ) the width of the grid band ( 8th ),
• e) introducing a macrostructure at least on the upper side of the cover substrate by removing surface areas, wherein trenches according to the grid bands of the carrier substrate he be witnessed
• f) joining carrier and cover substrate to form a composite substrate by applying the upper side of the carrier substrate ( 1 ) to the underside of the cover substrate ( 6 ), wherein the functional elements are housed and
• g) separating the composite substrate along a predetermined track within the raster bands, wherein the composite substrate is decomposed into individual components and at the same time the bonding elements of the separated components are exposed.

When Electronic components are functional elements in the sense of this invention with electrical connections Are defined. Functional elements are active semiconductor devices and / or Sensors and elements for the microelectromechanics and micro-optoelectronics.

The Process steps to f) need not necessarily executed in succession be, these can, as far as appropriate, also in parallel or in a different order accomplished become. Only process step g) is necessarily as last process step to execute.

The Specification of the grid areas and ribbons can by markings, masks, etc., but is also by a according to predetermined, for example, controllable, positioning the functional elements corresponding to an imaginary grid on the carrier substrate possible.

The Application of the bonding elements, which serve as contact surfaces for external connections Serve components, and the manufacture of internal contact between functional element and bonding elements, can preferably by Apply suitable conductive Structures on the carrier substrate respectively. These structures can, for example, with appropriate masks and coating methods such as vapor deposition or sputtering, are produced in lift-off technology. Another possible Contacting is by means of applied carrier films with prefabricated Arrangements of Flexible Metallic Film Conductors (Tape Automated Bonding), Flip-chip technology, beam-lead technology, photolithographic structuring or other methods known per se.

When carrier substrates for electronic Components are preferred semiconductor wafer, in particular of silicon used.

The Coversubstrat, with which the encapsulation in the wafer composite should, a flat semiconductor, plastic, ceramic or metal disc, preferably with a thickness of 500 to 1000 microns, include.

Especially for optical Functional elements and / or for Functional elements, for which is a hermetically sealed encapsulation of importance includes the cover substrate preferably a flat glass with a Thickness of 500 to 1000 microns. For cover substrates Substrates of borosilicate glass, e.g. Borofloat 33, because of its approximate same expansion coefficient to silicon.

The Microframe structure can be applied both to the finished carrier substrate, as well as on the cover substrate.

The micro-frame structure is produced by vapor deposition of a glass layer, which is preferably vapor-deposited and patterned through a mask. For structuring, photolithographic processes are suitable, in particular the lift-off technique, which is known in principle to a person skilled in the art. The vapor-deposited glass used is in particular a borosilicate glass, for example the vapor-deposited glass 8329 or G018-189 from SCHOTT Glas. An advantage of this method is the temperature-saving application of an insulating glass micro-frame structure at temperatures up to 150 ° C. Corresponding methods for producing a glass microstructure are in the applications DE 102 22 609 A1 the same applicant, the disclosure of which is incorporated by reference.

The Microframe structure is designed such that when joining both Substrates each functional element is enclosed by a frame and within the formed cavities and the bonding elements in areas of canals, which are formed between adjacent frames, are arranged. The structuring takes place in accordance with the arrangement of the functional elements and their bonding elements, as specified the grid areas described above and ribbons.

to Generation possible small structures on the wafer have the frame ridges of the micro-frame structure a width of 1 to 500 μm, preferably from 80 to 100 microns on. The frame size is aimed depending on the dimensions of the functional elements.

The height of Frame webs of the microframe structure mainly depends the requirements of the integrated functional elements and have preferably a height on, in which the cover substrate does not touch the functional elements. Usually are the orders of magnitude for the bridge heights in the area from 1 to 1000 μm, preferably from 3 to 10 microns.

The generation of the macrostructure on the Coversubstrat serves to reduce the substrate thickness on a given track within the grid bands, along which the finished composite substrate is to be broken down into individual components. A reduction of the glass thickness by 10 to 80% in the sawing areas later enables a considerably faster chip separation.

Preferably become trenches, the according to the channels the microstructure extend, with a width, the maximum of the width corresponds to the channels and preferably has a width of 200 to 500 microns, by material removal from the cover surface brought in. The trenches of the macrostructure introduced into the top and / or bottom of the cover substrate become.

The Generation of the macrostructure by removal of surface areas the cover substrate is preferably carried out by means of etching, sandblasting or Ultrasonic machining.

Becomes the micro-frame structure is applied to the underside of the cover substrate, the macrostructuring of the cover substrate preferably takes place subsequently.

to Encapsulation or housing design The functional elements in the wafer composite must support and Coversubstrat accordingly adjusted together become. Cavities form around the functional elements out. The bonding elements are outside these cavities, i.e. the frame structures are connected via the contacts (conductors) carried away, to an electrical connection of the housed functional element the encapsulation through to the outside sure.

Becomes the micro-frame structure is applied to the upper side of the carrier substrate, The frames around the functional elements and over the contacts away hermetically evaporated, leaving one hermetically sealed by the frame outward premier Contacting is ensured.

The Microframe structure of the top of the carrier substrate and the bottom of the cover substrate are then preferably by means of anodic bonding, Fusion bonding, sol-gel bonding, low-temperature bonding, soldering or Bonding adjusted accordingly to a composite substrate joined together. The execution of the glass copying substrate, i. with a transparent material, facilitates the adjustment considerably.

is the micro-frame structure is applied to the underside of the cover substrate, the frame can not be bonded directly to the carrier substrate, since the contacts on the carrier substrate are hermetically bridged have to. The connection to a composite substrate takes place by means of a connecting layer, which is preferably applied to the micro-frame structure. In a preferred embodiment the bonding layer is an adhesive layer, preferably of epoxy resin of which the two substrates are glued.

The Separation of the chips housed in the wafer composite is preferably carried out by exposing the channels along the trenches of the cover substrate, while exposing the bonding elements be and by separating the carrier substrate along a predetermined track, preferably along the middle of the channels runs.

The channels can by means of a saw, which preferably has a relatively large saw width (about 100 to 500 microns) or by sandblasting or ultrasonic luffing along the trenches of Macrostructure of the cover substrate are exposed. The carrier substrate is preferably by means of a saw, which is a relatively small saw width (about 100 μm) has, separately.

The Very small material thickness of the Coversubstrates in the trenches allows a significant shorter Time of the very costly sawing process.

With the method according to the invention succeeds in a simple and effective production of housed components. These have outside lying, easily accessible Bonding elements, which for conventional Technologies and bonding techniques, such as wire bonding techniques are well suited.

Farther is an electronic one with the method described above Component can be produced, which consists of a composite of a carrier substrate and a cover substrate or a composite of a carrier substrate and a cover substrate, wherein on the carrier substrate at least one functional element and at least one with the functional element contacted bonding element is arranged, the cover substrate is microstructured glass, which is arranged on the carrier substrate and over the functional element a cavity forms and the bonding elements outside the cavity on the carrier substrate are located.

The carrier substrate preferably comprises silicon. This shows the cover and carrier substrate an approximate same coefficients of expansion, causing no tension comes between the substrates.

The cover substrate forms the housing of the functional element and is due to its physical properties particularly for the housing of sensory active and optically active functional elements suitable.

By suitable joining technologies, as described for example in the method according to the invention, can also a dense network between carrier and cover substrate can be achieved.

to Formation of a cavity in the cover substrate, which is the functional element located on the carrier substrate housings should, the cover substrate is preferably made of a flat glass sheet with a vapor-deposited micro-glass frame. Possible procedures for producing such micro-frames are also in the process of the invention described.

electronic Components are intended for many applications be made in small dimensions. In an advantageous embodiment the glass sheet has a thickness of 500 to 1000 microns, the frame webs the micro-glass frame a width of 1 to 500 μm, preferably from 80 to 100 microns and a height from 1 to 1000 microns, preferably from 3 to 10 μm on.

The outside the housing lying and freely accessible Bonding elements comprise in a further advantageous embodiment Wire-bonding or solderable bond pads of the invention. As possible Materials for Bond pads are preferably Au, Al, TiCu, AlSiCu or AlSiTi for use.

Usual bonding methods are, for example, wire-bonding with thermocompression methods, Thermocompression bonding with gold bumps, ultrasonic wire bonding, Thermosonic wire bonding or soldering with solder bumps. Just the case off Glass makes the use of these bonding methods sensitive, in particular also temperature-sensitive functional elements possible. The contacting and the joining together the components of the invention to assemblies (packaging) and micro-systems thereby becomes industrial common and modern manufacturing technologies such as the tape-automated bonding or flip-chip bonding possible.

In a further advantageous embodiment, the electronic component comprises a on the underside of the carrier substrate ( 1 ) arranged heat-dissipating base substrate, preferably of silicon. The carrier substrate and the base substrate are attached to each other by means of adhesive or soldered connections. The heat-dissipating substrate may simultaneously form the base substrate for further components and / or assemblies.

In a further advantageous embodiment of the electronic Component are applied to the bonding elements Lotbumps, which the carrier substrate with bottom side bonding elements having an opening for the housed functional element connect provided base substrate. The solderbumps are small, electrically conductive material depots over which both the electrical as well as mechanical and / or thermal connection between carrier and base substrate will be produced. Will the solder bumps between the bond pads of the Melted substrates, for example by means of reflow technology, there is a self-aligning, stress-free connection of Substrates. The base substrate is for example part of an optical assembly, within that the housing Functional element, in particular with an optical function to arrange is.

According to the invention optical assemblies a base substrate having an opening and lower-side bond pads, an optical component, for example a lens, which is above the opening arranged and connected to the base substrate and a housed electronic Component which has at least one optically sensitive functional element includes. The base substrate has defined solderable bond pads on its underside, allowing the electronic component below the opening can be attached. The connection between the base substrate and electronic component is a molten solder bumps, which is between the bond pads of the base substrate and the bond pads of the electronic component, manufactured, finely centered Connection. this makes possible a precisely centered and extremely dense Arrangement of the optical component, for example a lens for electronic component.

such Optical assemblies are mainly used in digital cameras.

The The invention will be explained in more detail with reference to exemplary embodiments. It show:

1.a. a plan view of a carrier substrate,

1.b an enlarged section of the carrier substrate,

1.c a sectional view of the carrier substrate 1.b along the section line S1,

2.a a plan view of a carrier substrate with functional elements,

2 B a sectional view of the carrier substrates 2.a along the section line S2,

3.a a plan view of a carrier substrate with functional elements and bonding elements,

3.b a sectional view of the carrier substrate 3.a along the section line S3,

4.a a plan view of a carrier substrate with connection contacts between functional elements and bond pads,

4.b a sectional view of the carrier substrate 4.a along the section line S4,

5.a a view of the underside of a cover substrate

5.b a sectional view of the cover substrate 5.a along the section line S5,

6.a a view of the underside of a cover substrate with micro-frame structure,

6.b a sectional view of the cover substrate 6.a along the section line S6,

7.a a top view of the cover substrate with raster bands for the macrostructure,

7.b a sectional view of the cover substrate 7.a along the section line S7,

8.a a top view of the cover substrate with trenches for the macrostructure,

8.b a sectional view of the cover substrate 8.a along the section line S8,

9.a a top view of the composite substrate,

9.b a sectional view of the composite substrate 9.a along the section line S9,

10.a a top view of the composite substrate with exposed bonding elements,

10.b a sectional view of the composite substrate 10.a along the section line S10,

10.c a sectional view of the composite substrate 10.a along the section line S11,

11.a a plan view of the separate composite substrate,

11.b a sectional view of the composite substrate 11.a along the section line S12,

12 a housed electronic component

13 a sectional view of a composite substrate with protected bonding elements,

14 a sectional view of the composite substrate 13 after exposing the bonding elements,

15 a sectional view of a composite substrate with double-sided macrostructure of the cover substrate

16 a sectional view of a composite substrate with micro-frame structure of the carrier substrate

17 a sectional view of a wire-bonded electronic component

18 a sectional view of a wire-bonded electronic component on a base substrate

19 a sectional view of a solder-packaging device

20 a sectional view of an optical assembly

Production of the carrier substrate:

1.a. shows a wafer in the embodiment that the carrier substrate ( 1 ) is made of silicon. On the surface F1 of the carrier substrate ( 1 ) is a grid in the form of grid surfaces ( 2 ).

The grid surfaces ( 2 ) do not have to be real on the surface F1. They rather symbolize the arrangement of the functional elements ( 3 ), which in the further process steps described below on the surface F1 of the carrier substrate ( 1 ) are applied. It should also be noted that the grid surfaces ( 2 ) in a different arrangement and shape on the surface F1 of the carrier substrate ( 1 ) can be arranged. However, in this particular embodiment, the aligned arrangement of the bonding elements ( 4 ) between the functional elements ( 3 ) and the dicen of the wafer, for example by means of sawing, particularly easy to carry out, since the sawing can be done in straight paths.

1.b shows the in 1.a. marked section Z in an enlarged view with the predetermined screening. 1.c is a schematic representation of 1.b along the section line S1.

Referring to 2.a are on the surface F1 of the carrier substrate ( 1 ) the functional elements ( 3 ) with methods known to those skilled in the art, for example by means of bonding or adhesive bonds, within or on the predetermined grid surfaces ( 2 ) applied. Possible embodiments of the functional elements ( 3 ) are, for example, micro-opto-electronic, micro-opto-electro-mechanical, electronic systems (MOEMS), eg (organic) light-emitting and -absorbing sensors ((O) LED). Further, even if not explicitly mentioned embodiments of the functional elements ( 3 ) are included. 2 B is that too 2.a corresponding representation along the section line S2.

Referring to 3.a are on the surface F1 of the carrier substrate ( 1 ) Bonding elements ( 4 ), so-called bond pads, within the given grid bands ( 8th ) applied. 3.b is that too 3.a Corresponding illustration along the section line S3. The position of the bonding elements ( 4 ) is preferably chosen so that these are in a regular arrangement, closely spaced from the functional element ( 3 ) and between the bonding elements ( 4 ) of various functional elements ( 3 ) remains a straight track for the subsequent separation of the components.

As in 4.a shown are the connection contacts ( 5 ) between the functional elements ( 3 ) and the bonding elements ( 4 ) on the surface F1 of the carrier substrate ( 1 ) vapor-deposited conductor tracks made of aluminum. Alternatively, the connection contacts ( 5 ) also include gold, tungsten or titanium tungsten. 4.b is that too 4.a corresponding representation along the section line S4.

The method steps described separately, application of the bonding elements ( 4 ) and applying the connection contacts ( 5 ), can also take place in one process step. Ie in a further embodiment not shown here in detail, the connection contact ( 5 ) thus directly the bonding element ( 4 ).

The skilled person it is obvious that in the 2 . 3 and 4 described method steps can also take place in a changed order.

Preparation of the Coversubstrate:

5a shows a section (analogous to the section Z of the carrier substrate ( 1 ) in the 1 - 4 ) of the cover substrate ( 6 ) with its underside F2. The cover substrate ( 6 ) is made of glass and thereby in its thermo-mechanical properties to the carrier substrate ( 2 ) customized. 5.b is that too 5.a corresponding representation along the section line S5 and shows in addition to the bottom F2 of the cover substrate additionally its top F3.

6a shows the same section of the cover substrate ( 6 ) as in 5 after application of the micro-frame structure ( 7 ) of glass on the underside F2 of the cover substrate ( 6 ). 6.b is that too 6.a corresponding representation along the section line S6.

The manufacture of the micro-frame structure ( 7 ) is not explicitly shown in the figures, but is outlined below.

On the underside F2 to be structured, a photoresist is applied by a method known to those skilled in the art and patterned photolithographically. For generating the microstructure structures ( 7 ), a shadow mask, an adhesive mask or a non-adhesive mask can be used. The underside F2 then has, analogously to the screening, around each grid area ( 2 ) on a rectangular recess for the trainee frame. The later housing surface is covered by the mask. Within the recesses of the mask, the glass is directly on the cover substrate ( 6 ) deposited. The glass layer is deposited by, for example, plasma ion beam assisted electron beam evaporation. Subsequently, the areas of the vapor-deposited glass layer located on the resist mask are removed by means of a lift-off. For this purpose, the photoresist is peeled off in acetone. The deposited glass in the areas of the recesses of the photomask forms the desired microstructure ( 7 ).

6.a and 6.b show a section of the cover substrate ( 6 ) after application of the micro-frame structure ( 7 ).

Referring to 7 are on top F3 of the cover substrate ( 6 ) the vertical and horizontal grid bands ( 8th ), which lie between the grid surfaces ( 2 ) of the carrier substrate ( 1 ), marked. Within these raster bands ( 8th ), the removal of surface areas to produce the macrostructure of the cover substrate ( 6 ). 7.b is that too 7.a Corresponding illustration along the section line S7.

On top F3 of the cover substrate ( 6 ) with a subtractive method, for example with an ultrasonic vibration lapping method, in the area of the grid bands ( 8th ) Depressions or trenches ( 9 ) generated. Since the subtractive method only in the area of the raster bands ( 8th ), ie outside the "field of view" of the functional elements ( 3 ), at is used, the optical function / quality of the cover substrate ( 6 ) receive. 8.a shows that with the trenches ( 9 ) provided with Coversubstrat and 8.b a corresponding sectional view of the micro- and macrostructured Coversubstrats ( 6 ) along the section line S8.

Of course, the order of the individual process steps can be changed. For example, the trenches ( 9 ) of the macrostructure on top F3 of the cover substrate ( 6 ) before vapor deposition of the microstructure ( 7 ) on the underside F2 of the cover substrate ( 6 ) be generated.

Making the composite substrate:

The microstructured underside F2 of the cover substrate ( 6 ) is opposite the top F1 of the carrier substrate ( 1 ) are positioned and aligned according to the screening. Referring to 9 be the micro- and macrostructured cover substrate ( 6 ) and the carrier substrate ( 1 ) with the functional element ( 3 ) and contacted bonding elements ( 4 ) are joined together to form a composite substrate and attached to the underside of the microstructure ( 7 ) via a bonding surface ( 10 ) connected with each other. For bonding, for example, an epoxy adhesive is applied to the bonding surface ( 10 ) applied. Due to the height of the frame of the microframe structure ( 7 ) cavities ( 11 ) and channels ( 17 ) between carrier substrate ( 1 ) and cover substrate ( 6 ). Within the cavities ( 11 ) are the functional elements ( 3 ), within the channels ( 17 ) are the bonding elements ( 4 ). The result is a variety of functional elements ( 3 ), which are housed at the wafer level. 9.b is that too 9.a appropriate representation along the section line S9.

Separation of the components:

In the final process step, the sawing of the composite substrate takes place. The sawing of the composite substrate is effected by dicing the cover substrate ( 6 ) and dicen of the carrier substrate ( 1 ) and can take place in a single step or in successive steps.

Referring to 10.a becomes the cover substrate ( 6 ) along the in 9.a shown trenches ( 9 ) of the macrostructures in vertical and horizontal tracks by means of saws with a saw width, the width of the trenches ( 9 ), opened. Opening the macrostructure in one step through the open area ( 14 ) in the cover substrate ( 6 ) the bonding elements ( 4 ) and in the non-opened area each functional element ( 3 ) with a housing ( 13 ) surround. 10.b is that too 10.a corresponding representation along the section line S10. 10.c is that too 10.a appropriate representation along the section line S11. Referring to 11.b the dicen of the carrier substrate ( 1 ) with a much smaller saw width in the opening area ( 14 ) of the carrier substrate ( 1 ). The saw track is characterized by the division of the functional elements ( 3 ) and bonding elements ( 4 ) is predetermined on the carrier substrate and preferably runs on straight lines, centered within the grid bands (FIG. 8th ). 11.b is that too 11.a corresponding representation along the section line S12.

12 shows a housed electronic component ( 15 ) with integrated functional element ( 3 ).

Variants:

Next the described embodiment a variety of other variants are possible, some of which are exemplary listed below become.

According to 13 may be prior to the assembly of carrier and cover substrate ( 1 . 6 ) the bonding elements ( 4 ) with a temporary protective layer ( 16 ) are coated. The protective layer ( 16 ) prevents the dust and dirt particles formed during sawing from disturbing the bonding elements ( 4 ) and thus can impair their functionality. To expose the bonding elements ( 4 ) the protective layer ( 16 ) after the wafer has been diced, eg by etching.

Another embodiment according to the 14 can also be that another "sawing" is used, which leads to another, here eg rectangular edge shape of the housing ( 13 ) can lead.

Out 15 Still another embodiment can be seen in which both on the top F3 trenches ( 9 ) and the underside F2 of the cover substrate ( 6 ) Trenches ( 18 ) are generated for macro structuring.

Another embodiment in the sense of 16 could also be that the upper side F1 of the carrier substrate ( 1 ) with the micro-frame structure ( 7 ), the underside F2 of the cover substrate ( 6 ) untreated and only the top F3 of the cover substrate ( 6 ) has a macrostructure.

17 shows a housed electronic component ( 15 ) with over the connections ( 5 ), outside the cavity ( 11 ), bonding elements ( 4 ). The bonding elements are as solderable bonding elements ( 4 ) formed by means of soldering a wire ( 19 ) for contacting other not shown in the drawing components are attached can.

18 shows a housed electronic component ( 15 ), which on the underside of the carrier substrate ( 1 ) by means of an adhesive or soldered connection ( 20 ) on a heat-dissipating base substrate ( 21 ) is arranged.

In a further embodiment shows 19 a housed electronic component ( 15 ) with over the connections ( 5 ), outside the cavity ( 11 ), bonding elements ( 4 ). On the bonding elements ( 4 ) are solder bumps ( 22 ) applied. These are advantageously formed of tin. When connected to a base substrate ( 23 ), on which Bondpads ( 4 ) are applied, which in a corresponding, highly accurately positioned arrangement to the bond pads ( 4 ) of the carrier substrate ( 1 ), by means of reflow technique, in which the solder bumps are heated and melted, a self-aligning, finely centered arrangement of the substrates ( 1 . 23 ) to each other.

20 shows the section of an optical assembly with a packaged electronic component ( 15 ). This is opposite to an optical component ( 25 ), for example a lens. The optical component ( 25 ) is by means of a suitable holder ( 24 ) on the base substrate ( 23 ) attached.

The electronic component ( 15 ) is also on the base substrate ( 23 ) attached. The compound has been prepared as described above, using reflow technology. Thus, the optical component ( 25 ) and the optical sensor ( 3 ) extremely precisely adjusted to each other and centered. The very dense arrangement of the lens to the optical sensor ( 3 ) also enables improved resolution of an optical signal.

It It will be apparent to those skilled in the art that those described above embodiments by way of example, and the invention is not to be understood limited is, but in more diverse Way can be varied without departing from the spirit of the invention.

1

carrier substrate

2

grid area

3

functional element

4

Bond element

5

connection contact (between functional element and

Bond element)

6

Cover substrate

7

Micro frame structure

8th

Rasterband

9

dig (on top F3 of the cover substrate)

10

Bonding surface, Bondpad

11

cavity

12

opening area of the cover substrate

13

casing

14

opening area of the carrier substrate

15

single module

16

protective layer the bonding elements

17

channel

18

dig (on the bottom F2 of the cover substrate)

19

wire

20

Adhesives braze joint

21

heat dissipating base substrate

22

solder bumps

23

base substrate

24

bracket

25

optical Component, lens

Z

Magnified clipping area of the carrier substrate

F1

top of the carrier substrate

F2

bottom of the cover substrate

F3

top of the cover substrate

S1

intersection carrier substrate

S2

intersection carrier substrate

S3

intersection carrier substrate

S4

intersection carrier substrate

S5

intersection Cover substrate

S6

intersection Cover substrate

S7

intersection Cover substrate

S8

intersection Cover substrate

S9

intersection composite substrate

S10

intersection composite substrate

S11

intersection composite substrate

S12

intersection composite substrate

Claims (22)

Method for producing packaged electronic components ( 15 ) with an integrated functional element ( 3 ), comprising the steps of: a) providing a carrier substrate ( 1 ) and cover substrates ( 6 ), each with an upper side and a lower side, b) applying the functional elements ( 3 ) on the carrier substrate ( 1 ) within predefined grid areas ( 2 ) on the top side of the carrier substrate ( 1 ), c) application of bonding elements ( 4 ) on the carrier substrate ( 1 ) within predetermined raster bands ( 8th ), which between the grid surfaces ( 2 ) and establishing the connection contacts ( 5 ) between functional elements ( 3 ) and bonding elements ( 4 ), d) applying a micro-frame structure ( 7 ) made of glass on the underside of the cover substrate ( 6 ) and / or top side of the carrier substrate ( 1 ), where cavities ( 11 ) according to the grid areas ( 2 ) and channels ( 17 ) according to the grid bands ( 8th e) introducing a macrostructure at least on the Top side of the cover substrate ( 6 by removing surface areas, wherein trenches ( 9 ) according to the grid bands ( 8th ) of the carrier substrate ( 1 ) and wherein in the region of each raster band ( 9 ) one ditch each ( 9 ) and the width of the one trench ( 9 ) the width of the grid band ( 8th ), f) assembly of carrier and cover substrate ( 1 . 6 ) to a composite substrate by applying the top side of the carrier substrate ( 1 ) to the underside of the cover substrate ( 6 ), wherein the functional elements ( 3 ) and g) separating the composite substrate along a predetermined track within the raster bands ( 8th ), wherein the composite substrate into individual components ( 15 ) and at the same time the bonding elements ( 4 ) of the isolated components ( 15 ) are exposed. Method according to claim 1, characterized in that as support substrate ( 1 ) is provided a semiconductor wafer. Method according to Claim 2, characterized in that the carrier substrate ( 1 ) is provided a semiconductor wafer of silicon. Method according to one of the preceding claims, characterized in that the application of the functional elements ( 3 ) the application of active semiconductor functional elements ( 3 ). Method according to one of the preceding claims, characterized in that the application of the functional elements ( 3 ) the application of sensory active functional elements ( 3 ). Method according to one of the preceding claims, characterized in that the application of the functional elements ( 3 ) the application of optically active functional elements ( 3 ). Method according to one of the preceding claims, characterized in that as a cover substrate ( 6 ) is provided a flat semiconductor, plastic, ceramic or metal disc with a thickness of 500 to 1000 microns. Method according to one of the preceding claims, in particular according to claim 6, characterized in that as a cover substrate ( 6 ) is provided a flat glass plate with a thickness of 500 to 1000 microns. Method according to one of the preceding claims, characterized in that the frame webs of the microstructure ( 7 ) are applied with a width of 1 to 500 microns, preferably from 80 to 100 microns. Method according to one of the preceding claims, characterized in that the frame webs of the microstructure ( 7 ) are applied with a height of 1 to 1000 microns, preferably from 3 to 10 microns. Method according to one of the preceding claims, characterized in that the application of the micro-frame structure ( 7 ) the steps - applying a mask, which the micro-frame structure ( 7 ), - vapor deposition of a glass layer and - removal of the mask by means of the lift-off technique. Method according to one of the preceding claims, characterized in that the trenches ( 9 ) of the macrostructure having a width of 5 to 1000 microns, preferably from 200 to 500 microns are introduced. Method according to one of the preceding claims, characterized in that in the region of the trenches ( 9 ) of the macrostructure the thickness of the cover substrate ( 6 ) is reduced by 10 to 80%. Method according to one of the preceding claims, characterized in that the trenches ( 9 ) of the macrostructure on the top and bottom of the cover substrate ( 6 ) are introduced. Method according to one of claims 12 to 13, characterized in that the introduction of a macrostructure by removal of surface regions of the cover substrate ( 6 ) by means of etching, sandblasting or Ultraschallschwingläppen done. Method according to one of the preceding claims, characterized in that the microstructure ( 7 ) on the underside of the cover substrate ( 6 ) is applied. Method according to claim 16, characterized in that the microstructure ( 7 ) an adhesive layer is applied, preferably of epoxy resin, and the upper side of the carrier substrate ( 1 ) with the micro-frame structure ( 7 ) of the underside of the cover substrate ( 6 ) is glued to a composite substrate. Method according to one of the preceding claims, characterized in that the microstructure ( 7 ) on the top side of the carrier substrate ( 1 ) is applied. Method according to claim 18, characterized in that the microstructure ( 7 ) of the top side of the carrier substrate ( 1 ) and the underside of the cover substrate ( 6 ) using anodic bonding, fusion bonding, sol-gel bonding, low-temp rature bonding, soldering or gluing together to form a composite substrate. Method according to one of the preceding claims, characterized in that the composite substrate by exposing the channels ( 17 ) along the trenches ( 9 ) of the cover substrate ( 6 ) and by separating the carrier substrate ( 1 ) along the predetermined track, which are centered in the channels ( 17 ), is disassembled. Method according to claim 20, characterized in that the channels ( 17 ) by sawing, sandblasting or Ultraschallschwingläppen the cover substrate ( 6 ) along the trenches ( 9 ) are exposed. Method according to claim 20, characterized in that the carrier substrate ( 1 ) is separated by sawing.