DE102005025116B4 - Method for producing a structure - Google Patents

Abstract

A method of fabricating a structure (125) wherein an oxide (60, 160, 200) is etched by means of an etching gas using as the etching gas a gas mixture comprising at least one CHxFy-containing gas, where x is greater than or equal to zero and y is greater than or equal to 1, further comprising a portion of one or more of the components selected from C3F8, C4F6 or C4F8, and containing an amount of oxygen, wherein an oxide (160) immediately adjacent to a nitride (140) is etched as the oxide and etching a hole (350) during etching, wherein the sidewalls of the hole are completely or partially confined by the nitride (140).

Description

The invention relates to a method for producing a structure in which an oxide is etched with the aid of an etching gas.

Such methods are common, for example, in the field of semiconductor technology to produce microprocessors, memory elements or the like. For example, gases based on fluorine are used as the etching gases.

From the US 2003/0042465 and from the U.S. Patent 6,387,287 In each case, an etching gas mixture for etching a doped oxide layer, which is arranged above a silicon nitride layer, known. In the U.S. Patent 6,074,959 For example, a plasma etching method for etching an oxide film will be described. In the U.S. Patent 5,037,777 For example, a method of selectively planarizing a dielectric layer disposed over an underlying dielectric layer is described. Further structuring methods are from the DE 103 11 691 , of the U.S. Patent 6,544,883 as well as the U.S. Patent 5,286,344 known.

The invention has for its object to improve a method of the type described in such a way that during the oxide etching a particularly large Ätzselektivität against nitrides, especially against silicon nitrides, is achieved.

This object is achieved by the method according to claim 1.

A significant advantage of the invention is that due to the use of a gas containing at least carbon and fluorine in the etching of the oxide, for example, polymers or polymer chains are formed, which at least reduce the etching attack on nitrides, whereby a large Ätzselektivität is achieved.

It is considered preferable that the value of x is 1 or more than 1, because in this case, due to the presence of hydrogen, CH polymer chains are formed, whereby the etching selectivity becomes particularly large.

Preferably, an etching gas is used in which the atoms are arranged in a linear chain structure. A linear chain structure is understood in particular to mean a longitudinally stretched or ring-shaped structure.

A large etch selectivity over a nitride is particularly advantageous if the oxide to be etched is directly adjacent to a nitride during the etching process. Accordingly, use is made of the described method if, during the etching, the etching gas also comes into contact with a nitride which directly adjoins the oxide to be etched.

During the etching process, a hole is etched with the sidewalls of the hole being wholly or partially confined by the nitride.

The etching gas used is preferably a gas mixture which contains at least one gas from the group CH ₃ F, CH ₂ F ₂ , CHF ₃ , and which furthermore contains a proportion of one or more of the components selected from C ₃ F ₈ , C ₄ F ₆ or C ₄ F ₈ and contains a proportion of oxygen.

Preferably, a contact hole is etched as a hole. In the contact hole, for example, a connection contact or a connection electrode for a transistor can be formed.

Particularly preferably, at least two contact holes are etched, wherein in one of the two contact holes, a source terminal contact of the transistor and in the other contact hole, a drain terminal contact of the transistor is formed.

The nitride is preferably arranged such that it protects the gate terminal-that is, the contact material of the gate contact-of the transistor directly or indirectly from the etching gas.

In addition, an oxide may be disposed between the nitride and the gate terminal of the transistor, which has some sort of separation function and could be termed a separation oxide.

Preferably, the thickness of the nitride in the sidewall region of the gate terminal, in particular in the upper shoulder region of the gate terminal, is selected to be so thick that no holes can be etched into the nitride during the etching of the oxide. Short circuits between the gate terminal and the source and / or drain terminal are thus avoided.

Preferably, the contact holes for the source terminal and the drain terminal of the transistor are made self-adjusting relative to the gate terminal in order to achieve an optimal adjustment of the terminals, especially in small structures.

For example, the transistor may be fabricated in a raised region of a silicon substrate.

The method described is preferably used for the production of DRAM memory elements in which a transistor forms an integral part. Also, the method described can be used for the production of microprocessors.

The invention will be explained below with reference to an embodiment. The show 1 to 14 exemplary method steps for producing a DRAM memory element with field effect transistors and with self-adjusting connection contacts.

In the 1 can be seen in plan view, a silicon substrate 10 that in surface sections 20 was etched such that raised areas 30 to remain uneaten. The resulting structure is then over the entire surface with an oxide 40 coated and subjected to a CMP (CMP: chemical mechanical polishing) step. Subsequently, the oxide 40 etched wet-chemically, so that the surfaces 50 the sublime areas 30 from the oxide 40 be freed.

The resulting structure is in cross section (section AA according to the 1 ) in the 2 shown. One recognizes the raised areas 30 as well as the oxide 40 liberated surfaces 50 the sublime areas 30 , Between the sublime areas 30 is the oxide 40 that the sublime areas 30 separates each other.

The surfaces 50 the sublime areas 30 are in a subsequent processing step to form a gate oxide 60 which oxidizes an essential constituent for the field effect transistors of the DRAM memory element to be produced in the further. The resulting structure then becomes a heavily doped polysilicon layer 70 a tungsten silicide layer 80 , a nitride layer 90 and a photoresist layer 100 applied. As will be apparent below, the highly doped polysilicon layer becomes 70 and the tungsten silicide layer 80 serve as a gate contact material for the gate terminals of the aforementioned field effect transistors.

The resulting layer package is in cross section in the 3 shown. The photoresist layer 100 is structured as described in the 4 is shown in plan view. In this structuring remain bar-shaped photoresist strips 110 stand, which cover the layer package; the remaining areas are from the photoresist layer 100 freed. These free areas are subjected to an etching step in which the nitride layer 90 , the tungsten silicide layer 80 and the heavily doped polysilicon layer 70 to the gate oxide 60 be etched away (cf. 5 ). By this etching step, the gate terminals become 120 the field effect transistors 125 Are defined. The highly doped source and drain regions of the field effect transistors 125 in the sublime area 30 of the silicon substrate 10 are integrated in the monolithic 5 not explicitly drawn for reasons of clarity.

Subsequently, the resulting structure is subjected to an oxide coating process in which the sidewall regions 130 the structured tungsten silicide and polysilicon layer 70 respectively. 80 and thus the sidewall areas 130 the gate connections 120 be coated. The on the sidewall areas 130 applied oxide layer is in the 5 with the reference number 135 characterized. Subsequently, a silicon nitride spacer (spacer: thick layer) on the thus treated structure becomes mainly on the sidewall portions 130 and a silicon nitride liner (liner: thin layer) deposited over the entire structure. The silicon nitride spacer and the silicon nitride liner are together with the reference numeral 140 characterized.

The resulting structure shows the 5 in cross section. It can be seen that, despite the deposition of the silicon nitride spacer and the silicon nitride liner 140 separating regions 150 between the gate terminals 120 the field effect transistors 125 remain.

The 6 shows the structure according to 5 in the plan view before the application of the silicon nitride spacer and the silicon nitride liner 140 so that the exposed areas of the gate oxide 60 , the exposed areas of the oxide 40 and the unetched nitride layer 90 are still visible from above.

In the 7 the resulting structure is shown after in the separation areas 150 between the transistors 125 a borophosphosilicate glass 160 - So an oxide - was filled. As reflected in the 7 is boron-phosphorus silicate glass 160 from the gate oxide 60 through the silicon nitride liner 140 separated so that boron and / or phosphorus from the boro-phosphorous-silicate glass 160 neither in the gate oxide 60 still in the silicon substrate 10 can diffuse out.

After filling the separation areas 150 with the borophosphosilicate glass 160 For example, the structure is subjected to a CMP step, and then the resulting structure becomes an oxide 200 , For example, a LPCVD oxide or a LPTEOS oxide, over the entire surface covered. On this oxide 200 becomes an amorphous silicon layer 210 deposited with a photoresist mask 220 is coated. The 7 shows the photoresist mask 220 after a structuring step in which in the photoresist mask 220 circular areas 230 were uncovered.

The photoresist mask 220 is in the 8th shown in plan view; one recognizes in particular the circular areas 230 ,

In the 9 the resulting structure is shown in cross-section, after in the circular areas 230 the amorphous silicon layer 210 was opened and another photoresist mask 250 was applied. In the 9 is the further photoresist mask 250 shown after oval opening holes 260 in the further photoresist mask 250 have been introduced. The oval opening holes 260 are in the 10 shown again in plan view.

In a subsequent etching step, the amorphous silicon layer 210 in the area of the oval opening holes 260 etched, creating an amorphous silicon etching mask 270 is formed ( 11 ). In the 11 is the layer package after removal of the further photoresist layer 250 shown in cross section; the 12 shows the silicon etching mask 270 in the plan view.

The silicon etching mask 270 has thus been produced in two processing steps, alternatively, the etch mask 270 also be formed in a single manufacturing step.

The layer package is then subjected to an etching step in which the silicon etching mask 270 acts as a mask. In the context of this etching step, the oxide 200 , the boro-phosphorous-silicate glass 160 as well as the gate oxide 60 under the formation of contact holes 350 (see. 13 ) etched away. To ensure in this process step that the silicon nitride spacer and the silicon nitride liner 140 that the gate connections 120 In the etching process, an etching gas and etching process with the following parameters is preferably used in the etching: Print: 45 +/- 15 mT Temperature: Top / Wall / Bottom = 60/60/60 deg C each +/- 30 ° C Top Power: 2000 +/- 500 W Bottom Power: 2500 +/- 500 W Gas flow: C ₄ F ₆ / C ₃ F ₈ / CH ₃ F: 15 +/- 10 sccm O ₂ : 25 +/- 15 sccm C ₅ F ₈ : 20 +/- 10 sccm

Important in this oxide etching step is that in the upper "shoulder area" 310 the gate connections 120 always silicon nitride 140 with a sufficient thickness, so that an electrical insulation between the gate terminals 120 and the source and drain terminals of the transistors to be produced below 125 remains.

In the 13 the structure is shown after the via holes made during the oxide etch step 350 have been filled with a conductive material, such as a highly doped polysilicon material. The filler carries in the 13 the reference number 400 and forms the material for the source and drain terminal contacts 410 the otherwise only schematically indicated transistors 125 in the raised silicon area 30 ,

The circular contact holes seen in plan view 350 (see. 14 ) are preferably used to connect the transistors 125 used on capacitors in which the information to be stored by the DRAM memory device is stored in the form of stored charges; the oval contact holes in plan view 350 are preferably used to connect the transistors to a bit line of the DRAM memory module.

In summary, it can be stated that the etch parameters described during the etching of boron-phosphorus silicate glass 160 , the gate oxide 160 and the oxide 200 it is ensured that the the gate connections 120 protective nitride layer 140 at least as far as preserved, that no short circuits between the gate terminals 120 and the source and drain terminal contacts 410 may occur.

LIST OF REFERENCE NUMBERS

10

silicon substrate

20

surface sections

30

sublime areas

40

oxide

50

Surface of the raised areas

60

gate oxide

70

highly doped polysilicon layer

80

tungsten silicide

90

nitride

100

Photoresist layer

110

bar-shaped photoresist strips

120

Gate terminal

125

FETs

130

Sidewall portions

135

oxide

140

Silicon nitride spacer and liner

150

separating region

160

Boron phosphorus silicate glass

200

oxide

210

amorphous silicon mask

220

Photoresist mask

230

circular areas

250

further photoresist mask

260

oval opening holes

270

etching mask

300

Gate electrodes

310

shoulders

350

vias

400

filling material

410

Source or drain connection contacts

Claims (11)

Method for producing a structure ( 125 ), in which with the aid of an etching gas, an oxide ( 60 . 160 . 200 ), wherein the etching gas used is a gas mixture which comprises at least one CH _x F _y -containing gas, where x is greater than or equal to 0 and y greater than or equal to 1, furthermore a proportion of one or more of the components selected from C ₃ F ₈ , C ₄ F ₆ or C ₄ F ₈ , and contains a proportion of oxygen, wherein as oxide one directly to a nitride ( 140 ) adjacent oxide ( 160 ) and etching a hole during etching ( 350 ), wherein the side flanks of the hole through the nitride ( 140 ) be limited in whole or in part. A method according to claim 1, characterized in that as a hole a contact hole 350 ) is etched and in the contact hole a connection contact ( 410 ) for a transistor ( 125 ) is formed. Method according to claim 2, characterized in that at least two contact holes ( 350 ), wherein in one of the two contact holes, a source terminal contact ( 410 ) of the transistor ( 125 ) and in the other contact hole ( 350 ) a drain terminal contact ( 410 ) of the transistor is formed. Process according to claim 2 or 3, characterized in that the nitride ( 140 ) is arranged such that it connects the gate terminal ( 120 ) of the transistor ( 125 ) protects directly or indirectly. Process according to claim 4, characterized in that between the nitride ( 140 ) and the gate terminal ( 120 ) of the transistor is an oxide ( 135 ) is arranged. Method according to one of claims 2 to 5, characterized in that the thickness of the nitride ( 140 ) in the sidewall area ( 130 ) of the gate terminal ( 120 ), especially in the upper shoulder area ( 310 ) of the gate terminal is chosen to be so thick that in this case the etching of the oxide ( 160 ) no holes are etched. Method according to one of claims 2 to 6, characterized in that the contact holes ( 350 ) for the source terminal contact and the drain terminal contact of the transistor ( 125 ) are made self-adjusting relative to the gate terminal. Method according to one of claims 2 to 7, characterized in that the transistor ( 125 ) in a raised area ( 30 ) of a silicon substrate ( 10 ) will be produced. Method according to one of claims 2 to 8, characterized in that a DRAM memory element is produced as a structure and the transistor ( 125 ) forms a part of this DRAM memory element. Method according to one of Claims 2 to 8, characterized in that a microprocessor is produced as the structure and the transistor ( 125 ) forms part of this microprocessor. Method according to one of the preceding claims, characterized in that a gas is used as the etching gas, wherein the atoms are arranged in a linear chain structure.

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