DE102005040883B3 - Pitch periods partitioning method for e.g. semiconductor memory, involves applying complementary layer to fill free spaces, forming even surface on upper side of spacers and complementary layer, and removing spacers or complementary layer - Google Patents
Pitch periods partitioning method for e.g. semiconductor memory, involves applying complementary layer to fill free spaces, forming even surface on upper side of spacers and complementary layer, and removing spacers or complementary layer Download PDFInfo
- Publication number
- DE102005040883B3 DE102005040883B3 DE200510040883 DE102005040883A DE102005040883B3 DE 102005040883 B3 DE102005040883 B3 DE 102005040883B3 DE 200510040883 DE200510040883 DE 200510040883 DE 102005040883 A DE102005040883 A DE 102005040883A DE 102005040883 B3 DE102005040883 B3 DE 102005040883B3
- Authority
- DE
- Germany
- Prior art keywords
- layer
- spacer
- spacers
- complementary
- complementary layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
Abstract
Description
Die vorliegende Erfindung betrifft Herstellungsverfahren periodischer Strukturen oder Muster von Halbleiterbauelementen.The The present invention relates to manufacturing processes more periodically Structures or patterns of semiconductor devices.
Bestimmte Typen von Halbleiterbauelementen wie Halbleiterspeicher weisen Strukturelemente oder in Mustern strukturierte Schichten auf, die zumindest in einer Dimension periodisch sind. Wortleitungen und Bitleitungen, zum Beispiel, werden oftmals längs gerader Linien angeordnet, die parallel zueinander verlaufen. Die Breite der Linien und der Abstand zwischen benachbarten Linien sind über das Bauelement hinweg gleichbleibend. Auf diese Weise ist die Abfolge der Leitungen in einer Richtung periodisch, vorzugsweise in geringstmöglichem Abstand, was es ermöglicht, eine Speicherzellenanordnung geringster Fläche zu realisieren. Die Abmessungen der Leitungen und ihrer Zwischenräume werden in der Richtung der periodischen Abfolge fortlaufend wiederholt. Die Länge einer dieser Perioden wird Teilungsperiode oder Pitch des Musters genannt.Certain Types of semiconductor devices such as semiconductor memories have structural elements or patterned layers in patterns, at least in one dimension are periodic. Word lines and bit lines, for example often along arranged straight lines that are parallel to each other. The Width of the lines and the distance between adjacent lines are above the Constant component. This is the sequence the lines in one direction periodically, preferably in the least possible Distance, which makes it possible to realize a memory cell arrangement smallest area. The dimensions the wires and their gaps become in the direction the periodic sequence repeated continuously. The length of a These periods are called the pitch period or pitch of the pattern.
Die Größe des Pitch ist durch die Herstellungstechnologie, die zur Strukturierung des periodischen Musters angewendet wird, eingeschränkt. Einige Einschränkungen sind auf die Maskentechnik zurückzuführen, die in dem Strukturierungsprozess angewendet wird. In dem üblichen Ätzprozess unter Verwendung von Masken gibt es untere Grenzen für die erreichbaren Abmessungen. Eine weitere Miniaturisierung der Bauelemente macht es andererseits erforderlich, Herstellungsverfahren bereitzustellen, mit denen kleinere Pitches realisiert werden können. Diese Verfahren können nur angewendet werden, wenn die hergestellten Strukturen ausreichend präzise sind, um den Anforderungen an die Betriebseigenschaften des Bauelementes zu genügen.The Size of the pitch is due to the manufacturing technology used to structure the periodic pattern is applied, restricted. Some restrictions are due to the mask technique, the is used in the structuring process. In the usual etching process using masks, there are lower limits to the achievable Dimensions. Further miniaturization of the components makes On the other hand, it is necessary to provide manufacturing processes with which smaller pitches can be realized. These procedures can only be applied if the structures produced sufficient precise are to the requirements of the operating characteristics of the device to suffice.
In
der
In
der
Aufgabe der vorliegenden Erfindung ist es, ein Verfahren zur Herstellung periodischer Muster aus Halbleiterbauelementen anzugeben, das kleinere Pitches als bisher ermöglicht. Das Verfahren soll nur Standardprozessschritte der Halbleitertechnologie umfassen.task The present invention is a process for the preparation indicate periodic pattern of semiconductor devices, the smaller Pitches as previously possible. The method is only intended to standard process steps of semiconductor technology include.
Diese Aufgabe wird mit dem Verfahren mit den Merkmalen des Anspruchs 1 gelöst. Ausgestaltungen ergeben sich aus den abhängigen Ansprüchen. These The object is achieved by the method having the features of claim 1 solved. Embodiments emerge from the dependent claims.
Das Verfahren verwendet eine wiederholte Spacertechnik, um ein regelmäßiges, periodisches Muster durch kleinere und enger beabstandete Elemente zu ersetzen, die eine Unterteilung des Pitch liefern. Dieses Verfahren umfasst die Schritte der Bereitstellung eines Substrates mit einer Strukturschicht, die in getrennte streifenartige Anteile strukturiert wird, die parallel zueinander verlaufen und dieselbe laterale Abmessung und denselben Abstand zwischen ihnen besitzen; konformes Aufbringen einer ersten Spacerschicht auf die Strukturschicht; anisotropes Ätzen der ersten Spacerschicht, um erste Spacer auf den Seitenwänden der streifenförmigen Anteile zu bilden; Entfernen der Strukturschicht, wobei die ersten Spacer mit zwei Hauptseitenwänden jeweils stehen bleiben; konformes Aufbringen einer zweiten Spacerschicht; anisotropes Ätzen der zweiten Spacerschicht, um zweite Spacer auf den Hauptseitenwänden der ersten Spacer zu bilden, sodass freie Zwischenräume zwischen zueinander benachbarten zweiten Spacern bleiben; Aufbringen einer komplementären Schicht, um die freien Zwischenräume aufzufüllen; Bilden einer planaren Oberseite aus den oberen Oberflächen der ersten Spacer, der zweiten Spacer und der komplementären Schicht; und Entfernen entweder der ersten Spacer oder zweiten Spacer oder der komplementären Schicht oder der ersten und der zweiten Spacer oder der ersten Spacer und der komplementären Schicht oder der zweiten Spacer und der komplementären Schicht.The Method uses a repeated spacer technique to produce a regular, periodic pattern by replacing smaller and more closely spaced elements, the provide a subdivision of the pitch. This method includes the Steps of Providing a Substrate with a Structural Layer, which is structured into separate stripe-like portions which are parallel to each other and the same lateral dimension and the same Own distance between them; compliant application of a first Spacer layer on the structural layer; anisotropic etching of first spacer layer to first spacer on the sidewalls of the strip-shaped parts to build; Remove the structural layer, with the first spacer with two main side walls respectively stay standing; compliant application of a second spacer layer; anisotropic etching the second spacer layer to form second spacers on the main sidewalls of the first spacer, so free spaces between each other adjacent remain second spacers; Applying a complementary layer, around the free spaces fill; Forming a planar top from the upper surfaces of the first spacer, second spacer and complementary layer; and Remove either the first spacer or second spacer or the complementary Layer or the first and the second spacer or the first spacer and the complementary one Layer or the second spacer and the complementary layer.
Es folgt eine genauere Beschreibung von Beispielen des Verfahrens anhand der beigefügten Figuren.It follows a more detailed description of examples of the method the attached figures.
Die
Die
Die
Die
Die
Die
Die
Die
Die
Die
Die
Die
Die
Die
Die
Die
Die
Die
Die
Die
Die
Oberseite des Zwischenproduktes gemäß der
Die
Die
Die
Die
Die
Die
Die
Die
Die
- 11
- Substratsubstratum
- 22
- Strukturschichtstructural layer
- 33
- Hartmaskehard mask
- 44
- erste Spacerschichtfirst spacer
- 55
- erster Spacerfirst spacer
- 66
- zweite Spacerschichtsecond spacer
- 77
- zweiter Spacersecond spacer
- 88th
- komplementäre Schichtcomplementary layer
- 99
- Bauelementschichtdevice layer
- 1010
- Original-PitchOriginal pitch
Claims (6)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE200510040883 DE102005040883B3 (en) | 2005-08-29 | 2005-08-29 | Pitch periods partitioning method for e.g. semiconductor memory, involves applying complementary layer to fill free spaces, forming even surface on upper side of spacers and complementary layer, and removing spacers or complementary layer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE200510040883 DE102005040883B3 (en) | 2005-08-29 | 2005-08-29 | Pitch periods partitioning method for e.g. semiconductor memory, involves applying complementary layer to fill free spaces, forming even surface on upper side of spacers and complementary layer, and removing spacers or complementary layer |
Publications (1)
Publication Number | Publication Date |
---|---|
DE102005040883B3 true DE102005040883B3 (en) | 2007-01-04 |
Family
ID=37545307
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE200510040883 Expired - Fee Related DE102005040883B3 (en) | 2005-08-29 | 2005-08-29 | Pitch periods partitioning method for e.g. semiconductor memory, involves applying complementary layer to fill free spaces, forming even surface on upper side of spacers and complementary layer, and removing spacers or complementary layer |
Country Status (1)
Country | Link |
---|---|
DE (1) | DE102005040883B3 (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5296410A (en) * | 1992-12-16 | 1994-03-22 | Samsung Electronics Co., Ltd. | Method for separating fine patterns of a semiconductor device |
US6063688A (en) * | 1997-09-29 | 2000-05-16 | Intel Corporation | Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition |
-
2005
- 2005-08-29 DE DE200510040883 patent/DE102005040883B3/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5296410A (en) * | 1992-12-16 | 1994-03-22 | Samsung Electronics Co., Ltd. | Method for separating fine patterns of a semiconductor device |
US6063688A (en) * | 1997-09-29 | 2000-05-16 | Intel Corporation | Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE10207131B4 (en) | Process for forming a hardmask in a layer on a flat disk | |
DE102005049279B3 (en) | Semiconductor memory device and manufacturing method | |
EP0755067B1 (en) | Method of fabrication for sublithographic etching masks | |
DE19860505B4 (en) | ESD protection circuit and method for its manufacture | |
DE102008048651B4 (en) | Method of manufacturing a semiconductor device with two capacitors | |
DE102016123943A1 (en) | Semiconductor processes and devices | |
DE10327945B4 (en) | Semiconductor memory devices and methods of making the same using sidewall spacers | |
EP1497861B1 (en) | Semiconductor component having an integrated capacitance structure and method for producing the same | |
DE10245179A1 (en) | Integrated circuit comprises first lines on first plane, and second lines on second plane | |
DE102007016290A1 (en) | Method for producing semiconductor structures | |
DE102018208142A1 (en) | Multidirectional self-aligned multiple structuring | |
DE102019203596A1 (en) | Multiple structuring with mandrel cuts made using a block mask | |
DE19708031B4 (en) | Non-volatile semiconductor memory and method for its production | |
DE10228344B4 (en) | Process for the production of microstructures and arrangement of microstructures | |
DE102007007696B4 (en) | Semiconductor device and method for manufacturing a semiconductor device | |
DE102006048960B4 (en) | Method for producing insulation structures with integrated deep and shallow trenches | |
DE102007035898A1 (en) | Semiconductor component and method for its production | |
EP1540712B1 (en) | Method for production of a semiconductor structure | |
DE2743299A1 (en) | CHARGE COUPLING ARRANGEMENT | |
DE19983274B4 (en) | Method of manufacturing a non-volatile semiconductor memory device | |
DE102020115239A1 (en) | Vertical storage device | |
DE102005040883B3 (en) | Pitch periods partitioning method for e.g. semiconductor memory, involves applying complementary layer to fill free spaces, forming even surface on upper side of spacers and complementary layer, and removing spacers or complementary layer | |
DE102006043113B3 (en) | A method of processing a structure of a semiconductor device and structure in a semiconductor device | |
DE19719909A1 (en) | Dual damascene process for integrated circuits | |
DE10137575A1 (en) | Process for producing a mask and process for producing a semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8100 | Publication of the examined application without publication of unexamined application | ||
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: QIMONDA AG, 81739 MUENCHEN, DE |
|
R081 | Change of applicant/patentee |
Owner name: INFINEON TECHNOLOGIES AG, DE Free format text: FORMER OWNER: QIMONDA AG, 81739 MUENCHEN, DE Owner name: POLARIS INNOVATIONS LTD., IE Free format text: FORMER OWNER: QIMONDA AG, 81739 MUENCHEN, DE |
|
R081 | Change of applicant/patentee |
Owner name: POLARIS INNOVATIONS LTD., IE Free format text: FORMER OWNER: INFINEON TECHNOLOGIES AG, 85579 NEUBIBERG, DE |
|
R119 | Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee |