DE102008011757A1 - Method for maintaining lowest doping levels in semiconductor fabrication - Google Patents
Method for maintaining lowest doping levels in semiconductor fabrication Download PDFInfo
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- DE102008011757A1 DE102008011757A1 DE102008011757A DE102008011757A DE102008011757A1 DE 102008011757 A1 DE102008011757 A1 DE 102008011757A1 DE 102008011757 A DE102008011757 A DE 102008011757A DE 102008011757 A DE102008011757 A DE 102008011757A DE 102008011757 A1 DE102008011757 A1 DE 102008011757A1
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- oxide layer
- dopant concentration
- layer
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- nitride layer
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- 238000000034 method Methods 0.000 title claims description 23
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000002019 doping agent Substances 0.000 claims abstract description 43
- 150000004767 nitrides Chemical class 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims description 9
- 230000010354 integration Effects 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 230000035876 healing Effects 0.000 claims 1
- 238000000137 annealing Methods 0.000 abstract description 8
- 238000011109 contamination Methods 0.000 abstract description 7
- 238000000151 deposition Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 48
- 235000012431 wafers Nutrition 0.000 description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000003631 wet chemical etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
- H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier
- H01L31/105—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PIN type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Electromagnetism (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Oberseitige dotierte Bereiche einer Dotierstoffkonzentration von höchstens 1013 cm-3 werden gegen eine Kontamination mit Dotierstoff während eines Temperschrittes durch Herstellen einer Oxidschicht (7) an der Oberseite (6) und Abscheiden einer Nitridschicht (8) auf der Oxidschicht geschützt. Die Dotierstoffkonzentration kann auf diese Weise oberflächennah im Bereich von höchstens 1013 cm-3 gehalten werden.Upper side doped regions of a dopant concentration of at most 1013 cm-3 are protected against contamination with dopant during an annealing step by forming an oxide layer (7) on top (6) and depositing a nitride layer (8) on the oxide layer. The dopant concentration can be kept near the surface in the range of at most 1013 cm-3 in this way.
Description
Die vorliegende Erfindung betrifft ein Verfahren zur Aufrechterhaltung niedrigster Dotierlevel bei der Herstellung von Halbleiterbauelementen mit Bereichen niedriger Dotierstoffkonzentration, insbesondere mit einer Dotierstoffkonzentration von weniger als 1013 cm–3.The present invention relates to a method for maintaining lowest doping levels in the manufacture of semiconductor devices having low dopant concentration regions, in particular having a dopant concentration of less than 10 13 cm -3 .
Bei der Integration von Bauelementen in integrierten Schaltungen auf einem Halbleiterchip werden mitunter Bereiche von Dotierstoffkonzentrationen bis höchstens 1013 cm–3 benötigt. Üblicherweise bei der Herstellung von Halbleiterchips verwendete Wafer, zum Beispiel aus Silizium, können eine sehr hohe Grunddotierung von typisch etwa 1019 cm–3 aufweisen. Bei CMOS-Prozessen und BiCMOS-Prozessen werden dotierte Wannen beider Vorzeichen der Leitfähigkeit implantiert. Die Implantate werden bei erhöhter Temperatur in eigens dafür vorgesehenen Öfen ausgeheilt, wobei eine Diffusion des Dotierstoffes auftritt und der Dotierstoff in den Wafer eingetrieben wird. Vor diesem Verfahrensschritt wird ein vorzugsweise ebenfalls thermischer Oxidationsschritt durchgeführt, mit dem eine dünne oberflächliche Oxidschicht auf dem Halbleiterwafer hergestellt wird, die ein Ausdiffundieren des Dotierstoffes in die Gasphase und damit eine Verarmung der oberflächennahen Waferbereiche an Dotierstoff verhindern soll.When integrating components in integrated circuits on a semiconductor chip, sometimes ranges of dopant concentrations up to at most 10 13 cm -3 are required. Wafers commonly used in the manufacture of semiconductor chips, for example silicon, may have a very high fundamental doping of typically about 10 19 cm -3 . In CMOS processes and BiCMOS processes, doped wells of both signs of conductivity are implanted. The implants are annealed at elevated temperature in dedicated ovens where diffusion of the dopant occurs and the dopant is driven into the wafer. Prior to this process step, a preferably likewise thermal oxidation step is carried out, with which a thin surface oxide layer is produced on the semiconductor wafer, which is intended to prevent outdiffusion of the dopant into the gas phase and thus a depletion of the near-surface wafer regions to dopant.
Wenn die Implantate eines Wafers mit niedrig dotierten Bereichen auf diese Weise ausgeheilt werden, genügt die oberseitige Oxidschicht nicht, die Dotierstoffkonzentration in den niedrig dotierten Bereichen auf Werten unterhalb von 1013 cm–3 zu halten. Wenn der Ofen kostengünstig betrieben wird und Wafer mit niedrig dotierten Bereichen zusammen mit üblichen Wafern mit Dotierstoffkonzentrationen von typisch etwa 1015 cm–3 ausgeheilt werden, machen sich unterschiedliche Kontaminationsquellen, die nicht beseitigt werden können, negativ bemerkbar. Im Ergebnis besitzen alle Wafer an den Oberseiten nur dotierte Bereiche, in denen die Dotierstoffkonzentrationen mindestens 1015 cm–3 betragen, was nicht für alle vorgesehenen Anwendungen geeignet ist.When the implants of a wafer with low doped regions are annealed in this manner, the top oxide layer is insufficient to maintain the dopant concentration in the low doped regions at values below 10 13 cm -3 . When the furnace is operated inexpensively and wafers with low doped areas are annealed together with common wafers having dopant concentrations typically around 10 15 cm -3 , different sources of contamination that can not be eliminated are negatively impacted. As a result, all wafers on the tops have only doped areas in which the dopant concentrations are at least 10 15 cm -3 , which is not suitable for all intended applications.
Aufgabe der vorliegenden Erfindung ist es, ein Verfahren zur Aufrechterhaltung niedrigster Dotierlevel in der Halbleiterfertigung anzugeben, mit dem es möglich ist, niedrig dotierte Bereiche während eines thermischen Ausheilschrittes auf Werten der Dotierstoffkonzentration von höchstens 1013 cm–3 zu halten.The object of the present invention is to specify a method for maintaining the lowest doping levels in semiconductor production, with which it is possible to keep low-doped regions at values of the dopant concentration of at most 10 13 cm -3 during a thermal annealing step.
Diese Aufgabe wird mit dem Verfahren mit den Merkmalen des Anspruches 1 gelöst. Ausgestaltungen ergeben sich aus den abhängigen Ansprüchen.These Task is with the method with the features of the claim 1 solved. Embodiments emerge from the dependent claims.
Die Beseitigung des Kontaminationsproblems gelingt mit einer Abfolge von Verfahrensschritten, in denen zuerst auf der mit den Bereichen niedriger Dotierstoffkonzentration versehenen Oberseite des Wafers eine Oxidschicht ausgebildet wird und anschließend eine Nitridschicht auf die Oxidschicht abgeschieden wird. Danach erfolgt der Verfahrensschritt bei erhöhter Temperatur zum Eintreiben beziehungsweise Ausheilen des Dotierstoffes, während dessen die Bereiche niedriger Dotierstoffkonzentration von der Oxidschicht und der Nitridschicht geschützt bleiben. Nach dem Temperschritt können die Nitridschicht und die Oxidschicht entfernt werden.The Elimination of the contamination problem succeeds with a sequence of procedural steps in which first on the with the areas low dopant concentration provided top of the wafer an oxide layer is formed and then a nitride layer the oxide layer is deposited. Thereafter, the process step at elevated Temperature for driving or annealing the dopant, Meanwhile the regions of low dopant concentration from the oxide layer and the nitride layer protected stay. After the annealing step, the nitride layer and the oxide layer are removed.
Das geschieht zum Beispiel durch eine trocken- oder nasschemische Rückätzung.The happens, for example, by a dry or wet chemical etching back.
Es folgt eine genauere Beschreibung von Beispielen des Verfahrens anhand der beigefügten Figuren.It follows a more detailed description of examples of the method the attached figures.
Die
Die
Die
Die
An
der Oberseite
In
dem dargestellten Beispiel ist das Substrat
Die
Die
Es
wurde nachgewiesen, dass mit der Doppelschicht bestehend aus einer
ganzflächigen
Oxidschicht und einer darauf aufgebrachten wesentlich dickeren ganzflächigen Nitridschicht
eine wirkungsvolle Abschirmung der niedrig dotierten Bereiche an der
Oberseite des Wafers oder in der niedrig dotierten Epitaxieschicht
gegen Kontaminationen erzielt werden kann. Mit Verwendung nur einer
Oxidschicht oder nur einer Nitridschicht kann diese Wirkung nicht in
dem erwünschten
Umfang erreicht werden. Die Verwendung beider Schichten ermöglicht es
jedoch, die Dotierstoffkonzentration in Oberflächenbereichen des Wafers oder
in der Epitaxieschicht auf Werten von weniger als 1013 cm–3 zu
halten. Das gilt auch dann, wenn als Substrat
Die
in den Figuren dargestellten dotierten Wannen
Das
beschriebene Verfahren ermöglicht
es, Halbleiterwafer mit Bereichen unterschiedlicher Dotierstoffkonzentrationen
an der Oberseite derart zu schützen,
dass für
besondere Anwendungen, zum Beispiel zur Integration von PIN-Fotodioden, niedrigst
dotierte Bereiche an der Oberseite des Substrates erhalten bleiben.
Die Dotierstoffkonzentration kann dadurch in einem ursprünglich entsprechend niedrig
dotierten Bereich einer Epitaxieschicht insbesondere auf Werten
unterhalb 1013 cm–3 gehalten werden.
Wenn entweder die Oxidschicht
- 11
- Substratsubstratum
- 22
- Epitaxieschichtepitaxial layer
- 33
- n-Wannen-well
- 44
- p-Wannep-well
- 55
- OxidverkapselungOxidverkapselung
- 66
- Oberseitetop
- 77
- Oxidschichtoxide
- 88th
- Nitridschichtnitride
Claims (9)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102008011757.9A DE102008011757B4 (en) | 2008-02-28 | 2008-02-28 | Method for maintaining lowest doping levels in semiconductor fabrication |
PCT/EP2009/050950 WO2009106400A1 (en) | 2008-02-28 | 2009-01-28 | Method for maintaining lowest doping levels in semicondcutor production |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102008011757.9A DE102008011757B4 (en) | 2008-02-28 | 2008-02-28 | Method for maintaining lowest doping levels in semiconductor fabrication |
Publications (2)
Publication Number | Publication Date |
---|---|
DE102008011757A1 true DE102008011757A1 (en) | 2009-09-10 |
DE102008011757B4 DE102008011757B4 (en) | 2014-11-20 |
Family
ID=40474811
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE102008011757.9A Expired - Fee Related DE102008011757B4 (en) | 2008-02-28 | 2008-02-28 | Method for maintaining lowest doping levels in semiconductor fabrication |
Country Status (2)
Country | Link |
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DE (1) | DE102008011757B4 (en) |
WO (1) | WO2009106400A1 (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5279976A (en) * | 1991-05-03 | 1994-01-18 | Motorola, Inc. | Method for fabricating a semiconductor device having a shallow doped region |
US6048769A (en) * | 1997-02-28 | 2000-04-11 | Intel Corporation | CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers |
US20030008524A1 (en) * | 2001-07-04 | 2003-01-09 | Karsten Wieczorek | Method of forming a thin oxide layer having improved reliability on a semiconductor surface |
US20030059985A1 (en) * | 2001-09-27 | 2003-03-27 | Adkisson James W. | Method of fabricating lateral diodes and bipolar transistors |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4662956A (en) * | 1985-04-01 | 1987-05-05 | Motorola, Inc. | Method for prevention of autodoping of epitaxial layers |
KR100577607B1 (en) * | 2004-07-27 | 2006-05-10 | 삼성전자주식회사 | Method of forming well for using semiconductor device and method of manufacturing of semiconductor device having the same |
-
2008
- 2008-02-28 DE DE102008011757.9A patent/DE102008011757B4/en not_active Expired - Fee Related
-
2009
- 2009-01-28 WO PCT/EP2009/050950 patent/WO2009106400A1/en active Application Filing
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5279976A (en) * | 1991-05-03 | 1994-01-18 | Motorola, Inc. | Method for fabricating a semiconductor device having a shallow doped region |
US6048769A (en) * | 1997-02-28 | 2000-04-11 | Intel Corporation | CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers |
US20030008524A1 (en) * | 2001-07-04 | 2003-01-09 | Karsten Wieczorek | Method of forming a thin oxide layer having improved reliability on a semiconductor surface |
US20030059985A1 (en) * | 2001-09-27 | 2003-03-27 | Adkisson James W. | Method of fabricating lateral diodes and bipolar transistors |
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DE102008011757B4 (en) | 2014-11-20 |
WO2009106400A1 (en) | 2009-09-03 |
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