DE102008045813A1 - Logic circuit for calculating CRC test values - Google Patents

Abstract

A logic circuit is proposed for calculating a CRC check value of a message, wherein the CRC check value has a predefinable length. The logic circuit comprises an input (402) for receiving the message, an input (401) for receiving a freely definable CRC polynomial, calculation means (421-426, "&", "= 1") for calculating a CRC check value of the message based on the CRC polynomial and switching means (430), which connect the calculation means (421-426, "&", "= 1") to a length of the CRC polynomial such that the length of the CRC check value is equal to the length of the CRC polynomial Corresponds to CRC polynomial. This can be used to provide a hardware circuit that allows the calculation of different length test values using arbitrary genrator polynomials.

Description

The The present invention relates to a logic circuit for calculation of CRC test values and a use of such Circuit during a data transmission.

State of the art

at the cyclic redundancy check (cyclic redundancy check, CRC) is an information technology process for determining a test value for data (eg Network traffic or a file) to errors in the transfer or Recognize duplication of data.

CRC check values are often referred to as CRC checksums, although in the true sense it is a test division remainder and not buzz. At the CRC, a block of data is passed through divides a CRC polynomial modulo. The remainder of the division represents the CRC check value represents.

CRC types are distinguished by the CRC polynomial used (generator polynomial). The length of the testable data block depends on the bit length of the polynomials. There are known standard polynomials, such. B .:
CRC-CCITT (CRC-16): 0x11021
IBM CRC-16: 0x18005
IEEE-802 CRC (CRC-32): 0x104C11DB7
CRC32 / 4: 11EDC6F41
CAN-CRC: 0xC599
Bluetooth: 0x35

It is known to implement CRC logic circuits using a shift register - usually a linear feedback shift register LFSR - with XOR gates provided between the individual bits of the register. The placement of the XOR gates depends on the coefficients of the corresponding terms in the polynomial, which are 1. In the US 4,723,243 as well as the US 6,253,346 B1 Dedicated circuits are disclosed for calculating a CRC-32 checksum. However, these circuits are inflexible because they can only use a given generator polynomial, CRC-32 in the example given.

Especially in certain areas of data transmission it is necessary to be able to use different generator polynomials. These must be done either by implementing multiple hardware circuits or software calculated. Both possibilities are expensive. Furthermore, in situations in which the necessary CRC polynomials are not yet known, no (fast) Hardware circuits are used. Instead, you have to slow software solutions are used.

outgoing from this prior art is a logic circuit for calculation a CRC check value of a message with the characteristics of Patent claim 1 proposed. Advantageous embodiments are Subject matter of the dependent claims and the description below.

Advantages of the invention

By the logic circuit according to the invention can be a Substantial acceleration of the calculation process at large Flexibility can be achieved. The logic circuit is in able to use any CRC polynomials, the maximum number of bits of the polynomial limited only by the design of the circuit becomes. In practice, however, it will offer a maximum Bit number of 32 or 64 to set.

It is advantageous if the logic circuit has an interface functionality, for example, an API. This procedure allows the fast calculation of CRC test values in particular of data blocks in a data telegram at variable positions. The logic circuit can be an integrated circuit or part of a be formed integrated circuit. It can also be called ASIC or FPGA, etc. may be formed. In the prior art there are logic circuits in most cases not anymore like before hard-wired logic, but from flexibly programmable components (FPGAs, EPLDs, ASICs, Gate Arrays, etc.). These blocks include Depending on the type, no predetermined logic functionalities, but provide a kind of "logic kit" ready. By programming these blocks, a desired Functionality can be specified.

conventional Logic modules have a predetermined, manufacturing or type-related Capacity up. In many cases, existing circuits are Logic modules already exist whose capacity is still not fully occupied. In this case, the inventive Logic circuit can be implemented particularly advantageous because only small or no circuit changes necessary are. Thus, a cost saving can be achieved. In the Data transfer to the data blocks to the Logic circuit passed, which then independently calculated the corresponding CRC test values. The handover can for example be serial or parallel, via registers etc. take place.

The checksum of a data stream can be calculated in bits or bytes, etc., and attached to the data by the sender. The calculation of the checksum per se is preferably done over be knew methods, in particular use of shift registers for processing a bit data stream, as described, for example, in the cited prior art. Conveniently, the most significant bit of the shift register is defined by the switching means. Advantageously, the switching means for this purpose at least one multiplexer, are passed to the at least two bits of the shift register. Furthermore, the calculating means expediently comprise at least one XOR gate. By means of XOR gates, a polynomial division can be implemented particularly easily in hardware. The length dependence can then be achieved, for example, by selecting one of the bits of the shift register via the multiplexer and feeding it as feedback into the XOR block. For example, with a 32-bit checksum, the multiplexer requires five control inputs that select one of 2 ^ 5 (= 32) inputs as the CRC register bit to feed back. Alternatively, a chain of 31 AND gates could be used, with each AND gate having two inputs, each with a CRC register bit and a configurable bit. In this case one needs, for example, 31 control bits (instead of 5 control bits in comparison with a MUX), of which only exactly one AND gate is provided with a "1", all others have the value "0".

Preferably the logic circuit has an input for receiving an initialization value or start value for the shift register. Dependent on The used CRC polynomial has different initialization values proved to be advantageous, the advantageous of the logic circuit also be fed from the outside. For example for CRC-16 according to CCITT with the polynomial x ^ 16 + x ^ 12 + x ^ 5 + 1 as Start value "1" used in each register bit. The starting value can also be any value, in particular also accept "0".

advantageously, At least one predetermined CRC polynomial is integrated. It lends itself to the intended use needed and / or the known, in the description of the Prior art polynomials already firmly in the circuit to integrate, which in particular the external circuitry can be reduced. In particular, a choice may be made be provided to use one of the predetermined CRC polynomials for use select. It is also possible, only a predetermined one Integrate CRC polynomial, which, for example, then used automatically if no freely specifiable CRC polynomial is present at the input. It makes sense, for each predetermined CRC polynomial also one to predetermine initialization value.

It is useful if a length of the CRC polynomial can be specified externally. It is also possible to change the length of the externally given CRC polynomial within the circuit determine, but by the external specification of the length the complexity of the circuit can be reduced. By the determination of the length within the circuit is it possible to reduce the external circuit complexity.

It is particularly useful when the inventive Logic circuit is integrated in a communication controller. Communication controllers are used for data transmission used and set different functionalities for the data transfer ready. By the additional Integration of the logic circuit can be a beneficial space saver be achieved. It is understood that the inventive Logic circuit can also be integrated into other logic devices.

As well It is advantageous if the inventive Logic circuit is designed as an integrated circuit module. This allows it in addition to existing building blocks or Controllers are used and used in existing systems become.

It is useful if the inventive Logic circuit for Ethernet-based data transmission is used. Ethernet-based data transmission is now widely used and forms a standard embodiment the data transmission. The inventive Logic circuitry can be advantageously integrated into existing systems become.

In In a particularly preferred embodiment, the inventive Logic circuit in a fieldbus network, in particular in one Network used according to a SERCOS standard. For example, can a network to be used according to the SERCOS III standard, the the use of Ethernet components in a SERCOS connection allowed.

Conveniently, the logic circuit according to the invention for Real-time data transmission or real-time communication used. Especially with real-time communication, the accelerated effect CRC check value calculation advantageous.

Further Advantages and embodiments of the invention will become apparent from the Description and attached drawing.

It is understood that the features mentioned above and those yet to be explained not only in the combination specified, but also in other combinations or alone, without the To leave the scope of the present invention.

figure description

in the The following is intended to illustrate the invention and in particular its advantages an embodiment shown in the figures be explained in more detail.

It shows

1a a flowchart of a data transmission in which data fields are provided with CRC check values, in the prior art;

1b a flowchart corresponding 1a wherein an embodiment of a logic circuit according to the invention is used;

2 a schematic representation of an embodiment of a logic circuit according to the invention;

3 the construction of a master data telegram according to the SERCOS III standard, which is generated using an embodiment of the logic circuit according to the invention; and

4 a schematic representation of the switching elements of an embodiment of a logic circuit according to the invention.

In 1a A flow chart of data transmission in the prior art is shown wherein selected data fields are provided with CRC check values.

In the process step 100 the actions to be transferred are prepared. Among other things, this includes the division of the data into data blocks, whereby individual data blocks are transmitted in data telegrams.

In step 101 For each data block, the corresponding CRC check value is calculated. This is done in the prior art by software routines that take a relatively long period of time due to the described requirements.

In the process step 102 then the data blocks are combined with the calculated CRC check values. The summarized data is finally in the process step 103 passed to the communication controller. The communication controller performs the subsequent data transfer largely independently.

In 1b is a the in 1a shown flowchart corresponding flow chart, wherein a preferred embodiment of a logic circuit according to the invention is used.

In step 110 In turn, the data to be transmitted is divided into individual data blocks. In the process step 111 the logic circuit dedicated to calculating CRC check values is initialized and configured. Among other things, the logic circuit is informed of the CRC polynomial to be used, the length of the CRC polynomial to be used and the position of the data blocks for which CRC test values are to be calculated.

In the process step 112 are only the data blocks of the logic circuit or a communication controller having an integrated logic circuit to pass. Before the subsequent data transmission, the logic circuit or the logic circuit integrated into the communication controller independently carries out the CRC test value calculation. In this way, the process can be accelerated.

By the use of a logic circuit according to the invention In particular, communication controllers can be provided be used for different transmission protocols, especially different fieldbus systems are suitable. For example becomes a 16bit checksum on a SERCOS I / II or CAN bus whereas in a SERCOS III, safety SERCOS or EtherCAT bus a 32bit checksum is used.

In 2 an embodiment of a logic circuit according to the invention is shown roughly schematically and overall with 200 designated. The logic circuit 200 has an entrance 201 and an exit 202 on. The entrance 201 and the exit 202 can be designed for serial or parallel data transmission, as is well known in the art. It is understood that it is at the entrance 201 and the exit 202 not physically designed in this form components such. B. plug, etc. must act, but that also inputs and outputs of a logical interface description are included in this description.

At the entrance 201 become input data 203 provided. The input data 203 contain different data areas or data blocks 203a to 203e , In this schematic representation, the subdivision corresponds to the input data 203 in individual blocks not necessarily a temporal, spatial or other subdivisions, but above all represents a schematic subdivision.

The input data blocks 203a to 203e contain on the one hand the configuration data required for initialization and configuration of the logic circuit 200 and on the other hand the data for which a CRC check value calculation is to take place. For example, the input data block contains 203a the CRC polynomial to use, the input data block 203b the length of the CRC polynomial to use, the input data block 203c the amount or number of data for which the CRC check value calculation is to take place and the input data blocks 203d and 203e the data for which the CRC check value calculation is to take place.

A start value for a shift register within the logic circuit may also be preferred 200 over the entrance 201 be predeterminable. Usually, different start values, for example, "111111 .... 1"("1" in each register bit) or "0"("0" in each register bit) depending on the selected CRC polynomial have proven to be advantageous. The starting value can be within the input data 203 be specified as a further data area or data block (not shown).

The input data blocks 203a to 203e be as input data 203 to the entrance 201 to hand over. The logic circuit 200 then calculates the associated CRC check values according to their configuration for the transferred data.

The logic circuit 200 finally stops at its exit 202 the output data 204 ready. In this embodiment, the output data includes 204 Output data blocks 204a to 204d , The number of output data blocks is preferably determined by the number of input data blocks. In this example, for the two input data blocks 203d and 203e each calculated a CRC test value. The input data blocks 203d and 203e are called output data blocks 204a respectively. 204c output, with the associated CRC check values 204b respectively. 204d each inserted as additional output data blocks.

In this way, a fast CRC check value calculation for variable data blocks can be achieved, as they occur in particular in the case of data transmission according to the SERCOS III standard, as described in more detail 3 is explained.

In 3 the construction of an exemplary Master Data Telegram (MDT) according to the SERCOS III standard is shown schematically.

at SERCOS is a standardized servo drive interface with fieldbus couplers. The range of applications includes machining Machining technologies also other automation solutions z. As in the field of assembly robots, as well as printing and packaging machines.

Of the Access to the transmission medium is by a time slot method realized. Each participant is assigned a time, on which he exclusively the right of access to the transmission medium has.

Of the Communication cycle is through the master synchronization telegram (MST) of the master, z. As a control system started. The slaves, z. For example, drive systems or I / O stations send one at a time a drive telegram (AT) with its current actual values. Subsequent sends the master sends the master data telegram (MDT) with the setpoints. This Sequence repeats itself in every communication cycle. All data telegrams are received by all slaves. An MDT therefore contains Data for all the slaves to be controlled.

An MDT field (MDT data field) 300 has three areas 301 . 302 . 303 on, the area being 301 as "MDT hotplug field", the area 302 as "MDT service channel field" and the area 303 is called "MDT realtime data field". The area 303 (MDT realtime data field) contains the real-time data, which is transmitted to all the slaves to be controlled.

In the example shown, the. Area 303 three inner areas 304 . 305 and 306 which each contain real-time data for different connected slaves. This example contains data for three connected slaves, which is why the ranges 304 . 305 and 306 be referred to as "realtime data 1", "realtime data 2" and "realtime data 3". The number of slaves for which data is transferred may change each transmission cycle.

Depending on the intended use of the addressed slaves, the areas indicate 304 . 305 . 306 again a different internal structure.

In the example shown, the area points 304 (realtime data 1) two areas 304a and 304b referred to as "standard realtime data 1" (SRD 1) and "safe data container 1" (SDC 1).

The area 305 (realtime data 1) has an area 305a (SRD 1) on, the area 306 (realtime data 3) indicates an area 306a (SRD 3) and an area 306b (SDC 3).

In the fields of 304a (SRD 1), 305a (SRD 2) and 306a (SRD 3) contain the data for the respective slaves, which do not have to have increased error safety. In the fields of 304b (SDC 1) and 306b (SDC 3), on the other hand, contains the data that has increased error safety. to To provide increased error security, CRC check values are added.

In the prior art, the CRC test values for the ranges 304b and 306b calculated via software routines. The content of the areas 304a . 305a . 306a and the areas 304b and 306b usually varies with each transmission cycle. Also, the subdivisions of the area 303 (MDT realtime data field) into the areas 304 (real-time data 1), 305 (realtime data 2) and 306 (realtime data 3) only by way of example and also vary from application to application. Also, the number of subdivisions mentioned is not constant.

Out For these reasons, the CRC test values be recalculated in each transmission cycle. This takes a long time in every transmission cycle to complete.

By Use of a preferred embodiment of the invention Method for calculating the CRC test values included in the varying areas "SDC" added can be achieved, a significant time savings.

In 4 a preferred embodiment of a logic circuit according to the invention is shown schematically and in total with 400 designated. The logic circuit 400 has a first entrance 401 for receiving a generator polynomial. Furthermore, the logic circuit 400 a second entrance 402 to record a message. Furthermore, the logic circuit 400 a third entrance 403 to record the length of the CRC polynomial to be used. Finally, the logic circuit points 400 an exit 404 to output the calculated CRC check value.

The message becomes a shift register within the logic circuit 400 fed, which has a freely selectable in configuration of the logic circuit number of bits. In the illustrated embodiment, the shift register has six bits 421 to 426 , The arbitrary number of bits of the shift register determines the maximum size of the CRC polynomial usable with the logic circuit.

The logic circuit 400 also has storage means for receiving the CRC polynomial. The storage means store the individual bits 411 to 416 the generator polynomial and may be formed for example as flip-flops. The number of storage means preferably corresponds to the number of shift register locations. For example, it is advisable to provide a number of 32 or 64 bits, in which case CRC checksums with a maximum of 32 or 64 bits can be calculated.

optional the logic circuit also has an input (not shown) Recording a preset or initialization value for the shift register. Depending on the used CRC polynomial have become different initialization values proved to be advantageous, the advantageous of the logic circuit also be fed from the outside.

To determine the CRC check value, each of the polynomials is 411 to 416 connected via an AND gate "&" to an XOR gate ("= 1"). The individual XOR gates "= 1" are arranged between the bits of the shift register. The basic mode of operation of such a circuit is known to the person skilled in the art and will therefore not be explained further here. For example, an inversion may occur, etc.

According to the invention, in the logic circuit 400 CRC polynomials of variable length can be used. For this purpose, in each case one input of the AND gate "&" with a multiplexer circuit 430 connected by means of the entrance 403 length of the CRC polynomial selects one bit of the shift register and defines it as the most significant bit.

At the end of the calculation of the CRC check value, this is in the bits 421 . 422 , ... including the selected most significant bit. The test value can there, for example, also in series via the multiplexer circuit 430 or otherwise (for example, in parallel), including the output 404 is provided.

Although in the illustrated embodiment, the length of the CRC polynomial is across the input 403 This input can also be internally connected to a calculation circuit which determines the length of the polynomial based on the bits 411 to 416 certainly.

It is understood that in the illustrated figures, only exemplary embodiments of the invention is shown. In addition, any other embodiment is conceivable without departing from the scope of this invention. For example, the functionality of the AND gate in 4 also be realized by multiplexer. Conversely, the functionality of the multiplexer 430 also be reached by AND gates.

101-103

step

110-112

step

200

logic circuit

201

entrance

202

output

203

input data

203a-203e

Input data block

204

output data

204a-204d

Output data block

300

MDT field

301

MDT hotplug field

302

MDT service channel field

303

MDT real-time data field

304

realtime data 1

304a

default realtime data 1

304b

safe data container 1

305

realtime data 2

305a

default realtime data 2

306

realtime data 3

306a

default realtime data 3

306b

safe data container 3

400

logic circuit

401 402, 403

entrance

404

output

411-416

Generatorpolynombits

421-426

Shift register

430

multiplexer

&

AND gate

= 1

XOR gate

QUOTES INCLUDE IN THE DESCRIPTION

This list The documents listed by the applicant have been automated generated and is solely for better information recorded by the reader. The list is not part of the German Patent or utility model application. The DPMA takes over no liability for any errors or omissions.

Cited patent literature

• US 4723243 [0005]
• - US 6253346 B1 [0005]

Claims (13)

Logic circuit for calculating a CRC check value of a message, the CRC check value having a predeterminable length, comprising an input ( 201 ; 402 ) to receive the message ( 203d . 203e ), an entrance ( 201 ; 401 ) for receiving a freely definable CRC polynomial ( 203a ), Calculation means ( 421 - 426 , "&", "= 1") to calculate a CRC check value ( 204b . 204d ) of the message ( 203d . 203e ) based on the CRC polynomial ( 203a ), and switching means ( 430 ), which the calculation means ( 421 - 426 , "&", "= 1") depending on a length ( 203b ) of the CRC polynomial ( 203a ) such that the length of the CRC check value is equal to the length ( 203b ) of the CRC polynomial ( 203a ) corresponds. Logic circuit according to claim 1, wherein the calculating means ( 421 - 426 , "&", "= 1") at least one shift register ( 421 - 426 ) whose most significant bit ( 422 - 426 ) by the switching means ( 430 ) is defined. Logic circuit according to claim 2, comprising an input ( 201 ) for receiving an initialization value for the shift register ( 421 - 426 ). Logic circuit according to claim 2 or 3, wherein the switching means comprise at least one multiplexer ( 430 ), to the at least two bits of the at least one shift register ( 421 - 426 ). Logic circuit according to one of the preceding claims, wherein the calculation means ( 421 - 426 , "&", "= 1") have at least one XOR gate ("= 1"). Logic circuit according to one of the preceding claims, wherein an input ( 201 ; 403 ) for receiving the length ( 203b ) of the CRC polynomial ( 203a ) is provided. Logic circuit according to one of the preceding claims, wherein at least one predetermined CRC polynomial is integrated. Logic circuit according to one of the preceding claims, which is integrated in a communication controller. Logic circuit according to one of the preceding claims, which is designed as an integrated circuit module. Apparatus for calculating CRC test values, the at least two logic circuits according to one of the preceding Claims. Use of a logic circuit according to one of the claims 1 to 9 or a device according to claim 10 in a fieldbus communication system. Use of a logic circuit according to one of the claims 1 to 9 or a device according to claim 10 in a network according to a SERCOS standard. Use of a logic circuit according to one of the claims 1 to 9 or a device according to claim 10 for real-time data transmission.