DE102014111305A8 - A processor model that uses a single large linear register, FIFO-based I / O ports supporting new interface signals, and interrupt bus transfers that eliminate DMA, bridges, and an external I / O bus - Google Patents

A processor model that uses a single large linear register, FIFO-based I / O ports supporting new interface signals, and interrupt bus transfers that eliminate DMA, bridges, and an external I / O bus Download PDF

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Publication number
DE102014111305A8
DE102014111305A8 DE102014111305.5A DE102014111305A DE102014111305A8 DE 102014111305 A8 DE102014111305 A8 DE 102014111305A8 DE 102014111305 A DE102014111305 A DE 102014111305A DE 102014111305 A8 DE102014111305 A8 DE 102014111305A8
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DE
Germany
Prior art keywords
bus
fifo
dma
bridges
eliminate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE102014111305.5A
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German (de)
Other versions
DE102014111305A1 (en
Inventor
Muhammad Nasir Bin Ibrahim
Namazi Bin Azhari
Adam Bin Baharum
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Universiti Teknologi Malaysia (UTM)
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Universiti Teknologi Malaysia (UTM)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by Universiti Teknologi Malaysia (UTM) filed Critical Universiti Teknologi Malaysia (UTM)
Priority to DE102014111305.5A priority Critical patent/DE102014111305A1/en
Publication of DE102014111305A1 publication Critical patent/DE102014111305A1/en
Publication of DE102014111305A8 publication Critical patent/DE102014111305A8/en
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30123—Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
DE102014111305.5A 2014-08-07 2014-08-07 A processor model that uses a single large linear register, FIFO-based I / O ports supporting new interface signals, and interrupt bus transfers that eliminate DMA, bridges, and an external I / O bus Pending DE102014111305A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE102014111305.5A DE102014111305A1 (en) 2014-08-07 2014-08-07 A processor model that uses a single large linear register, FIFO-based I / O ports supporting new interface signals, and interrupt bus transfers that eliminate DMA, bridges, and an external I / O bus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE102014111305.5A DE102014111305A1 (en) 2014-08-07 2014-08-07 A processor model that uses a single large linear register, FIFO-based I / O ports supporting new interface signals, and interrupt bus transfers that eliminate DMA, bridges, and an external I / O bus

Publications (2)

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DE102014111305A1 DE102014111305A1 (en) 2016-02-11
DE102014111305A8 true DE102014111305A8 (en) 2016-04-07

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DE102014111305.5A Pending DE102014111305A1 (en) 2014-08-07 2014-08-07 A processor model that uses a single large linear register, FIFO-based I / O ports supporting new interface signals, and interrupt bus transfers that eliminate DMA, bridges, and an external I / O bus

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Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108810087B (en) * 2018-04-28 2020-06-26 北京青云科技股份有限公司 Connection method, system and equipment of storage server

Citations (3)

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Publication number Priority date Publication date Assignee Title
US4217638A (en) * 1977-05-19 1980-08-12 Tokyo Shibaura Electric Co., Ltd. Data-processing apparatus and method
US4459657A (en) * 1980-09-24 1984-07-10 Tokyo Shibaura Denki Kabushiki Kaisha Data processing system having re-entrant function for subroutines
US6029242A (en) * 1995-08-16 2000-02-22 Sharp Electronics Corporation Data processing system using a shared register bank and a plurality of processors

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US3401376A (en) 1965-11-26 1968-09-10 Burroughs Corp Central processor
GB1192371A (en) 1966-06-02 1970-05-20 Automatic Telephone & Elect Improvements in or relating to Data Processing Devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4217638A (en) * 1977-05-19 1980-08-12 Tokyo Shibaura Electric Co., Ltd. Data-processing apparatus and method
US4459657A (en) * 1980-09-24 1984-07-10 Tokyo Shibaura Denki Kabushiki Kaisha Data processing system having re-entrant function for subroutines
US6029242A (en) * 1995-08-16 2000-02-22 Sharp Electronics Corporation Data processing system using a shared register bank and a plurality of processors

Non-Patent Citations (8)

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Title
Call stack. In: Wikipedia, the free encyclopedia. Bearbeitungsstand: 21.05.2014. URL: http://en.wikipedia.org/w/index.php?title=Call_stack&oldid=609506158 [abgerufen am 16.10.2014] *
CS322 - Operating Systems and Computer Architecture; Lecture: Hardware Requirements for Modern Operating Systems; 2000, S. 1 – 3. URL: http://www.math-cs.gordon.edu/courses/cs322/lectures/hardware.html, Archiviert in http://www.archive.org am 10.01.2008 [abgerufen am 15.10.2024]
CS322 - Operating Systems and Computer Architecture; Lecture: Hardware Requirements for Modern Operating Systems; 2000, S. 1 - 3. URL: http://www.math-cs.gordon.edu/courses/cs322/lectures/hardware.html, Archiviert in http://www.archive.org am 10.01.2008 [abgerufen am 15.10.2024] *
Intel: Intel Architecture Software Developer's Manual - Volume 2 - Instruction Set Reference, 1999. S. i,ii,vi,2-1,3-367 - 3-368. URL: https://www.cs.cmu.edu/~410/doc/intel-isr.pdf [abgerufen am 16.10.2014] *
Proenca, AJ: Zusammenfassung für Vorlesung "Computer Architecture" zu Buch "Computer Organization and Architecture - Designing for Performance", 2006. URL Vorlesung: http://gec.di.uminho.pt/Discip/Mcc/ac0405/apoio.html [abgerufen am 13.10.2014], URL Zusammenfasung: http://brahms.di.uminho.pt/discip/MaisAC/COA5e_Stallings/ResumoCOA5e_Stallings.pdf [abgerufen am 13.10.2014] *
Register window. In: Wikipedia, the free encyclopedia. Bearbeitungsstand: 24.07.2014. URL: http://en.wikipedia.org/w/index.php?title=Register_window&oldid=618326898 [abgerufen am 13.10.2014] *
Vectored Interrupt. In: Wikipedia, the free encyclopedia. Bearbeitungsstand: 16.07.2014. URL: http://en.wikipedia.org/w/index.php?title=Vectored_Interrupt&oldid=617130557 [abgerufen am 13.10.2014] *
Williams, J. and Bergmann, N.: Programmable parallel coprocessor architectures for reconfigurable system-on-chip. IEEE International Conference on Field-Programmable Technology, 2004 (Proceedings). USA : IEEE, 2004. S. 193-200. - ISBN 0-7803-8651-5. http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=139326 [abgerufen am 13.10.2014] *

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Representative=s name: KUHNEN & WACKER PATENT- UND RECHTSANWALTSBUERO, DE