DE10233663A1 - Production of a SOI substrate comprises preparing a SOI substrate by embedding a trenched oxide layer between a crystalline silicon layer and a silicon substrate - Google Patents

Abstract

Production of a SOI substrate comprises preparing a SOI substrate by: (a) embedding a trenched oxide layer (BOX) between a crystalline silicon layer and a silicon substrate (Si); (b) applying a hard mask layer on at least one region of the silicon layer; (c) forming a window in the hard mask layer to expose the silicon layer in the window region; (d) removing the silicon layer in the window region by dry etching from a first silicon layer thickness to a second silicon layer thickness; and (e) removing the silicon layer in the window region by local oxidation of the silicon and wet chemical etching of the silicon oxide formed to a third silicon layer thickness.

Description

The invention relates to a method for the production of a SOI substrate (Silicon-On-Insulator) for one SOI field effect transistor according to claim 1.

So-called fully depleted silicon-on-insulator (FD-SOI) devices with ultra-thin Channel areas are seen as a promising alternative to conventional bulk-substrate transistors in future CMOS generations considered. Such SOI MOSFETs are field effect transistors, which on a SOI substrate with a thin, single-crystalline silicon layer (TOP-silicon layer), which is arranged on an oxide layer buried underneath, be processed. Have been particularly interesting for future generations of CMOS SOI MOSFETs proven in which the layer thickness of the silicon film is smaller than the depth of the depletion zone, which extends from the silicon-silicon dioxide interface into the Silicon layer extends into it. So at Threshhold voltage is the silicon layer completely impoverished, so that SOI MOSFETs are referred to as fully depleted (FD).

By scaling down the layer thickness of the monocrystalline silicon layer of the SOI substrate, which in known SOI MOSFETs of the Body or channel thickness of the transistor corresponds to short-channel effects effectively suppressed become. However, ultra-thin channel thicknesses of 5 to 10 are required nm necessary. The data from S. Takagi et al. in IEDM Tech. Dic. (1997) Page 219 published Simulations show that this also for undoped Channel areas apply. The simulations also show that the channel area has a layer thickness of less than 10 nm should meet the requirements of the ITRS road map, especially to meet the off-current of the transistor.

The SOI substrates required for processing such SOI MOSFETs can be produced using different methods. For example, laser and zone melt recrystallization processes, so-called epitaxial lateral overgrowth processes and SIMOX processes, were initially used. Recently, wafer bonding methods (for example ELTRAN or UNIBOND) have mostly been used, with which a low-defect, thin, single-crystal silicon layer can be arranged on a buried SiO ₂ layer (buried oxide; BOX).

The above manufacturing processes ultrathin Generate SOI substrates all one thin top silicon layer with homogeneous thickness over the entire wafer. Although the layer thickness of the top silicon layer down to the thickness ranges required for new FD-SOI-MOSFETs are interesting, but has the low-impedance source or drain contact such SOI MOSFETs proved problematic. Become such in the manufacturing process SOI-MOSFETs lithography and etching processes for opening of source or drain windows used with which to create the top silicon layer of the SOI substrate from source or drain contacts The extremely thin top silicon layer is often to be exposed destroyed. So stops at silicon layer thicknesses that are below 30 nm, the etching step to open the window due to insufficient etch selectivity on the top silicon layer, but often ends up in the silicon substrate below.

Try in the source and drain areas such SOI MOSFETs the layer thickness of the top silicon layer using local selective Locally increase epitaxy also fail due to the insufficient initial layer thickness of the single-crystalline ones Silicon layer. Would be the self-aligned growth of silicon at appropriate points using local epitaxy is a suitable way of reducing the connection resistance, however, are ultra thin Top silicon layers with thicknesses of less than 20 nm compared to necessary Preparation steps for a local epitaxy of silicon is not resistant. So must before a local epitaxy of silicon, a preheating (so-called pre-bake) carried out to be on the top silicon layer remove existing oxide residues before epitaxy. With this necessary temperatures tear Top silicon layers with layer thicknesses of less than about 20 nm, however, regularly.

By Uchida et al. was therefore in IEDM Techn. Dig. 2001 ("Experimental Evidences of Quantum-Mechanical Effects on low-field mobility, gate-channel capacity, and threshold Voltage of Utrathin Body SOI MOSFETs) SOI MOSFETs proposed which are comparatively thick top silicon layers on SOI substrates be processed. The top silicon layer however, during the MOSFET processing locally "thinned" in the channel areas. outgoing of SOI substrates SOI MOSFETs were manufactured with 200 nm thick silicon layers, in which the Body or channel thickness was reduced to 7 nm. The layer thickness the top silicon layer in the source and drain areas of the SOI MOSFETs there was an area which is a local epitaxy to reduce contact resistance would enable.

However, in the above-mentioned Uchida et al. Proposed manufacturing processes for ultra-thin SOI-MOSFETs have serious disadvantages, especially in the manufacture of short-channel MOSFETs. The source-drain resistance of an SOI-MOSFET manufactured in this way is too high, in particular in the case of a short-channel geometry, which leads to unsatisfactory transis gate properties leads.

Given the above disadvantages it is an object of the invention to provide a method for producing a SOI substrate for specify an SOI field effect transistor, which is the processing of an ultra thin SOI MOSFETs with reduced source-drain resistance allowed.

This task is accomplished through a process according to claim 1 solved. Preferred embodiments are subject to the dependent Expectations.

• (a) Bereitstellen eines SOI-Substrats, bei welchem eine vergrabene Oxidschicht zwischen einer kristallinen Siliziumschicht und einem Substrat eingebettet ist;
• (b) Aufbringen einer Hartmaskenschicht auf zumindest einem Bereich der Siliziumschicht;
• (c) Öffnen eines Fensters in der Hartmaskenschicht zum Freilegen der Siliziumschicht in einem Fensterbereich;
• (d) Abtragen der Siliziumschicht in dem Fensterbereich durch einen Trockenätzprozeß von einer ersten Siliziumschichtdicke d1 auf eine zweite Siliziumschichtdicke d2; und
• (e) Abtragen der Siliziumschicht in dem Fensterbereich durch lokale Oxidation des Siliziums und nachfolgendes naßchemisches Ätzen des gebildeten Siliziumoxids auf eine dritte Siliziumschichtdicke d3.

According to the invention, a method for producing an SOI substrate for an SOI field-effect transistor comprises the following steps in this order:

• (a) providing an SOI substrate in which a buried oxide layer is embedded between a crystalline silicon layer and a substrate;
• (b) applying a hard mask layer on at least a region of the silicon layer;
• (c) opening a window in the hard mask layer to expose the silicon layer in a window area;
• (d) removing the silicon layer in the window area by a dry etching process from a first silicon layer thickness d1 to a second silicon layer thickness d2; and
• (e) removing the silicon layer in the window area by local oxidation of the silicon and subsequent wet chemical etching of the silicon oxide formed to a third silicon layer thickness d3.

According to the invention, a two-stage removal process for the crystalline Silicon layer (top silicon layer) proposed. In a first anisotropic etching step, which is, for example, an RIE process (Reactive Ion etching), the silicon layer in the area of the later Channel of the SOI transistor "pre-thinned". Because the etch rates a dry etching process a pronounced one directionality have, the silicon layer in an anisotropic manner essentially thinned parallel to the normal direction of the substrate. in the Comparison is the etch rate along the resulting etching flanks the silicon layer, which is substantially parallel to the normal direction of the substrate run, significantly smaller.

By means of the dry etching process, the silicon layer is removed from an original thickness d1, which corresponds to the layer thickness of the top silicon layer of the SOI starting substrate, to a second, smaller silicon layer thickness d ₂ . A second removal process is then carried out, in which the already thinned silicon layer is reduced from the second silicon layer thickness d ₂ to a third, smaller silicon layer thickness d ₃ by means of local oxidation of the silicon to SiO ₂ and subsequent wet-chemical etching of the SiO ₂ .

The two-stage removal process of the silicon layer in the area of later Channel of the SOI transistor creates an edge profile in the top silicon layer, which clearly shows a subsequent processing of an SOI-MOSFET allows lower source-drain resistance (channel resistance). Removal processes that are carried out on a local Oxidation of silicon and subsequent wet chemical etching of the oxide based, defect-free and smooth etching fronts achieve. However, such a "one-stage thinned" silicon layer an edge profile, which a SOI MOSFET with comparatively great Channel resistance results. The cause is the isotropy of the local Oxidation and wet chemical etching based Ablation process of the silicon layer to name. Similar to so-called "birds beak" as used in the LOCOS process (local oxidation of silicon) is known, through the second removal step of the silicon layer also the flank areas of the top silicon layer etched. hereby there is an undesirable undercutting of the Hard mask layer on a length scale, which is of the order of magnitude of the etching depth in Corresponds to the normal direction of the substrate.

Through the two-stage removal process according to the invention the silicon layer effectively solves this problem. Thereby, that the Top silicon layer first is "pre-thinned" by an anisotropic dry etching process, only has to a smaller silicon layer thickness by means of the subsequent removal process removed by local oxidation and wet chemical etching become. Hence falls also the lateral undercut under the hard mask accordingly less. The result is a Edge profile of the silicon layer, which at the edge areas of the thinned Area has steeper flanks. This has the consequence that for the current flow of one Source or drain contact in or out of the transistor channel a larger "silicon volume" is available in the contact areas adjacent to the channel. This effect is particularly noticeable in short-channel transistors.

The hard mask layer can be, for example, a silicon nitride hard mask layer, which is deposited over the entire surface. Step (c) of opening the window in the hard mask layer preferably comprises a lithography and subsequent dry etching step for structure transfer. Since the later channel length of the SOI-MOSFET is determined by the geometrical dimension of the window in the hard mask layer, special requirements must be placed on the lithography step in the case of short-channel transistors with gate lengths of less than 100 nm. Electron beam lithography is preferably used in this case.

According to a preferred embodiment the first silicon layer thickness d1 in a range from 20 nm to 100 nm, preferably 25 nm to 35 nm. The silicon layer thickness d1 corresponds to the layer thickness of the single-crystalline silicon layer of the SOI substrate, which via the entire wafer is the same size. Since the silicon layer thickness d1 is at least 20 nm the silicon layer in "undiluted" Areas, i.e. especially in the source or drain regions of the SOI field effect transistor, sufficiently thick to withstand a pre-bake step to be able which is used to prepare the source or drain areas for a local Silicon epitaxy performed becomes.

Preferably, the third silicon layer thickness is d ₃ in a range of 3 nm to 15 nm, preferably 5 nm to 10 nm. The third silicon layer thickness d ₃ corresponds to the thickness of the channel to be processed SOI-MOSFETs. Channel thicknesses of less than 15 nm lead to SOI-MOSFETs with ultra-thin channels, which as FD-SOI-MOSFETs have advantageous properties compared to bulk-MOSFETs. In particular, short channel effects can be effectively suppressed in such MOSFET architectures.

The relationship preferably applies to the first, second and third silicon layer thicknesses d ₁ , d ₂ , d ₃
0.5 ≤ (i.e. 1 -d 2 ) / (D 1 -d 3 ) ≤ 0.9,
preferably 0.7 ≤ (d ₁ -d ₂ ) / (d ₁ -d ₃ ) ≤ 0.9.

The quotient (d ₁ -d ₂ ) / (d ₁ -d ₃ ) corresponds to the etching depth of the dry etching process in relation to the total etching depth of the dry etching process and the wet oxidation etching process. This ratio of dry etching depth to total etching depth is preferably greater than 0.5, so that a predominant part of the silicon layer is removed by means of the anisotropic etching process. Preferably, only a comparatively small layer thickness of the silicon layer is removed by the subsequent oxidation and wet chemical etching step. This enables the processing of "thinned" silicon layers, which are particularly well suited for the production of FD-SOI-MOSFETs.

The window area preferably has an essentially rectangular one Shape up, the shorter one edge length is in the range of 10 nm to 500 nm, preferably 20 nm to 40 nm. The shorter one edge length of the rectangular The window area corresponds to the channel length of the process to be processed SOI MOSFETs. The production method according to the invention has particular advantages in the area of short channel lengths which are below 100 nm in particular.

According to another preferred embodiment after opening (c) a hard mask spacer on the flanks of the window of the hard mask formed after the step (e) of removing the silicon layer Will get removed. Such a hard mask spacer, which for example can be formed from TEOS or from silicon nitride, with a usual Spacer formation process attached to the flanks of the hard mask, So that the Areas of the parallel to the normal direction of the substrate Hard mask are "protected" by the spacer. Through this hard mask spacer is a further improvement of the flank course of the top silicon layer in the thinned Channel area achieved. In particular, the additional Hartmaskenspacer the distance between the "undiluted" source or drain contacts and further reduced the transistor channel formed under the gate become.

• (f) Aufbringen eines Schutzoxids auf die Siliziumschicht in dem Fensterbereich;
• (g) Bilden eines Spacers an Flanken des Fensters der Hartmaske und an Flanken der Siliziumschicht in dem Fensterbereich; und
• (h) Abtragen des Schutzoxids.

According to a further preferred embodiment, the method comprises the further following steps:

• (f) applying a protective oxide to the silicon layer in the window area;
• (g) forming a spacer on flanks of the window of the hard mask and on flanks of the silicon layer in the window area; and
• (h) removing the protective oxide.

The spacer on the flanks of the window and the silicon layer in the window area prevents one later electrical short circuit between the source or drain contact on the one hand and the gate contact on the other. The spacer is preferably formed from silicon nitride or TEOS.

• (i) Aufbringen eines Gateoxids auf die Siliziumschicht in dem Fensterbereich;
• (k) Aufbringen von Polysilizium zumindest auf das Gateoxid zur Bildung eines Gates des Feldeffekttransistors;
• (l) Abtragen von auf der Hartmaske aufgebrachtem Polysilizium; und
• (m) Entfernen der Hartmaske.

According to a further preferred embodiment, the method comprises the further following steps:

• (i) applying a gate oxide to the silicon layer in the window area;
• (k) applying polysilicon to at least the gate oxide to form a gate of the field effect transistor;
• (l) removing polysilicon deposited on the hard mask; and
• (m) removing the hard mask.

A particular advantage of processing the Gate contact consists in the fact that no additional lithography step necessary is. Instead, it is a self-adjusting one Method in which the hard mask is used, which previously for thinning the top silicon layer was used.

Preferably, removal includes of the polysilicon according to step (l) a dry etching and / or a CMP process (chemical mechanical polishing). The polysilicon thickness is determined by the dry etching and / or CMP process which then up to the hard mask height ablated.

The hard mask preferably has one Layer thickness of 20 nm to 100 nm, most preferably 30 nm to 60 nm.

In summary, the method according to the invention sees a thinning the top silicon layer of the SOI substrate only in areas, which correspond to the channel areas of the SOI MOSFET to be processed, i.e. the areas under the gate. On the other hand the silicon layer in the source and drain regions does not thinned. As a result, the process technology makes contacting considerably easier and a high connection resistance can be avoided. Nevertheless, the necessary ultra-thin channel areas can be implemented. For the Costing is an advantage that none additional Mask needed becomes. The proposed process flow makes it possible to use transistors with different channel thicknesses and therefore variable electronic To produce properties. The generation of elevated source or drain areas (so-called "elevated S / D") by means of selective epitaxy is made possible by the chosen manufacturing process.

The invention is described below Reference to accompanying drawings of preferred embodiments described as an example. It shows:

1 - 12 Cross-sectional views of an SOI substrate with an SOI MOSFET in various stages of manufacture in accordance with preferred embodiments of the invention;

13a a cross-sectional view of an SOI substrate, which was thinned by local oxidation according to a method not according to the invention;

13b a cross-sectional view of an SOI substrate with a locally "thinned" channel region according to an embodiment of the invention; and

13c a cross-sectional view of the in 13b embodiment shown in a later process stage.

The invention is described below with reference to two preferred embodiments of the method according to the invention for producing a SOI substrate for an SOI field-effect transistor. The Figures show cross-sectional views of the process product in FIGS main stages of the process, irrelevant process steps such as for example, implantations are not shown.

The basic steps of the manufacturing process are described below using the 1 - 12 described.

In 1 the basic SOI material is shown in its unprocessed basic state. The SOI base material comprises a substrate Si, which in this case is a single-crystal silicon wafer. Using the so-called ELTRAN process, a typically 100 nm thick buried silicon oxide layer, which is referred to as buried oxide (BOX), was arranged on the silicon substrate Si. Adjacent to the surface of the buried oxide layer BOX facing away from the silicon substrate Si is a 30 nm thick single-crystalline silicon layer C-Si (so-called top silicon layer). The channel of the SOI field-effect transistor to be processed runs in this top silicon layer C-Si.

In a first lithography and etching step, the active areas (mesen) are first defined ( 2 ). As in 3 is shown, the mesa spacer MS is then processed. In the simplest case, a suitable spacer material, for example TEOS or silicon nitride, is deposited over the entire surface of the BOX and C-Si surface. Without a lithographic definition of the spacer regions being necessary, Mesaspacer MS can be formed on the mesa flanks by suitable control of the subsequent etching back step. Subsequently, as in 4 a nitride layer, for example 50 nm thick, is deposited for the hard mask HM. 5 shows the subsequent lithography step for defining the gate level. The lithography can be done optically as well as by alternative methods, for example by electron beam lithography. For this purpose, a suitable resist is spun on the hard mask layer, exposed and developed around a window 10 open in the resist so that in a window area 12 the surface of the hard mask HM is exposed. The structure is transferred from the resist into the hard mask HM using a dry etching step, for example an RIE etching step ( 6 ).

In 6a - 6f Two alternative, preferred embodiment variants of the method according to the invention are described which follow the stage of the method which is described in 6 is shown.

First, the in the 6a - 6c described method variant described. In order to generate a flank profile in the silicon layer C-Si that is as favorable as possible for the SOI-MOSFET to be processed, the silicon layer C-Si exposed in the window area is first locally thinned by means of a dry etching process, for example an RIE etching process. The areas 14 and 16 which later represent the source or drain regions of the silicon layer C-Si are not attacked by this removal process. The silicon layer C-Si is only removed in the window area 12 , so that the silicon layer thickness in the adjacent source and drain regions 14 . 16 is not reduced. Due to the strongly anisotropic etching behavior of the dry etching process used, steep etching flanks are generated, so that the silicon layer thickness of the single-crystal silicon layer C-Si changes abruptly in the flank region.

Following the anisotropic etching process a local oxidation of the silicon layer C-Si to SiO _{2 is used} with subsequent wet chemical etching back of the SiO ₂ . The surface of the silicon layer C-Si is smoothed by this combined oxidation and wet chemical etching step and thinned to its final silicon layer thickness d ₃ . In 6b the process stage is shown after the oxidation of the silicon layer C-Si has ended. As is known, for example, from the so-called LOCOS technology, the oxidation of the silicon layer C-Si leads to an isotropic oxidation, which also attacks the previously generated vertical flanks of the silicon layer C-Si. Furthermore, as schematically in 6b it is indicated that the hard mask HM is locally underpinned by the oxidation process. 6c shows the process product after completion of the wet chemical etching step with which the oxide layer is removed. Since only a small oxide layer thickness has to be removed by means of the wet chemical etching step, only a small "birds beak" is formed. In a subsequent process step (not shown), spacers SP are subsequently formed on the flanks of the silicon layer C-Si and the hard mask HM.

The one in the 6d - 6f The alternative process sequence described represents a further improvement of the manufacturing method according to the invention. In this manufacturing process, additional hard mask spacers HS are formed before the top silicon layer C-Si by means of the dry etching process in the window area 12 is thinned. The process product after the end of the dry etching process is in 6d shown. Similar to 6b and 6c a local oxidation step is then carried out, followed by a wet chemical etching step to remove the silicon layer C-Si to its final layer thickness d ₃ . In 6e the process product is shown before the wet chemical etching back step of the oxide formed.

After the etching step, spacers SP are formed in a spacer formation step on the flanks of the hard mask HM and the silicon layer C-Si. Since the hard mask HM is set back from the top silicon layer C-Si by the previously formed hard mask spacers HS, it is possible to form the spacers SP in such a way that they have only a minimal contact area with the top silicon layer C-Si. This has the consequence that the distance between the channel formed under a gate of the SOI-MOSFET to be processed and the source or drain region 14 . 16 is smaller than in the 6c illustrated embodiment is possible. At the in 6c In the illustrated embodiment, the spacer SP (not shown) occupies a larger space on the thinned top silicon layer. In other words, the distance between the source and drain regions 14 . 16 and according to the channel under the gate to be processed in the embodiment 6a - 6c greater. However, an increase in the distance between the channel and the source region results in an increase in the channel resistance, which can be particularly troublesome in the case of short-channel transistors. For such applications, this is accordingly based on 6d - 6f illustrated manufacturing process is advantageous.

In the 13a to 13c the advantage of a manufacturing method according to the invention with hard mask spacers HS compared to a conventional one-step thinning process of the silicon layer C-Si is again shown in highly schematic cross-sectional views. 13a shows an SOI substrate in which the top silicon layer C-Si is to be thinned exclusively by local oxidation and wet chemical etching back. As can clearly be seen, under-etching forms under the hard mask HM during the oxidation of the silicon layer, the dimensions of which essentially correspond to the depth of oxidation along the normal direction of the substrate. These undercuts, which are similar to the "birds beak" known from LOCOS technology, have disadvantageous properties on the source-drain resistance of the SOI-MOSFET. As in 13b and 13c such problems are effectively avoided in the preferred manufacturing method of the present invention. 13b , which essentially corresponds to the process state of 6d shows the silicon layer C-Si thinned locally by the dry etching. While the original silicon layer thickness is d ₁ , the silicon layer C-Si is thinned to a silicon layer thickness of d ₂ by the dry etching process. This is followed as in 13c it can be seen a further thinning of the silicon layer C-Si to the final silicon layer thickness d ₃ by means of local oxidation and wet chemical etching back. Compared to the conventional method according to 13a the significantly reduced birds beak is clearly visible.

In contrast to the in 6 Embodiments shown in the in 13b and 13c embodiment shown a protective oxide 18 applied between the silicon layer C-Si and the hard mask HM.

The further process steps, which are related to the 6c and 6f connect, are based on the 7 to 12 described. This in 6c and 6f Protective oxide (not shown) of the silicon layer C-Si, which was applied before the spacer formation and is, for example, 3 nm, is subsequently replaced by the gate oxide GOX. As in 8th is shown, polysilicon poly-Si is subsequently deposited over the entire area for gate formation. Anisotropic etching back, for example using RIE or CMP, limits the gate material to the corresponding gate areas. Advantageously, no further lithography step in the gate plane is necessary for this, so that the gate material is placed in a self-adjusting manner (cf.

9 ). 10 shows the process product with removed hard mask HM and spacers SP. Rounding oxidation (for example RTO) removes the "ears" of the gate material, 11 , Then, as in 12 is shown, the formation of the gate spacer GS, for example, from TEOS or nitride.

10

window

12

pane

14

source region

16

drain region

18

protective oxide

BOX

verbrabenes oxide

C-Si

Top silicon layer

GOX

gate oxide

GS

gate spacers

HM

hard mask

HS

Hartmaskenspacer

MS

Mesaspacer

Poly-Si

polysilicon

Si

silicon substrate

SP

spacer

Claims (11)

A method for producing an SOI substrate for an SOI field effect transistor comprising the following steps in this order: (a) providing an SOI substrate in which a buried oxide layer (BOX) between a crystalline silicon layer (C-Si) and a substrate (Si ) is embedded; (b) applying a hard mask layer (HM) on at least one area of the silicon layer (C-Si); (c) opening a window ( 10 ) in the hard mask layer (HM) to expose the silicon layer (C-Si) in a window area ( 12 ); (d) removing the silicon layer (C-Si) in the window area ( 12 ) by a dry etching process from a first silicon layer thickness d ₁ to a second silicon layer thickness d ₂ ; and (e) removing the silicon layer (C-Si) in the window area ( 12 ) by local oxidation of the silicon and subsequent wet chemical etching of the silicon oxide formed to a third silicon layer thickness d ₃ . The method of claim 1, wherein the first silicon layer thickness d _{1 is} in a range from 20 nm to 100 nm, preferably 25 nm to 35 nm. Method according to one of claims 1 or 2, wherein the third silicon layer thickness d _{3 is} in a range from 3 nm to 15 nm, preferably 5 nm to 10 nm. Method according to one of the preceding claims, wherein for the first, second and third silicon layer thickness d ₁ , d ₂ , d ₃ the relationship 0.5 ≤ (i.e. 1 -d 2 ) / (D 1 -d 3 ) ≤ 0.9, preferably 0.7 ≤ (d ₁ -d ₂ ) / (d ₁ -d ₃ ) ≤ 0.9. Method according to one of the preceding claims, wherein the window area ( 12 ) has an essentially rectangular shape, the shorter edge length of which is in the range from 10 nm to 500 nm, preferably 20 nm to 40 nm. Method according to one of the preceding claims, wherein after step (c) of opening the window ( 10 ) a hard mask spacer (HS) on the flanks of the window ( 10 ) the hard mask (HM) is formed, which is removed after step (e) of removing the silicon layer (C-Si). The method of claim 8, wherein the hard mask spacer (HS) is made of TEOS is formed. Method according to one of the preceding claims, comprising the further following steps: (f) applying a protective oxide to the silicon layer (C-Si) in the window area ( 12 ); (g) forming a spacer (SP) on the flanks of the window ( 10 ) the hard mask (HM) and on the flanks of the silicon layer (C-Si) in the window area ( 12 ); and (h) removing the protective oxide. Method according to one of the preceding claims, comprising the further steps below: (i) applying a gate oxide (GOX) to the silicon layer (C-Si) in the window area ( 12 ); (k) applying polysilicon (poly-Si) at least to the gate oxide (GOX) to form a gate of the field effect transistor; (l) removing polysilicon (poly-Si) applied to the hard mask (HM); and (m) removing the hard mask (HM). The method of claim 9, wherein removing the polysilicon (poly-Si) according to step (1) includes a dry etch and / or a CMP process. Method according to one of the preceding claims, wherein the hard mask (HM) has a layer thickness of 20 nm to 100 nm.