DE10235814B3 - Process for detachably mounting a semiconductor substrate to be processed on a supporting wafer used in the production of semiconductor components comprises thinly grinding the substrate and removing the substrate from the wafer - Google Patents

Abstract

Process for detachably mounting a semiconductor substrate (3) to be processed on a supporting wafer (1) comprises thinly grinding the substrate and removing the substrate from the wafer. The wafer is connected to the substrate or detached from it by applying a direct voltage.

Description

The present invention relates on a method for solvable Assembly of a semiconductor substrate to be processed on a carrier wafer according to the preamble of claim 1.

Such a method is, for example, from the publication DE 199 58 803 C1 known.

Currently semiconductor devices increasingly on very thin Semiconductor wafers or wafers produced, so-called ultra-thin wafers or disk-shaped objects thinner than Are 100 μm. This is usually done Semiconductor wafers are used which have a standard thickness of 500 to 700 μm and that before the completion of respective semiconductor components ground thin become.

However, such ultra-thin wafers are due their mechanical properties very difficult to handle and leave not with the same manufacturing machines and transport and holding devices process like wafers with a conventional standard thickness. Therefore have to especially for ultrathin Wafer modified manufacturing machines and transport devices are manufactured for special wafer cassettes are designed and especially for ultra-thin wafers constructed, usually manually operated gripping devices for loading the Have manufacturing machines.

Furthermore, the devices to fix the ultra thin Wafer while the actual manufacturing process, such as chucks, more or less expensive for rebuilt the requirements of the so-called ultra-thin product wafers. About that are also modifying manufacturing machines for the purpose processing and handling of ultra-thin wafers due to their increasing complexity set narrow limits.

The provision of such new ones or modified manufacturing machines for processing ultra-thin wafers is therefore extremely expensive and expensive.

For Processes that do not involve any temperature treatment For example, known processes that use ultra-thin product wafers with a wax or a double-sided adhesive film on a carrier wafer fasten it again afterwards by exposure to temperature to solve.

There are also manufacturing processes a connection between a product wafer and a carrier wafer known, the higher ones too Withstand temperatures. However, the use here is disadvantageous of metal-containing, aqueous Silicates and phosphates as binders, especially at higher temperatures the electrical properties of semiconductor components to be trained in the product wafer can or special etching processes require.

The effort of this conventional However, the process is relatively high, since consumption is particularly high of wear materials and sacrificial layers as well as for whole wafers increase the cost. Furthermore, there are often a variety of cleaning procedures the separation of the product wafer from its carrier wafer necessary, which in turn a danger of possible Break and elongated Include process runtimes.

From the publication JP 4-206 948 A an electrostatic chuck is known in which an internal electrode is embedded in a ferrodielectric ceramic, for example made of barium titanate.

In the same way is also from the publication JP 4-367 247 A a ceramic electrostatic chuck is known which has a ferroelectric ceramic with a high dielectric constant as a dielectric on an internal electrode to improve the holding forces.

From the reference “Hartsough, L. D .: Electrostatic Wafer Holding ... "Solid State Technology, 1993, January, pages 87-90 are also the basic principles of electrostatic fastening of semiconductor wafers, especially in electrostatic chucks (ESC) described, for example on an electrically conductive electrode a dielectric made of lead zirconium titanate (PZT) for fixing a connection surface is formed into a product wafer.

From the publication US 3,993,509 A method for holding a semiconductor substrate in an internal implantation is known, wherein dielectrics with a dielectric constant> 1000 are used to improve the holding forces.

From the publication US 4,724,510 A method for electrostatic wafer mounting is known, wherein concentric electrically conductive rings are designed as “interdigitated” electrodes in an n-type silicon semiconductor substrate.

The other publication US 4,554,611 discloses a further electrostatic chuck in which a charge-storing dielectric is formed on an electrode as a connection surface for a product wafer to be held. An electrically conductive ring which is in contact with the product wafer, together with the electrode, serves to apply a potential difference, as a result of which the product wafer is attracted to the holding device.

From the pamphlets US 4047214 and US 6333202 Transfer techniques are known in which ferroelectric layers are produced on a first substrate and then transferred to the product substrate.

From the publication US 4,047,214 a ferroelectric field effect transistor is known, which with is bonded to a semiconductor substrate by means of electrostatic forces. A lead zirconium titanate (PZT) is used as the dielectric.

The publication US 6,333,202 relates to a so-called FERAM cell, the ferroelectric material being converted into so-called “perovskite oxide” at temperatures greater than 600 ° C.

From the publication DE 44 46 703 A Finally, the use of a field plate structure on substrate edges to avoid field strength concentrations and rollovers caused thereby is known.

Furthermore, from the literature “Wright, et al .: Manufacturing issues of electrostatic chucks ... "J. Vac. Sci. Technol. B, ISSN 0734-211X, 1995, Vol. 13, No. 4, pages 1910-1916 known, for printing or removing a product from an electrostatic Hold a negative or opposite voltage to apply the respective electrodes, which means that of a permanent Polarization of the dielectric used resulting residual forces compensated or can be canceled.

In contrast, the invention is the Task based on a method for the detachable assembly of a processable Semiconductor substrate on a carrier wafer to create, a processing much easier and economical is.

According to the invention, this object is achieved by activities of claim 1 solved.

In the further subclaims are characterized further advantageous embodiments of the invention.

The invention is set out below Hand of working examples described in more detail with reference to the drawing.

Show it

1A to 1C simplified sectional views to illustrate essential process steps in the production of a releasable connection between two disc-shaped objects;

2 a simplified sectional view of a carrier wafer with product wafer according to a first embodiment; and

3 a simplified and enlarged sectional view of a carrier wafer with product wafer according to a second embodiment.

Figures 1A to 1C show simplified sectional views to illustrate essential process steps in the production of a releasable connection between two disc-shaped objects 1 and 3 by means of a ferroelectric layer 2 ,

According to 1A is a first step in a connecting step, a first electrically conductive disc-shaped object 1 such as a metal disk and preferably a conventional semiconductor wafer made of, for example, Si as carrier wafer, wherein, for example, a surface treatment of the two main surfaces or at least one connection surface is carried out, which connects to a second electrically conductive disk-shaped object 3 or a Si product wafer.

On this possibly pretreated connection surface of the disk-shaped object or carrier wafer 1 then becomes a ferroelectric layer 2 formed, which can form a high dielectric constant and / or a permanent electrical dipole moment D at least at a predetermined voltage or potential difference. Then the second electrically conductive disc-shaped object 3 again with its connection surface onto the ferroelectric layer 2 placed, preferably an already processed ultra-thin or a product wafer to be thinned, ie again semiconductor wafer (Si) is placed.

For the actual fixing, all that is now required is a direct voltage DC to the first and second electrically conductive disk-shaped objects 1 and 3 are applied, as a result of which charges L of opposite polarity are present in the disk-shaped objects acting as electrodes 1 and 3 train and change the ferroelectric layer 2 to the effect that at least an increased dielectric constant and / or a permanent electrical dipole moment D is formed. Because of these charges L or due to the dipole moment D, the ferroelectric layer results 2 an attractive (electrostatic) force between the first and second electrically conductive disc-shaped objects 1 and 3 , which enables sufficient fixation for further processing or processing without the use of adhesives, waxes or bonding materials.

According to 1B can consequently, even after removing the DC voltage DC, the second disc-shaped object 3 together with the first disc-shaped object 1 further processed or processed, resulting in the shatterproof properties, especially when using very thin disc-shaped objects.

The maintenance of force takes place essentially through that in the ferroelectric layer 2 trained permanent electrical dipole moment D, which in the electrically conductive disc-shaped objects 1 and 3 Appropriate free charge carriers binds and thus the electrical field necessary for the attractive force between them disc-shaped objects. Accordingly, when using a ferroelectric layer 2 with dipole moment properties that in the disc-shaped objects 1 and 3 excess charges are also eliminated, which means that sensitivity to leakage currents is very low.

On the other hand, however, even in the case of a ferroelectric layer without formed dipole moments D, a necessary attraction force can only be formed by the accumulated charges L and the increased dielectric constant, but with a possible loss of charge also a respective attraction force between the disk-shaped objects 1 and 3 decreases and thus adequate insulation of the disc-shaped objects 1 and 3 to avoid leakage currents or an outflow of the charges L is important.

For releasing the second disc-shaped object 3 from the first disc-shaped object 1 with its ferroelectric layer 2 is according to 1C only a release voltage -DC opposite to the connection voltage is applied to the two disc-shaped objects or a short circuit is generated, as a result of which the stored charges L can flow away and, if a permanent electrical dipole moment D is generated, an opposite electrical field is formed to release the second disc-shaped object. In this way, a mechanically resilient connection can be formed up to a Curie temperature range (thermal resolution of the dipole moment) of approx. 350 ° C. without the use of bonding processes, adhesives and thus necessary cleaning procedures.

2 shows a simplified sectional view of a carrier wafer T according to the invention with associated product wafer P, as are used according to a first embodiment. The same reference numerals designate the same or corresponding elements or layers, which is why a repeated description is omitted below.

According to 2 a carrier wafer consists of a carrier material or a disk-shaped object 1 with a ferroelectric layer 2 for defining a connection surface. The electrically conductive carrier material 1 consists for example of a metal or a (doped or intrinsic) semiconductor material and preferably of a conventional Si semiconductor wafer.

In order to increase a charge carrier concentration or the free charges necessary for the electrosatic attraction, the semiconductor wafer can additionally have a doping of the first conductivity type, for example p. On the remaining surface of the semiconductor wafer or carrier material 1 is an insulating layer 7 with the exception of a contact opening 10 formed, which has a silicon oxide layer, for example. Because of this first layer of insulation 7 there may be a loss of charges L in the carrier material 1 are reliably prevented, as a result of which even ferroelectric layers with only the ability to form an increased dielectric constant are sufficient when a field is applied as a dielectric.

According to 2 is on the connection surface or the ferroelectric layer 2 an ultra-thin or to be thinned product wafer P with a second disk-shaped object 3 hung up. The disk-shaped object preferably also exists 3 made of an electrically conductive material such as a metal and preferably of a semiconductor material, which, however, to avoid space charge zones or depletion zones, is one of the first conductivity types of the carrier material 1 has opposite doping of the second conductivity type (eg n). Again, the product wafer P can also have a second insulating layer 6 for isolating the remaining surface of the second disc-shaped object 3 have, in turn preferably silicon oxide is thermally formed or deposited and a contact opening 9 is trained to apply a connection or release voltage.

To form the largest possible contact area between the ferroelectric layer 2 and the second disc-shaped object 3 it is advantageous to the connecting surface of the second disc-shaped object 3 or the product wafer P with a ductile or easily deformable metal layer 4 To be provided, whereby a usually untreated and therefore wavy back of the product wafer P can be leveled, whereby an attractive force is increased. In addition, the use of the metallic material allows a greater density of charges L to be absorbed than is possible, for example, in the semiconductor material (Si).

In addition, on the surface of the ferroelectric layer 2 a protective layer of precious metal 5 be formed. Precious metal is preferred because it does not form an additional capacitor in the form of a native oxide.

For the ferroelectric layer 2 a dielectric with a particularly high dielectric constant is used to promote the electrostatic attraction. A distinction is made here between ferroelectric layers, which can assume a permanent, electrical dipole moment D, the orientation of which can be changed abruptly with an hysteresis by an external electrical field. A typical representative of such materials is, for example, lead-zirconium-titanate (PZT), in this case, when a certain polarization is taken, energy is stored in the dielectric that can hardly diffuse into the environment and thus also when the DC voltage is released or in the event of loss of excess charges L a reliable high attraction guaranteed.

Alternatively, there are also ferroelectric layers without hysteresis, which can only assume high induced dielectric constants, of which a typical representative is barium strontium titanate (BST). If, in the case of capacitances formed with such ferroelectric layers, the introduced excess charges L from the electrodes or the disk-shaped objects 1 and 3 diffuse into the environment (leakage current), the attractive force between the disc-shaped objects acting as capacitor plates will also 1 and 3 to zero.

In the practical implementation for the production of the ferroelectric layer 2 can on the one hand liquid precursor on the carrier material 1 spun on and then crystallized at temperatures of approx. 700 ° C. Alternatively, however, MOCVD methods can also be used.

In this way, ferroelectric layers are obtained with dielectric constants of ≥ 1000, where due to the crystallization temperature of 700 ° C or more operating temperatures of up to 350 ° C are also possible in principle.

The Curie temperature here is that Temperature at which the ferroelectric layer is not permanent Dipole moment D can take more, which is why processes such as Formiergastempern, one possible Show borderline case and possibly only using the remaining excess charges L the necessary attraction can be generated.

In processes or further processing, at which temperatures of 250 ° C however not exceeded permanent electrical dipole moments remain continue to receive, which is why a resulting attraction is present and the requirements for electrical insulation or avoiding leakage currents are significantly reduced in this temperature range.

Furthermore, according to 2 in an edge region of the first disk-shaped object 1 or the carrier wafer T a field plate structure 8th the ferroelectric layer 2 be trained to reduce an electric field strength. To be more precise, it must be taken into account at the edge of the wafer that the surrounding air cannot break down as high field strengths as the ferroelectric layer 2 , which is why the field strengths in a conventional dielectric are indicated by the indicated field plate geometry or structure 8 7 such as again reducing silicon oxide so much that there are no flashovers on the surface of the wafer edges.

The contact openings 9 and 10 are preferably designed in such a way that they expose only very small areas of the first and second disk-shaped object, for example in order to apply the corresponding DC voltage for the connection and disconnection process via a needle contact.

In order to implement the present invention, some electrostatic calculations are given below:
a contact pressure p, with which the two conductive electrodes of an infinitely large plate capacitor are pressed against its dielectric, follows p = ½ × (ε 0 ε d U 2 ) / D 2 . where U is the applied voltage, d is the thickness and ε _{d is} the dielectric constant of the dielectric.

While dielectric constants ≥ 500 are currently not a problem, but breakdown voltages must be limited to 100 to 200 kV / cm, for example for the ferroelectric layer 2 a dielectric constant of 500 and a thickness of 1 μm can be selected, a pressure of 2.2 × 10 ⁵ Pa being obtained when a voltage of 10 volts is applied (approx. double atmospheric pressure). This is more than sufficient to firmly bond two wafers together.

However, further considerations must now be made. Assuming that serial to the ferroelectric layer 2 another thin native oxide layer or a glass protective layer 5 is formed, for which a thickness of 2 nm with a dielectric constant of 3.6 is used, for example, the compressive force in the resulting series connection is thereby reduced to approximately 1.7 × 10 ⁵ Pa. To avoid such an effect, it is therefore used as a protective layer 5 for example, a metal protective layer and preferably a noble metal is used.

Furthermore, attention now has to be paid to what percentage of the area the contact between the two disc-shaped objects 1 and 3 is made at all. Since the back of an ultra-thin product wafer P, for example, is usually not polished, the contact area can be reduced to a few percent. With a contact area of approx. 2%, this results in a contact force between the two wafers of approx. 3 kg (weight, which is additionally placed on top). Such a contact force will still be sufficient for most applications.

The situation is more critical, however, if one wants to use the carrier wafer T for fastening a front side of a product wafer P, which has a structure of an intermediate oxide 11 Is provided.

3 shows a simplified sectional view of a carrier wafer with a product wafer, in which such a constellation is present. The same reference numerals again designate the same or corresponding elements or layers, which is why a detailed description is omitted below.

Accordingly, should the present invention also be used to thin a product wafer that already has a structure of, for example, intermediate oxides on its front side or connection surface 11 and pn junctions 12, the thickness d1 of the ferroelectric layer 2 with its increased dielectric constant and optionally present permanent dipole moments D can be significantly larger than a thickness d2 of this intermediate oxide structure 11 , Only when d1 is very much larger d2 can the negative charges L of the product wafer P which are in accumulation and the positive charges L of the carrier wafer T which are also in accumulation attract each other sufficiently strongly to realize the required attraction force.

An example is a d2 = 1 μm thick intermediate oxide structure 11 used, wherein a thickness d1 of the ferroelectric layer is 10 microns. If one now applies a voltage U = 100 volts and assumes a 100% contact area, the series connection of the two capacitors results in a compressive force of only 1.5 × 10 ⁴ Pa. From this it can be seen that the reserves with respect to the contact area are considerably smaller, but the situation is due to a thicker ferroelectric layer 2 and a higher voltage can be easily compensated.

At the end of the numerical considerations, the charge adhering to the two electrodes of the capacitor may be determined, for example, assuming approx. 0.35 C / m ² . If one compares such a charge with that which is introduced into a wafer with a typical rear side implantation of 1 × 10 ¹⁵ atoms / cm ² , this can be determined to be 1.69 C / m ² . When carrying out the invention, it must therefore be taken into account that processes such as ion implantations, plasma etching, plasma CVD or sputtering have a charge balance on the ferroelectric layer 2 not significantly disturb.

The invention has been described above Hand of silicon semiconductor wafers described as disc-shaped objects to be contacted. However, it is not limited to and includes the same Corresponding electrically (semi) conductive objects. Further The invention was based on special ferroelectric layers described. However, it should be noted that corresponding alternative materials with the same or similar properties are used can be.

1

first disc-shaped object

2

ferroelectric layer

3

second disc-shaped object

4

ductile metal layer

5

Metal protection layer

6 7

first, second layer of insulation

8th

Field plate structure

9 10

contact openings

11

Intermediate oxide structure

12

pn junction

L

charges

D

permanent electrical dipole moment

DC

DC

T

carrier wafer

P

product wafers

Claims (13)

Method for detachable assembly of a semiconductor substrate to be processed ( 3 ) on a carrier wafer ( 1 ), with the carrier wafer ( 1 ) semiconductor substrate connected on a connection surface ( 3 ) goes through several process steps, one of which is a thin grinding of the semiconductor substrate ( 3 ), and the thinly ground semiconductor substrate ( 3 ) from the carrier wafer ( 1 ) is separated, characterized in that the carrier wafer ( 1 ) with the semiconductor substrate ( 3 ) connected or detached from it. Method according to claim 1, characterized in that the several process steps that the with the carrier wafer ( 1 ) connected semiconductor substrate ( 3 ), selected from the set: internal implantation, plasma etching, plasma CVD and sputtering. Method according to claim 1 or 2, characterized in that that the DC voltage for connection takes on a value DC. Method according to claim 1 or 2, characterized in that that the DC voltage to release takes a value of -DC. Method according to one of the claims 1 to 4 , characterized in that on the connection surface of the carrier wafer ( 1 ) a ferroelectric layer ( 2 ) is trained. Method according to one of the claims 1 to 5 , characterized in that the carrier wafer ( 1 ) a semiconductor wafer with a to the semiconductor substrate ( 3 ) has opposite doping. Method according to one of the claims 5 or 6 , characterized in that as a ferroelectric layer ( 2 ) a lead-zirconium-titanate layer for Realization of a permanent electrical dipole moment (D) is formed. Method according to one of the claims 5 or 6 , characterized in that as a ferroelectric layer ( 2 ) a barium-strontium-titanate layer is formed in order to achieve a high dielectric constant. Method according to one of the claims 1 to 8th , characterized in that on the connection surface of the semiconductor substrate ( 3 ) a ductile metal layer ( 4 ) is trained. Method according to one of the claims 5 to 9 , characterized in that on the surface of the ferroelectric layer ( 2 ) a protective metal layer ( 5 ), preferably made of a noble metal. Method according to one of the claims 5 to 10 , characterized in that in an edge region of the carrier wafer ( 1 ) a field plate structure ( 8th ) of the ferroelectric layer ( 2 ) is designed to reduce a field strength. Method according to one of the claims 1 to 11 , characterized in that on a residual surface of the carrier wafer ( 1 ) and the semiconductor substrate ( 3 ) first and second insulating layers ( 7 . 6 ) is trained. Method according to claim 12, characterized in that in the first and second insulating layers ( 6 . 7 ) respective contact openings ( 9 . 10 ) are trained to apply the DC voltage.