DE10244446A1 - Semiconductor chip or semiconductor chip stack - Google Patents

Abstract

Semiconductor chips (1) or semiconductor chip stacks thinned for use in chip cards have arrangements of the directions (A, B) of sections of the conductor tracks (2) on a (1,0,0) upper side, which correspond to the {0,1,0} - Include planes and the {0,0,1} planes of the silicon crystal angles (6, 7) of at least 10 ° in order to increase the safety against breakage.

Description

The present invention relates to a semiconductor chip or semiconductor chip stack with an integrated Circuit which is intended for use in a chip card.

In chip cards, but also in electronic letter sorting systems, for example, the IC chips are exposed to sharp bends. The mechanical stability of many chips is not sufficient for this. If the chips are installed in a stabilizing housing, this inevitably involves an increase in the overall thickness. In the chip card area, the thickness of the chips is limited to 185 μm. The chip area is limited to a maximum of 25 mm ² to reduce the risk of breakage.

Because of the limitation of the maximum allowable thickness For the installation of two-layer chip stacks in chip cards the smaller one Chip can be thinned down to 60 μm. In the future, chip stacks with more than two layers will be used, whose chips are even thinned to less than 20 μm. Such thinned chips have a much lower mechanical stability than thick ones Chips and tend to break on the edge of the chip, which is over can spread the entire chip.

There is a cause for this problem especially in that the crystalline silicon of the chip substrate most easily breaks along the main planes of the crystal lattice. The location of the main planes in the crystal lattice of silicon (diamond structure) will with the Miller indices of the relevant equivalence classes {1,0,0}, (0,1,0} and {0,0,1}. For six-inch wafers made from (1,0,0) material an upper main side of the wafer is a (1,0,0) plane. The vertical the main levels of the other equivalence classes that run along this line perpendicular to each other and on the upper main side of the wafer. This fact is used to break down the wafer prepare. For this purpose, a small scratch is created on the edge of the silicon wafer, the as a disturbance works and causes a notch break. When bending the wafer runs from at this point, the break through the entire wafer. The wafer can be separated into individual semiconductor chips.

The chips surrounded by the scoring frame are common arranged on the wafer so that the internal semiconductor structures of the integrated circuits, the trenches for electrical isolation or to form memory cell transistors on the top applied conductor tracks and the like in each case along the main directions of the crystal are aligned. These structural elements therefore reinforce the risk of breakage of the semiconductor chip additionally. This is especially true in the case of much thinner Semiconductor chips.

This problem is increasing if multiple semiconductor chips in the course of vertical or cubic Integration connected to semiconductor chip stacks become. With vertical integration, the chips have to be ground particularly thin are provided, in particular if use is made in a chip card is. If the vertical integration chips are made as conventional, the tendency to break continues through the entire stack of chips.

Object of the present invention It is necessary to state how the risk of breakage is to be used in the chip card area thinned Chips, especially with vertical integration, can be reduced can.

This task is done with the semiconductor chip or the semiconductor chip stack with the features of claim 1 or 3 solved. Refinements result from the dependent claims.

It can still be a substrate made of crystalline silicon with a (1,0,0) plane as the top be used. The for the integrated circuit provided metallic conductor tracks become on the top, essentially along two perpendicular to each other Directions aligned with the {0,1,0} planes and the {0,0,1} planes Include an angle of at least 10 °. If the conductor tracks therefore diagonally across the Main crystal planes run, they have a mechanically stabilizing effect. The metallic conductor tracks are also polycrystalline or amorphous and can be deformed or stretched within certain limits. You act like this additionally mechanically reinforcing, roughly comparable to the fibers in a fabric-reinforced composite material.

In addition to this, straight lines and flat structures of components of the integrated circuit in the crystal also angles of at least 10 ° with the Include {0,1,0} planes and the {0,0,1} planes. For this purpose in the manufacture of the semiconductor chips, the components on the Wafer oriented at an angle, preferably between 15 ° and 45 °, to a main crystal plane, that runs perpendicular to the top of the wafer. Because of this alignment can the edges created during the structuring do not cause breakage.

Since the structures of the semiconductor components are defined by the photolithography used in the production, it is sufficient in principle for the production of a semiconductor chip according to the invention to insert the wafer into the stepper rotated by the specified angle during the exposure processes (i.e. flat or notch not below or to the side, but instead rotated by 15 ° to 45 °). All other process steps can remain essentially unchanged. In this way, the arrangement of the chips on the wafer is rotated compared to conventional production and the sawing lines are aligned at an angle to the apparatus. For the design and the routing in the semiconductor chip itself no changes, the internal structures of the semiconductor components can in particular still run parallel to the chip edge, which does not need to be sawed parallel to a main crystal plane.

In a semiconductor chip stack according to the invention are the semiconductor chips that form the individual circuit levels, aligned to each other in such a way that the vertical ones on the circuit levels Main crystal planes of successive semiconductor chips different from 0 ° and 90 ° Include angles, and preferably angles of different sizes. Since two successively arranged circuit levels over one another common metallization are connected as an interface, enough it when the metallization of at least one of two successive Semiconductor chips in from 0 ° and 90 ° different Angles to those perpendicular to the top of the semiconductor chip Main crystal planes is structured. If the semiconductor chips designed in this way to the semiconductor chip stack one above the other set and over the metallization are electrically connected the main crystal planes perpendicular to the circuit planes without further action in from 0 ° and 90 ° different Angles to each other. In another embodiment are only semiconductor chips with each other in the semiconductor chip stack connected that everyone already for is unbreakable due to the alignment of the conductor tracks described above are designed.

If the conductor tracks at least a part the semiconductor chips of the semiconductor chip stack at an angle to the Main crystal planes are aligned, but the side faces of the Chips, the chip edges, parallel to all semiconductor chips Sawed track sections then you can these side faces coplanar with each other. You just get one in this way limited chip stack, in which nevertheless in the individual circuit levels the positions of the main crystal planes perpendicular to the circuit planes are different. The main crystal planes perpendicular to the Layer levels can therefore stand even with just limited semiconductor chip stacks from chip to chip in from 0 ° and of 90 ° different Angles to each other.

A more detailed description of examples of the semiconductor chips or semiconductor chip stacks follows on the basis of FIG 1 and 2 ,

The 1 shows a schematic of a semiconductor chip in supervision.

The 2 shows a schematic of a semiconductor chip stack in cross section.

In the 1 is a semiconductor chip under supervision 1 with conductor tracks applied on an upper side 2 shown. The conductor tracks are essentially aligned along two mutually perpendicular directions. The sections of the conductor tracks are each arranged in the direction A or in the direction B, which in the 1 are drawn vertically or horizontally. The in the 1 The illustrated top of the semiconductor chip is coplanar to the {1,0,0} planes of the substrate or semiconductor crystal in question. In conventional semiconductor chips, the chip edges are 4 . 5 a {0,1,0} plane and a {0,0,1} plane. Instead, the {0,1,0} planes or the {0,0,1} planes run in one of the directions indicated by the two arrows. The chip edges 4 . 5 can however be sawn parallel to the conductor tracks. Instead, it is also possible to arrange the lateral chip edges in a direction shown by the arrows and in the direction perpendicular to them. The conductor tracks then run obliquely with respect to the chip edges.

The Indian 1 drawn angles 6 between the direction B in the 1 horizontal conductor track sections and the direction indicated by the arrow drawn on the right of the one main crystal plane or that to the angle 6 belonging supplement angle 7 is between 10 ° and 80 °, preferably between 15 ° and 75 °. The angle 6 is in the in the 1 example shown 67.5 °. The two directions, which are indicated by the arrows, form an angle of 45 degrees to one another.

In the case of a semiconductor chip stack comprising two semiconductor chips, if the main crystal planes of the semiconductor crystals or substrates form an angle to one another of, in this example, 45 °, if the conductor track sections of both semiconductor chips are aligned along directions A and B, the semiconductor chips become parallel with their vertical integration The respective metallizations aligned with one another are connected to one another in such a way that the main crystal planes of the chips are aligned at an angle of 45 ° to one another and thus stabilize one another. The chip edges 4 . 5 are parallel to the sections of the conductor tracks in this example 2 , while the main crystal planes of the chips, which are perpendicular to the circuit planes, form an angle of 45 degrees with one another and, with the relevant metallization of the respective chip, form an angle of 22.5 ° or 67.5 °.

The 2 shows an example of a semiconductor chip stack in cross section, in which on a lower semiconductor chip 1 a first further semiconductor chip 11 and a second further semiconductor chip 12 are arranged. The semiconductor chips are each with their tops 3 interconnected, which are coplanar to the {1,0,0} planes of the substrate or semiconductor crystal. In the simplified representation of the 2 are the structured metallizations between the semiconductor chips omitted.

The chip edges 4 . 5 on the sides of the in the 2 According to the invention, the cross section shown or within the plane of the drawing does not coincide with the other main crystal planes {0,1,0} and {0,0,1}. Rather, the chip edges are oriented at different angles to these main crystal planes. The chips in the stack can therefore be placed on top of one another in an edge-conforming manner, while those on the top are perpendicular 3 standing main crystal planes of two successive semiconductor chips, preferably in pairs of two semiconductor chips, are each aligned at angles different from 0 ° and 90 °.

One perpendicular to the top 3 of the semiconductor chip 1 standing main crystal plane can with a perpendicular on top 3 of the first further semiconductor chip 11 standing main crystal plane, for example, form an angle of 55 °. This vertically on the top 3 of the first further semiconductor chip 11 standing main crystal plane can with a perpendicular on top 3 of the second further semiconductor chip 12 main crystal plane, for example, form an angle of 17 °. This also means that between the relevant main crystal planes of the lower semiconductor chip 1 and the second further semiconductor chip 12 there is an angle of 55 ° - 17 ° = 38 ° or 55 ° + 17 ° = 72 °, which is different from the other angles 55 ° and 17 °. Here, the angles between the relevant main crystal planes are not only different from each other not only two successive but also any two pairs of semiconductor chips.

The conductor tracks of the chips in the semiconductor chip stack are at different angles to the main crystal planes aligned. This already ensures a certain level of break resistance. The Structures of the semiconductor components of the integrated circuit yourself can then with their straight or flat structures parallel or coplanar to the main crystal planes of the semiconductor crystal or Be aligned substrate. In a preferred embodiment However, these structures of the components themselves are also opposite to the main crystal planes at an angle of more than 0 ° and aligned less than 90 °.

This has the particular advantage that in this case the traces with their two main ones Directions outside of the main vertical crystal planes are still parallel can be aligned with the structures of the semiconductor components. at A special and preferred embodiment of the semiconductor chip stack can Semiconductor chips of the semiconductor chip stack are aligned with one another in this way be that the conductor tracks of the various semiconductor chips in Angles of 0 ° or 90 ° to each other are arranged, as is the case with conventional chip stacks is.

Because of the different orientation of the conductor tracks to the main crystal planes of the individual substrates, orientations of the main crystal planes which change from chip to chip are present within the semiconductor chip stack. Perpendicular to the tops of the chips, ie perpendicular to the {1,0,0} planes, there is therefore no uniform main crystal plane which extends through the entire semiconductor chip stack. This significantly increases the break resistance of the semiconductor chip stack. Such a semiconductor chip stack can therefore also be brought to a thickness of at most 185 μm with three and more semiconductor chips, which allows use in standardized chip cards. In the embodiment of the 2 is the semiconductor chip 1 for example 130 μm thick, the first further semiconductor chip 11 is 30 μm thick, and the second further semiconductor chip 12 is 20 μm thick.

1

Semiconductor chip

2

conductor path

3

top

4

chip edge

5

chip edge

6

angle

7

supplementary angle

11

first another semiconductor chip

12

second another semiconductor chip

A

direction

B

direction

Claims (6)

Semiconductor chip or semiconductor chip stack with at least one semiconductor crystal or a substrate made of crystalline silicon with equivalent classes of main planes of the crystal, which are denoted by the Miller indices {1,0,0}, {0,1,0} and {0,0,1} , wherein an upper side of the semiconductor crystal or substrate is formed by a (1,0,0) plane, with an integrated circuit and with metallic conductor tracks, which on the upper side formed by the (1,0,0) plane essentially are aligned along two mutually perpendicular directions, characterized in that the directions of the conductor tracks of a semiconductor crystal or substrate in question include angles of at least 10 ° with the {0,1,0} planes and the {0,0,1} planes. Semiconductor chip or semiconductor chip stack according to claim 1, in the straight and flat structures of components of the integrated circuit in the relevant semiconductor crystal or The substrate also has an angle of at least 10 ° with the {0,1,0} planes and include the {0,0,1} planes. Semiconductor chip stack, with the semiconductor chips with a semiconductor crystal or substrate made of crystalline silicon with equivalence classes of major planes of the crystal, which have the Miller indices {1,0,0}, {0,1,0} and {0,0,1}, with tops, each coplanar to the {1,0,0} planes of the semiconductor crystal or substrate, are permanently attached to each other and the semiconductor crystals or substrates are aligned with one another such that the {0,1,0} planes or the {0,0,1} planes of the semiconductor crystals or the substrates of successive semiconductor chips each in one of 0 ° and 90 ° different angles are arranged to each other. Semiconductor chip stack according to claim 1 or 2, the at least one further semiconductor crystal or another Crystalline silicon substrate is present with metallic Conductor tracks on an upper side formed by a (1,0,0) plane in the Essentially longitudinal two mutually perpendicular directions are aligned with the {0,1,0} planes and the {0,0,1} planes of the further semiconductor crystal or include substrate angles of at least 10 °, With semiconductor chips formed in the semiconductor crystals or substrates with tops, each coplanar to the {1,0,0} planes of the semiconductor crystals or substrates, permanently attached to each other are, the semiconductor crystals or substrates to each other are aligned with the directions of sections of the traces of the various semiconductor crystals or substrates each at an angle of 0 ° or 90 ° to each other are arranged, and the angles between the directions of Sections of the conductor tracks and the {0,1,0} planes or the {0,0,1} planes of the relevant semiconductor crystal or substrate for the existing semiconductor crystals or substrates in each case are different. Semiconductor chip or semiconductor chip stack according to one of claims 1 to 4, in which the total thickness is at most 185 μm. A semiconductor chip stack according to claim 5, which is more than contains two semiconductor chips, wherein at least one semiconductor chip is at most 20 μm thick.