DE10261500B4 - Processor and method for controlling a processor - Google Patents

Abstract

Processor with
A first program flow generation device (PFG) for generating first instructions (iw) as the basis for first control statements for at least one processing device (INTU, FFT, DFP),
A first control bus (p1) for transmitting the first instructions (iw) from the first program flow generator (PFG) to a first instruction decoder (IDC) for converting the first instructions (iw) into control instructions (iwx),
At least a second program flow generation device (SM, PFG2) for generating second instructions (iw2) as a basis for direct control instructions (iwx) for at least one processing device (INTU, FFT, DFP),
A second control bus (p2) for transmitting the second instructions (iw2) and
- a second instruction decoder (IDC2, DFP) with an upstream switching device (SW, SW *) for supplying either the first instructions (iw) from the first control bus (p1) or the second instructions (iw2) from the second control bus (p2).

Description

The The invention relates to a processor and a method for Controlling such a processor.

To control the flow and data processing in a processor, a processor, as is known 3 1, usually a program flow generation device (PFG) for converting a user-programmed software program into machine instructions or instructions (iw). If appropriate, the program flow generation device (PFG) and other devices of the processor are connected to a control and clock device (C). The instructions (iw) are forwarded via a control bus (p1) to processor controllers (IDC, IDC2) which translate the instructions (iw) into control instructions (iwx) which are sent to individual processors (INTU, FPU, X) are guided. The processing devices serve to process data (d), which are transmitted via data buses (d0, d1). Optionally, the processor additionally includes an address bus (a) for addressing various of the devices. Usually, a processor also has an internal memory (M) for temporarily storing data (d), instructions (iw), programs and / or addresses. Typically, a processor is also equipped with at least one interface (IF) for transmitting data, addresses and information to and from an external device.

current Digital signal processors are characterized in that they optimized arithmetic units or

processing facilities for one Fixed-point data type or, in the case of more complex variants, additionally for one Floating-point data type.

One essential optimization criterion and at the same time an essential one Characteristic for Signal processors is their data throughput.

One high data throughput is achieved by using multiple data buses over which the arithmetic units are supplied broadband with data achieved. The feeder The data is paralleled by so-called address generators to the arithmetic operations controlled by an instruction set executed.

at more modern signal processors, e.g. TMS 32C80 from Texas Instruments et. al., is additional increases the number of parallel arithmetic units.

adversely on the known approaches However, that is simultaneous with the increase in the number of buses and the computing units the complexity of the instruction set used to control the buses and arithmetic units is required, grows strongly. On the one hand, this causes the programming of these processors becomes very difficult and, secondly, that the word width of the instruction set and thus the memory requirements for the programming becomes very big. The corresponding technique is under VLIW (Very Long Instruction Word) known. Another problem of the described parallelization approach is the poor workload of the arithmetic units and buses that are causing it justified is that particular iterative and recursive algorithms are not always be parallelizable in a rigid form.

Farther The use of VLIW commands drag problems of synchronization by themselves, in different execution times for parallel Arithmetic operations are justified. This is typically done by accelerating slower parts through elaborate techniques with high power consumption or by artificial delay realized faster parts.

This causes either a significant increase in power consumption the processor, what for battery-powered applications is undesirable or leads to large pipeline delays have a negative impact on the achievable computing power.

The The object of the invention is a processor or a method to propose for controlling which has an improved Overall performance, in particular improved utilization of. processing facilities and allow buses.

These The object is achieved by a processor having the features of the patent claim 1 or by a method for controlling such a processor solved with the features of claim 8.

advantageous Embodiments are the subject of dependent claims.

Particularly advantageous is an embodiment with such a processor with a first program flow generation device for generating addresses and / or instructions as a basis for first control instructions, a first processing device control means for Um setting the instructions in control instructions for at least one first processing device for processing data, at least one further processing device for processing data, a second processing device control device for converting the instructions into control instructions for at least one second processing device and / or a further processing device for processing data at least one data line, in particular a data bus for transmitting the data from and / or to the processing devices and a first control bus for transmitting the instructions to the first processing device control device and the further processing device and with at least one second program flow generating device for generating addresses and or instructions as a basis for second control instructions and with at least one switching device for supplying either the first instructions or the second Instructions for the first and / or second processing device control device or the further processing device.

advantageously, In the case of a processor, on the one hand, the program flow generation device and the processing device controller for controlling the drain and data flow control formed. On the other hand, the Processing facilities separate from it for processing the data educated. This separation allows an optimization, since the transmission from data to and from the processing facilities as well as the data processing in these independent of the transmission and processing of instructions and control statements. The processor arrangement is thus divided into two parts into a flow and data flow control section and a data processing section.

According to one particularly preferred embodiment finds a division of several processing facilities for processing data to various processing device controllers instead, with the processing means controllers being independent of each other simultaneously can be operated. In order to make this possible, includes at least a portion of the processing device controllers a switching device comprising the processing device control device either to a standard program flow generator or to a separate program flow generator.

Around a decoupling of the flow and data flow control on the one hand and to optimize the data processing on the other hand, have the Processing facilities on the one hand connections to data lines or Data buses for the exchange of data and on the other hand connections to the assigned processing device control devices or a switching device for receiving control instructions.

In particularly preferred embodiment one of the extra Program flow generation means as state machine for Generating instructions for a standardized control process in the further processing device educated. this makes possible when using the further processing device than, for example Viterbi decoder or Fourier transform calculator for the further processing device after receiving according to processing data to transfer an automated control process, without reference to corresponding control statements of the standard program flow generation device to be instructed. As a result, the standard program flow generation device can use the Control bus and corresponding processing device controllers simultaneously address and operate other processing facilities. There is thus a real parallelization of processes, merely to coordinate the accesses to the data bus (s) are when the time consuming Data processing in the further processing device completed is. Further optimization can be achieved by transferring further, second Instructions to the Processor Controllers be made possible by providing another control bus. This also supports a parallelization, the instructions for the further control bus expediently from another, second program flow generation means provided become. This makes a more elaborate programming algorithm required, as for the two or more program flow generation devices have their separate ones Control taken into account in the program code must be possible but a more efficient operation of the processor through the parallelized data processing.

When using control statements from different sources, eg. As the further program flow generation means or a state machine, which generate and provide further instructions or control instructions are provided in accordance with switching devices which allow access to the various data sources. In this case, the instruction of the instruction source itself can advantageously be used as the switching instruction. In this regard, various embodiments are possible, such as examining the instruction for an address to which the switching device responds, or even the presence of an instruction at a particular one of the inputs of the switch direction.

A Analysis of the problems of the classic DSP approach described in the introduction (DSP: Digital Signal Processing), that the use of a central processing device control device, in particular instruction execution unit for parallel execution units these problems are causal pulls.

The basic idea The processor presented here is therefore a processor structure or a method for decentralizing the instruction execution to several parallel, loosely synchronized facilities and processes with own control logic in the form of at least one processing device controller.

The Expandable architecture of the Digital Signal Processor combined preferably a common RISC calculation kernel (RISC: Reduced Instruction Set computer / calculator with reduced instruction set) with data flow units for different types Data types.

• 1. Konsequente Aufspaltung des Prozessors und seines Instruktionssatzes in Ablauf-/Datenflusssteuerung (RISC-Teil) und Datenstrom-Verarbeitung (Datenfluss-Teil).
• 2. Minimierung bzw. Reduktion der Ausführungszeit für Operationen des RISC-Teils auf ein Minimum (typischerweise 1 Takt).
• 3. Realisierung von komplexen stark gepipelineten und datentypabhängigen Datenfluss-Operationen, wobei diese sowohl im Vordergrund, d.h. durch eine Prozessorinstruktion, als auch im Hintergrund, d. h. in einem parallelisierten Prozess, in dem der Datenfluss-Teil nach einer Initialisierung selbständig Daten anfordert und abgibt, ablaufen können.

This method is characterized by the following properties:

• 1. Consistent splitting of the processor and its instruction set into flow / data flow control (RISC part) and data flow processing (data flow part).
• 2. minimize or reduce the execution time for RISC part operations to a minimum (typically 1 clock).
• 3. Realization of complex highly pipelined and data type-dependent data flow operations, these being both in the foreground, ie by a processor instruction, as well as in the background, ie in a parallelized process in which the data flow part independently requests and delivers data after an initialization, can expire.

By This method also achieves a high utilization of the Arithmetic units and buses of the processor, adding the individual, possibly strong pipelined data flow units in time multiplex directly over the instruction set or in the background about in particular a suitable Memory access control, e.g. a DMA control logic (DMA: Direct Memory Access / Direct Memory Access) is achieved. Here you will find thus a switch between different required and advantageous processing facilities and / or processing purchases.

The Separation of execution units or Various facilities allow, for each of the execution units to program simple controls. The synchronization takes place via a Bus arbitration logic. This causes both a modularization and thus better maintainability / reusability of the software, as also a reduction of the memory requirements for the programs, since advantageously only relatively short programs for the individual blocks must be stored. The according to VLWI (Very Long Instruction Word), hard coupling of the various blocks is avoided in the present approach, which in a limited Number of data buses on average leads to an increase in data throughput.

embodiments will be explained in more detail with reference to the drawing. Show it:

1 Components of a processor arrangement according to a first embodiment,

2 Components of a processor arrangement according to a first embodiment and

3 Components of a processor arrangement according to the prior art.

A processor consists of a plurality of individual components, in particular stand-alone or controlled functional devices, of which in the 1 and 2 only those that are useful in understanding the particular processor arrangement of the control method are illustrated. Repetitions are preferably avoided in the description of the embodiments. In particular, the same names stand for comparable facilities.

The processor of the first embodiment is as shown 1 can be seen, split into a RISC part, a central instruction decoder IDC for the program control and the control of the RISC part, a plurality of memory blocks and a plurality of interface modules.

The individual modules shown in the block diagram are including their Characteristic characteristics listed below. there are the individual modules or facilities by a control bus p1 to transmit of instructions, one or more data buses d0, d1 and optionally an additional one Bus r for controlling interfaces IF, IF_1, ..., IF_k as internal or external interfaces. Also an additional address bus can be provided.

The RISC part contains the following components or fulfills the following tasks. These are associated with a program flow control, an address calculation for the data buses, a fast indirect memory access, eg a Huffman decoder known per se, an integer arithmetic, a bit stream manipulation device and a register bank.

Of the RISC part is an essential element of the processor concept of the first embodiment and also advantageous in the concept of the second embodiment used.

All Operations performed in the RISC part work advantageously on a register bank. Furthermore, all operations of the RISC part in the cited first embodiment preferably executed within a clock. This has the advantage that the latency for a data storage access is eliminated and all operations and their results in a very early pipeline stage available. Shorten it latencies in program loops, in jumps and in indirect memory access, which in turn simplifies programming and above all one increase the computing power results.

The Data flow processing takes place in one of preferably several Data flow processing units DFP instead. The data flow processing units DFPs are characterized by being data type dependent, directly access to several buses p1, d0, d1, a separate flow control included and a longer one Latency for their execution units need can.

A possible use the data flow processors or processing units is in the direct control of the arithmetic operation by the instruction set given.

The However, data flow processing units DFP are still too characterized in that once initiated, cyclically repeats operations To run can, the associated with Pointers of address generators of the RISC part to memory areas of the main memory M can access. This data access takes place via direct memory access (DMA) in the background, so to speak. In the foreground is expediently the memory access by the current instruction set. Under background memory access is to understand a low priority memory access, which takes place only when data buses are free.

From The data flow processing units DFP described here can have several operated in parallel in the background, these of course with each other to prioritize on bus access. This is despite it eventually long execution pipeline possible, the data bus occupancy, which is the criterion for performance of a digital signal processor is to maximize. The parallelization takes place through the bus arbitration logic in the instruction decoder or in the address generation unit instead of a rigid coupling by means of long instruction words.

typical examples for Data flow processing units DFP are a floating-point unit FFT processor (FFT: Fast Fourier Transformation / Fast Fourier Transformation) or a Viterbi decoder.

Especially preferred exemplary applications are an FIR filter calculation (Finite Impulse Response / finite impulse response) as a non-recursive Filter, a complex-valued mixer, a Galois field calculation or a DCT (DCT: Discrete Cosine Transform) processor.

The Data Flow Processing Units DFP make the extensible Part of the proposed architecture and may vary depending on the application integrated in different variants in the processor architecture become.

Of the One advantage of this expandable architecture is that the main part of a compiler, especially the part that the Program scheduling and program structuring concerns only needs to be realized once. The data flow processing units form in associated Program development tools typically as data type extensions so that the expandability of the proposed processor architecture also on the associated Extends tools.

Memory blocks Mem_0, Mem_1, ... are characterized in the specified embodiment, that they are each coupled to a plurality of data buses d0, d1. This allows it, by clever memory allocation during programming or by simultaneously using multiple data flow processing units DFP simultaneously to access multiple buses d0, d1 to increase data throughput.

The Interface modules IF, IF_1, ... are for data transfer between Processor core and external units provided. The connection of the interface modules can also be accessed through background memory access or through an interrupt (interrupt) logic take place.

In particular, it is possible to have the buses with an interface to outside the actual Processor design so that subsequent extensions to other such data flow processing units DFP can be made.

Of the Instruction decoder IDC, as a processing device controller, manages the Foreground commands of the processor while controlling the synchronization the foreground activity with the parallel background processes.

The The processor architecture described here is in the following areas can be used, in particular as a processor for audio signal processing, as a processor for high data throughput, e.g. For Video compression / decompression, for digital modem applications, especially radio / wireless modem applications, as a mixed controller processor and signal processing tasks or as a signal processor for applications with compiled execution code, requires special data types. Other facilities and functions, that in the first embodiment can be advantageously implemented or used, can be taken from the second embodiment become.

In the second embodiment, the processor arrangement as shown 2 it can be seen, in addition to a first control bus p1 in addition to a second control bus p2. Of course, an extension to even more tax busses can be implemented. While the first control bus p1 serves to receive instructions iw, also commonly referred to as a command or instructions, from a first program flow generator PFG and processing means VIT or memory means M directly controllable by various processor controllers IDC2 as a standard basis The second and further control buses p2 serve to transmit additional instructions iw2, which are generated by a corresponding additional program flow generator PFG2. These additional instructions or further instructions iw2 serve to selectively control the further processing device control devices IDC2 or also storage devices M in parallel to the first instructions iw, so that a parallel operation of the processing device control devices IDC, IDC2 and further processing devices VIT, M is made possible.

The Instructions iw, iw2 correspond to one in machine language implemented program code, the implementation of the program code into the machine language of the program flow generation facilities PFG, PFG2 performed becomes. The instructions can besides instruction data also information and address data exhibit. In the programming of such a processor arrangement is considered in the program code accordingly, that the different Program and generation facilities PFG, PFG2 for optimization the operation advantageously with separate program code sections be controlled.

to general control of the processor is used in particular by a control and clock C, which with different facilities of the Processor is connected, as it is known on its own. In particular, it is also possible to connect to an address generator A exist, which over an address bus a different devices, in particular different Processing facilities, external interfaces IF and one or several central memory devices M drives. The address control coordinates in particular the access of various institutions on data buses d0, d1, which for transmitting the actual to be processed or processed data in the processor arrangement are formed, as is also known.

At the illustrated embodiment become the default first Processing device controller, which is designed in particular as an instruction decoder IDC, the first instructions iw the standard first program flow generation device PFG supplied. The processing device controller IDC is used to translate the instructions iw into direct control statements iwx for various processing facilities X (DFP), FPU. The processing device controller IDC advantageously has a plurality of outputs which are the corresponding different processing devices X, FPU are connected. In addition to the translation of the instructions iw into the iwx control statements the processing device controller IDC controls the connected processing equipment. At present embodiment is in particular a sliding, calculation device FPU (Floating Point Unit) at the first processing device controller IDC connected. Furthermore, an additional processing device X for others specialized processing or general purpose processing the data d connected.

The further, second instructions iw2 of the second or further program flow generation device PFG2 serve to drive the second processing device control device IDC2 in parallel. This converts supplied instructions iw, iw2 into corresponding control instructions iwx, which are supplied to connected processing devices INTU, FFT. The special processing equipment, the of the illustrated second processing device controller IDC2 are an integer-number calculating means INTU and a foyer-transformation calculating means FFT. These processing devices are thus also used for special purposes of data processing.

Of the second processing device controller IDC2 is a Switching device SW upstream, which depending on the switching position either instructions iw the first program flow generation device PFG feeds, like that according to the state the technology for is known, or instructions iw2 the second program flow generation device PFG2 supplies. As a result, the second processing device control device IDC2 optional, as it is for you be known, operated, but can alternatively also directly in parallel to the first processing device controller IDC.

When Switching signal for the switching device SW can advantageously directly an instruction iw2 can be used on the second control bus p2. In this simple embodiment always switches the switching device SW2 automatically to the second control bus p2, if there is a signal or instructions iw2 issue. Alternatively, the switching device switches to the first Control bus p1.

alternative can but also different types of switching signals are provided. For example, can the switching device SW always one of the two control buses p1, Observe p2 and based on address information in the transmitted Instructions iw, iw2 determine from which of the two control buses p1, p2 retrieve the instructions iw, iw2 and to the second processing device controller To run ID2 are.

Besides that is in the illustrated processor arrangement, a further processing device VIT connected to the first control bus p1, the first instructions iw from the first program flow generation means PFG. In the illustrated embodiment this further processing device VIT is a Viterbi decoder which data d gets on one of the data buses d0, d1, processed and output again on one of the data buses d0, d1.

These Further processing device VIT also has a switching device SW * on, as an alternative to the instructions iw the first program flow generation means PFG further, second Instructions iw2 from a standalone program flow generation facility fed to get, which is in the form of a state machine SMausgebildet. By using the further switching device SW * can thus as required, control signals or instructions iw, sw2 from different control signal sources are supplied to the further processing device VIT.

This allows a parallel processing of standardized processes, such as for example, the execution a Viterbi algorithm, where a variety of standard expires Program steps to process the data d is to work. While this processing is the feeder the instructions iw the program flow generation device PFG not required so that it is not blocked accordingly, but for the generation of instructions iw for other processing device controllers IDC, IDC2 free remains. For the special processing will be the second iw2 instructions either generated directly from the state machine SM or one of these associated or external memory retrieved and deployed.

Advantageously 2 Two alternative embodiments with switching devices SW and SW * for supplying second instructions iw2, sw2 to a processing device controller IDC2 and another processing device VIT. Such arrangements can alternatively or as shown, operated in parallel. In particular, an extension to other program flow generation devices, control buses, processing device controllers and other processing devices as needed is possible.

alternative or additionally may also be the first processing device controller be equipped with an upstream switching device. In particular, it is possible in the switching devices SW * and / or the program flow generation devices in the form of independent State machines SM and the like corresponding instructions or provide control statements in a form as defined by the downstream processing device controllers IDC2 or further processing devices VIT for their ideal control are optimally suitable.

Claims (8)

Processor with - a first program flow generation device (PFG) for generating first instructions (iw) as a basis for first control instructions for at least one processing device (INTU, FFT, DFP), - a first control bus (p1) for transmitting the first instructions (iw ) from the first program flow generator (PFG) to a first instruction decoder (IDC) for implementing the first instructions (iw) in control instructions (iwx), - at least one second program flow generator (SM; PFG2) for generating second instructions (iw2) as a basis for direct control instructions (iwx) for at least one processor (INTU, FFT; DFP) - a second control bus (p2) for transmitting the second instructions (iw2) and - a second instruction decoder (IDC2; DFP) with an upstream switching device (SW; SW *) for supplying optionally the first instructions (iw) from the first control bus (p1 ) or the second instructions (iw2) from the second control bus (p2). The processor of claim 1 including a state machine (SM) as the second program flow generating means for generating the second instructions (iw2) for a standardized control flow the further processing device (SW *, VIT). Processor according to one of claims 1 or 2 with a Viterbi decoder (VIT), a Floating point calculator, an FFT processor (FFT: Fast Fourier Transformation), an FIR filter calculation (FIR: Finite Impulse Response), a complex mixer, a Galois Field Calculator or a DCT (DCT: Discrete Cosinus Transformation) processor as the further processing device (DFP, FFT, VIT, X). Processor according to one of claims 1-3, wherein said processing means control means (IDC2; IDC) and / or a switching device (SW *) with a program flow generation device (PFG, PFG2, RISC) which contain the instructions (iw, iw2) with a reduced instruction set. Processor according to one of claims 1-3, wherein the program flow generating device (s) (PFG, PFG2, RISC) Instructions (iw, iw2) with an instruction set for the Driving either only the first processor controller (IDC) on the one hand or only the second processing device control device on the other hand (IDC2) and / or the further processing device (SW *, VIT) is trained. Processor according to one of claims 1-5, wherein the at least one Switching device (SW, SW *) for supplying the second instructions (IW2) whenever second instructions (iw2) for the associated Processing device controller (IDU2) or the associated further processing device (VIT) present, is formed. Processor according to one of claims 1-5, wherein the at least one Switching device (SW) for feeding the second instructions (iw2) whenever the program flow generation means (PFG2) second instructions (iw2) for the associated processing device controller (IDU2) or the associated further processing device are announced, is trained. Method for controlling a processor after a the claims 1-7, at the - at least a processing device (SPU, INTU, VIT; DFP) for processing of data (d) by means of switching means (SW, SW *) for supplying optionally first instructions (iw) or second instructions (iw2) as addresses and / or control instructions from either a first program flow generator (PFG) or a second program flow generation device (SM; PFG2; IDC) is switched as needed, - Where a switching signal for the taken from the switching device instructions (iw; iw2) taken becomes.