DE10319541A1 - Semiconducting device, especially substrate- or circuit board-free re-wiring device on chip or chip scale package, has re-wiring device attached to first chip surface and corresponding bearer surface - Google Patents
Semiconducting device, especially substrate- or circuit board-free re-wiring device on chip or chip scale package, has re-wiring device attached to first chip surface and corresponding bearer surface Download PDFInfo
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- DE10319541A1 DE10319541A1 DE10319541A DE10319541A DE10319541A1 DE 10319541 A1 DE10319541 A1 DE 10319541A1 DE 10319541 A DE10319541 A DE 10319541A DE 10319541 A DE10319541 A DE 10319541A DE 10319541 A1 DE10319541 A1 DE 10319541A1
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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Abstract
Description
Die vorliegende Erfindung betrifft eine Halbleitervorrichtung und ein Verfahren zur Herstellung einer Halbleitereinrichtung, und insbesondere eine Substrat- bzw. Platinen-freie Umverdrahtungseinrichtung auf einem Chip oder ein Chip Scale Package (CSP).The present invention relates to a semiconductor device and a method for producing a Semiconductor device, and in particular a substrate or circuit board-free Rewiring device on a chip or a Chip Scale Package (CSP).
Die Entwärmung eines Halbleiter-Chips bzw. eines Halbleiter-Packages bereitet gerade bei den mit der fortschreitenden Entwicklung steigenden Taktfrequenzen Probleme. Ein effektiver Pfad zur Wärmeabfuhr vom Chip zum Board erfolgt z.B. über Interconnect-Elemente, wie Solder Balls, und/oder über einen möglichen Underfil. Soll ein Underfil jedoch vermieden werden, verbleiben die Solder Balls (Lotkugeln) als wesentlicher Entwärmungspfad.The cooling of a semiconductor chip or a semiconductor package prepares especially with the increasing clock frequencies with the advancing development Problems. An effective path for heat dissipation from the chip to the board e.g. via interconnect elements, like solder balls, and / or over one possible Underfil. However, if an underfil is to be avoided, remain the Solder Balls (solder balls) as an essential cooling path.
Die Wärmeabfuhr ist allerdings nur bei Lotkugeln gut, wenn sie so kurz wie möglich, d.h. insbesondere im Chip-Schatten bzw. der Chip-Breite, an den Chip gekoppelt sind. Wird eine Fan-out-Technologie verwendet, d.h. das Ball-out des Packages ist größer als der Chip-Schatten, tragen die Lotkugeln, welche im Fan-out-Bereich, d.h. außerhalb des Chip-Schattens, angeordnet sind nur sehr geringfügig zur Wärmeabfuhr bei. Zum einen liegt dies darin begründet, dass der Weg zwischen der Wärmequelle (Chip) und der Wärmesenke (kontaktierte Lotkugel) sehr lang ist. Zum anderen besteht der thermische Pfad meist aus thermisch schlecht leitenden Materialien, wie beispielsweise Polymeren, einer Leiterplatte, Mold- bzw. Gussmasse, usw. Ist der Chip sehr klein und das erforderliche Fan-out-Design der Umverdrahtungseinrichtung sehr groß, erfolgt eine schlechte Wärmeableitung. Derartige Halbleiter-Chips können bei erhöhter Leistungsaufnahme ein Zuverlässigkeitsrisiko darstellen.However, the heat dissipation is only good for solder balls if they are as short as possible, i.e. especially in Chip shadow or the chip width, are coupled to the chip. If fan-out technology is used, i.e. the ball-out of the package is bigger than the chip shadow, carry the solder balls, which are in the fan-out area, i.e. outside of the chip shadow, are arranged only very slightly heat dissipation at. For one, this is because the path between the heat source (chip) and the heat sink (contacted solder ball) is very long. On the other hand there is the thermal path mostly made of thermally poorly conductive materials, such as Polymers, a printed circuit board, molding or casting compound, etc. Is the Very small chip and the required fan-out design of the rewiring device very large, there is poor heat dissipation. Such semiconductor chips can with increased Power consumption is a reliability risk represent.
Betrachtet man ein herkömmliches
CSP gemäß
Definitionsgemäß liegen bei einem solchen CSP
alle Anschlusseinrichtungen
Der Hauptanteil der thermischen Kopplung zwischen Chip und der Umgebung erfolgt über die "Beine" des Chips zu dem nächsten Level des Boards. Kleine Chips verfügen lediglich über geringe Möglichkeiten der thermischen Kopplung, da entweder die Kugeln groß sind, dann sind nur wenige vorhanden, oder die Anzahl der Kugeln ist hoch, aber die Kugeln sind klein. Außerdem ist in vielen Anwendungsfällen die gewünschte Standard-Anschlusseinrichtungserstreckung größer als der Chip-Schatten, d.h. die Chip-Breite oder -Länge, so dass die bekannte CSP-Technologie, d.h. ein Fan-in-Design, nicht möglich ist.The main part of the thermal coupling between Chip and the environment is done over the "legs" of the chip to that next Board level. Small chips have only limited possibilities thermal coupling, because either the balls are large, then there are only a few, or the number of balls is high, but the balls are small. Moreover is in many use cases the desired Standard connector extension larger than the chip shadow, i.e. the Chip width or length, so the well-known CSP technology, i.e. a fan-in design, is not possible.
Es ist deshalb Aufgabe der vorliegenden Erfindung, eine Halbleitervorrichtung und ein Verfahren zur Herstellung einer Halbleitervorrichtung bereitzustellen, bei welcher eine Fan- out-Technologie bei dem Konzept einer Substrat- bzw. Platinen-freien Umverdrahtungseinrichtung auf einem Chip eingesetzt wird, um insbesondere die Entwärmung des Chips zu steigern.It is therefore the task of the present Invention, a semiconductor device and a method of manufacturing to provide a semiconductor device in which a fan-out technology in the Concept of a substrate or circuit board-free rewiring device is used on a chip, in particular the cooling of the chip to increase.
Erfindungsgemäß wird diese Aufgabe durch die im Anspruch 1 angegebene Halbleitervorrichtung und durch das Verfahren zur Herstellung einer Halbleitereinrichtung nach Anspruch 10 gelöst.According to the invention, this object is achieved by The semiconductor device specified in claim 1 and by the method to produce a semiconductor device according to claim 10.
Die der vorliegenden Erfindung zugrunde liegende Idee besteht im wesentlichen darin, eine Trägereinrichtung bzw. einen Rahmen um den Chip vorzusehen, auf dessen bündig mit der ersten Oberfläche des Halbleiter-Chips abschließenden Unterseite ebenfalls Anschlusselemente außerhalb des Chip-Schattens angeordnet sind.The basis of the present invention The idea essentially lies in a carrier device or a frame to provide the chip, on the flush with the first surface of the semiconductor chip Underside also connecting elements outside the chip shadow are arranged.
In der vorliegenden Erfindung wird das eingangs erwähnte Problem insbesondere dadurch gelöst, dass eine Halbleitervorrichtung bereitgestellt wird mit einem Halbleiter-Chip, welcher eine Kontakteinrichtung auf einer ersten Oberfläche zum Bereitstellen einer integrierten elektrischen Komponente aufweist; mit einer Trägereinrichtung über den nicht mit der Kontakteinrichtung versehenen Oberflächen des Halbleiter-Chips, welche sich seitlich über den Halbleiter-Chip hinaus erstreckt; und mit einer strukturierten Umverdrahtungseinrichtung zum elektrischen Verbinden der Kontakteinrichtung des Halbleiter-Chips mit einer Anschlusseinrichtung, wobei die strukturierte Umverdrahtungseinrichtung auf der ersten Oberfläche des Halbleiter-Chips und der entsprechenden Oberfläche der Trägereinrichtung aufgebracht ist, und sich die Anschlusseinrichtung seitlich über die Breite des Halbleiter-Chips hinaus erstreckt.In the present invention the aforementioned Problem solved in particular by that a semiconductor device is provided with a semiconductor chip, which a contact device on a first surface for Providing an integrated electrical component; with a carrier device over the surfaces of the Semiconductor chips, which overlaps laterally extends the semiconductor chip; and with a structured Rewiring device for electrically connecting the contact device of the semiconductor chip with a connection device, the structured Rewiring device on the first surface of the semiconductor chip and the corresponding surface the carrier device is applied, and the connection device laterally over the Width of the semiconductor chip extends beyond.
Auf diese Weise kann beispielsweise durch Übergießen eines Chips von der Rückseite bei abgedeckter Vorderseite des Chips, welche die Kontakteinrichtung aufweist, nachfolgend auf vorteilhafte Weise die herkömmlichen Herstellungsprozesse einer Umverdrahtungseinrichtung und des Aufbringens der Anschlusseinrichtung erfolgen.In this way, for example by pouring over one Chips from the back with the front of the chip covered, which is the contact device has, in an advantageous manner below the conventional Manufacturing processes of a rewiring device and the application of Connection set up.
In den Unteransprüchen finden sich vorteilhafte Weiterbildungen und Verbesserungen des jeweiligen Erfindungsgegenstandes.There are advantageous ones in the subclaims Further developments and improvements of the respective subject of the invention.
Gemäß einer bevorzugten Weiterbildung weist die Trägereinrichtung eine thermisch und/oder elektrisch leitfähige Einrichtung, insbesondere eine Metallschicht, auf. Eine solche Metallschicht ermöglicht eine bessere Wärmeverteilung bzw. Entwärmung des Halbleiter-Chips.According to a preferred development the carrier device a thermally and / or electrically conductive device, in particular a metal layer on. Such a metal layer enables one better heat distribution or cooling of the semiconductor chip.
Gemäß einer weiteren bevorzugten Weiterbildung ist über der elektrisch und/oder thermisch leitfähigen Einrichtung eine Schutzeinrichtung vorgesehen. Diese dient zur Verstärkung oder auch zur elektrischen Isolation der beispielhaften Metallisierung.According to another preferred Continuing education is about a protective device of the electrically and / or thermally conductive device intended. This is used for amplification or electrical Isolation of the exemplary metallization.
Gemäß einer weiteren bevorzugten Weiterbildung erstreckt sich die thermisch und/oder elektrisch leitfähige Einrichtung in der Breite zumindest bis zur seitlichen Erstreckung der Anschlusseinrichtung. Eine weiter verbesserte Entwärmung des Fan-out Packages wird somit vorteilhaft gewährleistet.According to another preferred The thermally and / or electrically conductive device extends in width at least up to the lateral extent of the connection device. A further improved cooling the fan-out package is thus advantageously guaranteed.
Gemäß einer weiteren bevorzugten Weiterbildung ist die thermisch und/oder elektrisch leitfähige Einrichtung an ein vorbestimmtes elektrisches Potential angeschlossen. Die Kopplung an ein Abschirmpotential kann auf diese Weise erfolgen.According to another preferred Further training is the thermally and / or electrically conductive device connected to a predetermined electrical potential. The coupling shielding potential can be done in this way.
Gemäß einer weiteren bevorzugten Weiterbildung ist die thermisch und/oder elektrisch leitfähige Einrichtung an die Anschlusseinrichtung angeschlossen. Dies birgt den Vorteil der Möglichkeit zur Nutzung der beispielhaften Metallfolie als gemeinsame, niederohmige Masseverbindung der verschiedensten Anschlusselemente der Anschlusseinrichtung.According to another preferred Further training is the thermally and / or electrically conductive device connected to the connection device. This has the advantage The possibility to use the exemplary metal foil as a common, low-resistance Earth connection of various connection elements of the connection device.
Gemäß einer weiteren bevorzugten Weiterbildung weist die strukturierte Umverdrahtungseinrichtung mindestens eine strukturierte Metallisierung und eine andersartig strukturierte elektrisch isolierende Schicht 15 auf.According to another preferred The structured rewiring device has further training at least one structured metallization and another structured electrically insulating layer 15.
Gemäß einer weiteren bevorzugten Weiterbildung ist die Trägereinrichtung, insbesondere die elektrisch und/oder thermisch leitfähige Einrichtung, über ein thermisch leitfähiges Klebemittel an den Halbleiter-Chip gekoppelt.According to another preferred Further training is the sponsoring institution in particular the electrically and / or thermally conductive device thermally conductive Adhesive coupled to the semiconductor chip.
Ausführungsbeispiele der Erfindung sind in den Zeichnungen dargestellt und in der nachfolgenden Beschreibung näher erläutert.Embodiments of the invention are shown in the drawings and in the description below explained in more detail.
Es zeigen:Show it:
In den Figuren bezeichnen gleiche Bezugszeichen gleiche oder funktionsgleiche Bestandteile.In the figures denote the same Reference numerals same or functionally identical components.
In
In
Ein solches Substrat- bzw. Platinen-freies Fan-out
Package gemäß
In
Gemäß
Vorzugsweise erstreckt sich die thermisch und/oder
elektrisch leitfähige
Einrichtung
Die thermisch und/oder elektrisch
leitfähige Einrichtung
Obwohl die vorliegende Erfindung vorstehend anhand zweier bevorzugter Ausführungsbeispiele beschrieben wurde, ist sie darauf nicht beschränkt, sondern auf vielfältige Weise modifizierbar.Although the present invention described above using two preferred exemplary embodiments it is not limited to this, but in a variety of ways modifiable.
So sind insbesondere andere Gestaltungsformen
als die mit Bezug auf
- 1010
- Halbleiter-ChipSemiconductor chip
- 1111
- Kontakteinrichtung, vorzugsweise Kontakt-PadsContact means, preferably contact pads
- 1212
- Trägereinrichtungsupport means
- 12'12 '
- Schutzeinrichtungguard
- 1313
- Umverdrahtungseinrichtung, z.B. strukturierte Leiterb.rewiring, e.g. structured ladder
- 1414
- Anschlusseinrichtung, z.B. Lotkugeln (solder balls)Connecting device, e.g. Solder balls
- 1515
- elektrisch isolierende Schichtelectrical insulating layer
- 1616
- elektrisch und/oder thermisch leitfähige Einrichtung,electrical and / or thermally conductive Facility,
- z.B. geformte Metallfoliee.g. shaped metal foil
- 1717
- thermisch leitfähiges Klebemittelthermal conductive adhesive
- AA
- peripherer Bereich außerhalb des Chip-Schattensperipheral Area outside the chip shadow
- BB
- Breite des Halbleiterchips bzw. Chip-Schattenwidth of the semiconductor chip or chip shadow
Claims (12)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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DE10319541A DE10319541A1 (en) | 2003-04-30 | 2003-04-30 | Semiconducting device, especially substrate- or circuit board-free re-wiring device on chip or chip scale package, has re-wiring device attached to first chip surface and corresponding bearer surface |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10319541A DE10319541A1 (en) | 2003-04-30 | 2003-04-30 | Semiconducting device, especially substrate- or circuit board-free re-wiring device on chip or chip scale package, has re-wiring device attached to first chip surface and corresponding bearer surface |
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Publication Number | Publication Date |
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DE10319541A1 true DE10319541A1 (en) | 2004-07-08 |
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DE10319541A Withdrawn DE10319541A1 (en) | 2003-04-30 | 2003-04-30 | Semiconducting device, especially substrate- or circuit board-free re-wiring device on chip or chip scale package, has re-wiring device attached to first chip surface and corresponding bearer surface |
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DE (1) | DE10319541A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102013103015B4 (en) | 2012-03-27 | 2022-03-10 | Intel Deutschland Gmbh | Fan-out wafer-level grid package and method of fabricating a fan-out wafer-level grid package |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6048755A (en) * | 1998-11-12 | 2000-04-11 | Micron Technology, Inc. | Method for fabricating BGA package using substrate with patterned solder mask open in die attach area |
EP1093159A1 (en) * | 1999-10-15 | 2001-04-18 | Thomson-Csf | Method for encapsulating electronic components |
US20010035576A1 (en) * | 1992-10-26 | 2001-11-01 | Wachtler Kurt P. | HID land grid array packaged device having electrical and optical interconnects |
US20020050639A1 (en) * | 2000-01-28 | 2002-05-02 | Fujitsu Limited | Semiconductor device having a plurality of semiconductor elements interconnected by a redistribution layer |
US6603209B1 (en) * | 1994-12-29 | 2003-08-05 | Tessera, Inc. | Compliant integrated circuit package |
-
2003
- 2003-04-30 DE DE10319541A patent/DE10319541A1/en not_active Withdrawn
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010035576A1 (en) * | 1992-10-26 | 2001-11-01 | Wachtler Kurt P. | HID land grid array packaged device having electrical and optical interconnects |
US6603209B1 (en) * | 1994-12-29 | 2003-08-05 | Tessera, Inc. | Compliant integrated circuit package |
US6048755A (en) * | 1998-11-12 | 2000-04-11 | Micron Technology, Inc. | Method for fabricating BGA package using substrate with patterned solder mask open in die attach area |
EP1093159A1 (en) * | 1999-10-15 | 2001-04-18 | Thomson-Csf | Method for encapsulating electronic components |
US20020050639A1 (en) * | 2000-01-28 | 2002-05-02 | Fujitsu Limited | Semiconductor device having a plurality of semiconductor elements interconnected by a redistribution layer |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102013103015B4 (en) | 2012-03-27 | 2022-03-10 | Intel Deutschland Gmbh | Fan-out wafer-level grid package and method of fabricating a fan-out wafer-level grid package |
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