DE10328072A1 - Semiconductor component used as a stacked multiple grid structure in transistors comprises a semiconductor substrate with a doped sink as a contact region with an alternating layer sequence of dielectric and electrically conducting layers - Google Patents
Semiconductor component used as a stacked multiple grid structure in transistors comprises a semiconductor substrate with a doped sink as a contact region with an alternating layer sequence of dielectric and electrically conducting layers Download PDFInfo
- Publication number
- DE10328072A1 DE10328072A1 DE2003128072 DE10328072A DE10328072A1 DE 10328072 A1 DE10328072 A1 DE 10328072A1 DE 2003128072 DE2003128072 DE 2003128072 DE 10328072 A DE10328072 A DE 10328072A DE 10328072 A1 DE10328072 A1 DE 10328072A1
- Authority
- DE
- Germany
- Prior art keywords
- contact hole
- electrically conductive
- semiconductor substrate
- dielectric
- conductive layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
Abstract
Description
Logische Gatter können dadurch gebildet werden, dass mehrere Transistoren in Reihe hintereinander geschaltet werden, so dass zwischen den äußersten Source-/Drain-Bereichen eine Mehrzahl von über Gate-Elektroden angesteuerten Kanalbereichen angeordnet ist, die somit in Serie hintereinander geschaltet sind. Es müssen daher alle Transistoren offen sein, um einen Stromfluss von Source nach Drain zu ermöglichen. Die logische Verknüpfung ist daher zwischen einer Mehrzahl von Eingangssignalen gleichzeitig realisiert.logical Gates can be formed by multiple transistors in series one behind the other be switched so that between the outermost source / drain regions a plurality of over Gate electrode driven channel regions is arranged, the thus connected in series in series. It must therefore all transistors should be open to drain current from source to enable. The logical link is therefore between a plurality of input signals simultaneously realized.
Eine derartige Schaltungsanordnung beansprucht einen erheblichen Platzbedarf auf der Oberseite eines Halbleiterchips. Dreidimensionale Anordnungen der Transistoren für eine derartige Schaltungsanordnung in so genannter kubischer oder vertikaler Integration (Sandwich), bei denen die Längsrichtung der Transistoren senkrecht zur Oberseite eines Halbleiterchips verläuft, sind nur durch aufwendige Prozessschritte herstellbar.A Such circuitry requires a considerable amount of space on top of a semiconductor chip. Three-dimensional arrangements the transistors for Such a circuit arrangement in so-called cubic or vertical integration (sandwich), where the longitudinal direction the transistors are perpendicular to the top of a semiconductor chip, are can only be produced by complex process steps.
Seit einiger Zeit werden im Bereich der Halbleitertechnologie Materialstrukturen im Nanometer-Bereich als so genannte Carbon-Nanotubes oder Silizium-Nanowires hergestellt. Mit derartigen Materialstrukturen lassen sich bei geeigneter Anordnung Bauelemente äußerst geringer Dimension herstellen.since For some time, material structures have become in the field of semiconductor technology in the nanometer range as so-called carbon nanotubes or silicon nanowires produced. With such material structures can be in a suitable Arrangement components extremely low Create dimension.
Aufgabe der vorliegenden Erfindung ist es, eine einfach herstellbare Bauelementstruktur als Mehrfach-Gatter anzugeben, die einen möglichst geringen Oberflächenanteil eines Halbleiterchips beansprucht. Außerdem ist ein zugehöriges Herstellungsverfahren anzugeben.task It is the object of the present invention to provide an easily fabricated device structure specify as multiple gates, the lowest possible surface portion a semiconductor chip claimed. In addition, an associated manufacturing process specify.
Diese Aufgabe wird mit dem Halbleiterbauelement mit den Merkmalen des Anspruches 1 bzw. mit dem Verfahren zur Herstellung eines Halbleiterbauelementes mit den Merkmalen des Anspruches 3 gelöst. Ausgestaltungen ergeben sich aus den abhängigen Ansprüchen.These Task is with the semiconductor device with the features of Claim 1 or with the method for producing a semiconductor device solved with the features of claim 3. Embodiments result from the dependent ones Claims.
Bei dem Halbleiterbauelement ist in einem Halbleitersubstrat eine als Kontaktbereich vorgesehene dotierte Wanne ausgebildet, über der sich eine Schichtfolge befindet, die alternierend dielektrische Schichten und elektrisch leitfähige Schichten umfasst. In dieser Schichtfolge befindet sich eine vertikale Kontaktlochfüllung, die bis auf die dotierte Wanne herabreicht und ein elektrisch leitfähiges Material, vorzugsweise ein Material mit Nanotube- oder Si-Nanowire-Struktur, ist, das für die Transistorkanäle vorgesehen ist. Zwischen dieser Kontaktlochfüllung und den elektrisch leitfähigen Schichten ist jeweils eine schmale Zone eines elektrisch isolierenden Materials vorhanden, das vorzugsweise während des Ätzens des Kontaktloches durch eine Oxidation des elektrisch leitfähigen Materiales hergestellt ist. Auf der Oberseite befindet sich eine weitere Schicht aus elektrisch leitfähigem Material, die mit der Kontaktlochfüllung, vorzugsweise durch direkten Kontakt, elektrisch leitend verbunden ist und als oberer Anschlusskontakt vorgesehen ist.at the semiconductor device is in a semiconductor substrate as a Contact area provided doped well formed over the there is a layer sequence, the alternating dielectric layers and electrically conductive Includes layers. In this layer sequence is a vertical Contact hole filling, which extends down to the doped well and an electrically conductive material, preferably a material with nanotube or Si nanowire structure, which is intended for the transistor channels is. Between this contact hole filling and the electrically conductive layers If there is a narrow zone of an electrically insulating material, preferably during the etching of the Contact hole by oxidation of the electrically conductive material is made. On the top is another layer made of electrically conductive Material with the contact hole filling, preferably by direct Contact, electrically connected and as the upper terminal contact is provided.
Die die Kontaktlochfüllung bildenden Nano-Materialien können Carbon-Nanotubes oder Silizium-Nanowires sein. Die Kontaktlochfüllung bildet die Kanalbereiche der Transistoren in vertikaler Richtung bezüglich der Oberseite des Substrates. Über die Kontaktlochfüllung sind Die dotierte Wanne in dem Halbleitersubstrat als unterer Kontaktbereich und die obere elektrisch leitfähige Schicht als oberer Anschlusskontakt sind über die Kanalbereiche der Transistoren in der Kontaktlochfüllung elektrisch miteinander verbunden. Je nach Anordnung beziehungsweise Kontaktierung der jeweiligen Gate-Elektroden, die durch die elektrisch leitfähigen Schichten gebildet werden, mit anderen Gate-Elektroden oder Kontaktanschlüssen las sen sich logische Gatter (zum Beispiel UND, ODER) realisieren. Die elektrisch leitfähigen Schichten können insbesondere Aluminium sein, das angrenzend an die Kontaktlochfüllung bei der Ätzung des Kontaktloches zu Aluminiumoxid (Al2O3) oxidiert wurde. Das Aluminiumoxid bildet die Gate-Oxide.The nano-materials forming the contact hole filling can be carbon nanotubes or silicon nanowires. The contact hole filling forms the channel regions of the transistors in the vertical direction with respect to the top side of the substrate. The doped well in the semiconductor substrate as the lower contact region and the upper electrically conductive layer as the upper contact contact are electrically connected to one another via the channel regions of the transistors in the contact hole filling. Depending on the arrangement or contacting of the respective gate electrodes, which are formed by the electrically conductive layers, with other gate electrodes or contact terminals read sen logic gates (for example, AND, OR) realize. The electrically conductive layers may in particular be aluminum, which has been oxidized adjacent to the contact hole filling during the etching of the contact hole to aluminum oxide (Al 2 O 3 ). The alumina forms the gate oxides.
Es
folgt eine genauere Beschreibung von Beispielen des Halbleiterbauelementes
und des Herstellungsverfahrens anhand der
Die
Die
Die
Die
Die
Die
Die
Die
Die erfindungsgemäße Anordnung ist äußerst platzsparend. Vertikale Anordnungen von Transistoren um jeweilige Kontaktlochfüllungen herum können auf demselben Halbleiterchip mehrfach vorgesehen werden. Dazu werden gleichzeitig mehrere Kontaktlöcher ausgeätzt. Auch die Kontaktlochfüllungen können in mehrere Kontaktlöcher gleichzeitig in demselben Herstellungsschritt eingebracht werden. Es ist so möglich, eine Mehrzahl von Mehrfach-Gattern auf kleinster Fläche unterzubringen.The inventive arrangement is extremely space-saving. Vertical arrangements of transistors around respective contact hole fills around be provided several times on the same semiconductor chip. To do this at the same time several contact holes etched. Also the contact hole fillings can in several contact holes be introduced simultaneously in the same manufacturing step. It is so possible accommodate a plurality of multiple gates in the smallest area.
Das
Halbleiterbauelement gemäß
- 11
- HalbleitersubstratSemiconductor substrate
- 22
- dielektrische Schichtdielectric layer
- 2020
- dielektrische Schichtdielectric layer
- 2121
- dielektrische Schichtdielectric layer
- 2222
- dielektrische Schichtdielectric layer
- 33
- elektrisch leitfähige Schichtelectrical conductive layer
- 3030
- elektrisch leitfähige Schichtelectrical conductive layer
- 3131
- elektrisch leitfähige Schichtelectrical conductive layer
- 44
- Kontaktlochcontact hole
- 55
- Gate-DielektrikumGate dielectric
- 66
- KontaktlochfüllungContact hole filling
- 77
- weitere elektrisch leitfähige SchichtFurther electrically conductive layer
- 88th
- Kanalbereichchannel area
- 99
- Gate-ElektrodeGate electrode
- 1010
- dotierte Wannedoped tub
Claims (7)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE2003128072 DE10328072B4 (en) | 2003-06-23 | 2003-06-23 | Method of fabricating semiconductor devices as stacked multiple gates |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE2003128072 DE10328072B4 (en) | 2003-06-23 | 2003-06-23 | Method of fabricating semiconductor devices as stacked multiple gates |
Publications (2)
Publication Number | Publication Date |
---|---|
DE10328072A1 true DE10328072A1 (en) | 2005-01-20 |
DE10328072B4 DE10328072B4 (en) | 2007-03-15 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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DE2003128072 Expired - Fee Related DE10328072B4 (en) | 2003-06-23 | 2003-06-23 | Method of fabricating semiconductor devices as stacked multiple gates |
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DE (1) | DE10328072B4 (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5612563A (en) * | 1992-03-02 | 1997-03-18 | Motorola Inc. | Vertically stacked vertical transistors used to form vertical logic gate structures |
US6197641B1 (en) * | 1998-08-28 | 2001-03-06 | Lucent Technologies Inc. | Process for fabricating vertical transistors |
US6515325B1 (en) * | 2002-03-06 | 2003-02-04 | Micron Technology, Inc. | Nanotube semiconductor devices and methods for making the same |
-
2003
- 2003-06-23 DE DE2003128072 patent/DE10328072B4/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5612563A (en) * | 1992-03-02 | 1997-03-18 | Motorola Inc. | Vertically stacked vertical transistors used to form vertical logic gate structures |
US6197641B1 (en) * | 1998-08-28 | 2001-03-06 | Lucent Technologies Inc. | Process for fabricating vertical transistors |
US6515325B1 (en) * | 2002-03-06 | 2003-02-04 | Micron Technology, Inc. | Nanotube semiconductor devices and methods for making the same |
Also Published As
Publication number | Publication date |
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DE10328072B4 (en) | 2007-03-15 |
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ON | Later submitted papers | ||
OP8 | Request for examination as to paragraph 44 patent law | ||
8125 | Change of the main classification |
Ipc: H01L 21/8234 AFI20051017BHDE |
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8364 | No opposition during term of opposition | ||
R119 | Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee |