DE10345402A1 - Production of semiconductor structure having recess comprises forming covering layer, and stopping the process after exposing the base region of the covering layer - Google Patents

Production of semiconductor structure having recess comprises forming covering layer, and stopping the process after exposing the base region of the covering layer Download PDF

Info

Publication number
DE10345402A1
DE10345402A1 DE10345402A DE10345402A DE10345402A1 DE 10345402 A1 DE10345402 A1 DE 10345402A1 DE 10345402 A DE10345402 A DE 10345402A DE 10345402 A DE10345402 A DE 10345402A DE 10345402 A1 DE10345402 A1 DE 10345402A1
Authority
DE
Germany
Prior art keywords
covering layer
base region
exposing
stopping
production
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE10345402A
Other languages
German (de)
Other versions
DE10345402B4 (en
Inventor
Daniel Koehler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE10345402A priority Critical patent/DE10345402B4/en
Publication of DE10345402A1 publication Critical patent/DE10345402A1/en
Application granted granted Critical
Publication of DE10345402B4 publication Critical patent/DE10345402B4/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0385—Making a connection between the transistor and the capacitor, e.g. buried strap

Abstract

Production of a semiconductor structure having a recess (2) comprises forming a covering layer (5) on a base region, on a wall region and a peripheral region of the recess in an anisotropic plasma process having an adjustable etching rate and deposition rate so that the base region is more quickly etched than the wall region and the peripheral region, and stopping the process after exposing the base region of the covering layer.
DE10345402A 2003-09-30 2003-09-30 Method for processing a semiconductor structure with a recess Expired - Fee Related DE10345402B4 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE10345402A DE10345402B4 (en) 2003-09-30 2003-09-30 Method for processing a semiconductor structure with a recess

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10345402A DE10345402B4 (en) 2003-09-30 2003-09-30 Method for processing a semiconductor structure with a recess

Publications (2)

Publication Number Publication Date
DE10345402A1 true DE10345402A1 (en) 2005-05-04
DE10345402B4 DE10345402B4 (en) 2005-10-13

Family

ID=34399075

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10345402A Expired - Fee Related DE10345402B4 (en) 2003-09-30 2003-09-30 Method for processing a semiconductor structure with a recess

Country Status (1)

Country Link
DE (1) DE10345402B4 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017024309A1 (en) * 2015-08-06 2017-02-09 Texas Instruments Incorporated Substrate contact etch process

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9082719B2 (en) 2012-10-19 2015-07-14 Infineon Technologies Ag Method for removing a dielectric layer from a bottom of a trench

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4784720A (en) * 1985-05-03 1988-11-15 Texas Instruments Incorporated Trench etch process for a single-wafer RIE dry etch reactor
DE19706682A1 (en) * 1997-02-20 1998-08-27 Bosch Gmbh Robert Anisotropic fluorine-based plasma etching process for silicon
US5843847A (en) * 1996-04-29 1998-12-01 Applied Materials, Inc. Method for etching dielectric layers with high selectivity and low microloading
EP1047122A2 (en) * 1999-04-21 2000-10-25 Alcatel Method of anisotropic etching of substrates
DE19736370C2 (en) * 1997-08-21 2001-12-06 Bosch Gmbh Robert Process for anisotropic etching of silicon
US6362109B1 (en) * 2000-06-02 2002-03-26 Applied Materials, Inc. Oxide/nitride etching having high selectivity to photoresist

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4784720A (en) * 1985-05-03 1988-11-15 Texas Instruments Incorporated Trench etch process for a single-wafer RIE dry etch reactor
US5843847A (en) * 1996-04-29 1998-12-01 Applied Materials, Inc. Method for etching dielectric layers with high selectivity and low microloading
DE19706682A1 (en) * 1997-02-20 1998-08-27 Bosch Gmbh Robert Anisotropic fluorine-based plasma etching process for silicon
DE19736370C2 (en) * 1997-08-21 2001-12-06 Bosch Gmbh Robert Process for anisotropic etching of silicon
EP1047122A2 (en) * 1999-04-21 2000-10-25 Alcatel Method of anisotropic etching of substrates
US6362109B1 (en) * 2000-06-02 2002-03-26 Applied Materials, Inc. Oxide/nitride etching having high selectivity to photoresist

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017024309A1 (en) * 2015-08-06 2017-02-09 Texas Instruments Incorporated Substrate contact etch process
US9793364B2 (en) 2015-08-06 2017-10-17 Texas Instruments Incorporated Substrate contact having substantially straight sidewalls to a top surface of the substrate
CN107851577A (en) * 2015-08-06 2018-03-27 德克萨斯仪器股份有限公司 Substrate contact etch process
CN107851577B (en) * 2015-08-06 2022-05-17 德克萨斯仪器股份有限公司 Substrate contact etching process

Also Published As

Publication number Publication date
DE10345402B4 (en) 2005-10-13

Similar Documents

Publication Publication Date Title
TW200625440A (en) Wafer bevel polymer removal
EP1420438A3 (en) Method and apparatus for etching a deep trench
MY142148A (en) Semiconductor texturing process
WO2004042771A3 (en) Method of etching a silicon-containing dielectric material
EP1291910A4 (en) Wafer chuck, exposure system, and method of manufacturing semiconductor device
TW344858B (en) Highly integrated and reliable DRAM and its manufacture
TW200625468A (en) A method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
TW200501199A (en) Methods of forming semiconductor mesa structures including self-aligned contact layers and related devices
KR950032704A (en) High pressure plasma processing method and apparatus
TW200623211A (en) Method of manufacturing semiconductor device
WO2009022440A1 (en) Ashing apparatus
WO2002065512A3 (en) Process for etching organic low-k materials
TW200643611A (en) Etch with photoresist mask
TW377453B (en) Production of electronic device
TW200509244A (en) A selective etch process for making a semiconductor device having a high-k gate dielectric
TWI654651B (en) Semiconductor substrate etching method
WO2003030238A1 (en) Processing method
EP0814501A3 (en) Method for etching metal silicide with high selectivity to polysilicon
TW200633006A (en) Methods for forming isolation films
TW200703499A (en) Semiconductor device fabrication method
TW200632595A (en) Pattern forming method and semiconductor device manufacturing method
TW200507103A (en) Semiconductor fabrication method for making small features
EP0951963A3 (en) Wafer flattening process, wafer flattening system, and wafer
TW200629542A (en) A method and system for forming a feature in a high-k layer
SG132691A1 (en) Wafer processing method and wafer processing apparatus

Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee