DE10345402B4 - Method for processing a semiconductor structure with a recess - Google Patents

Abstract

Method for processing a semiconductor structure (1, 2a, 2b, 3, 4; 1, GS1, GS2, 7, 8) having a depression (2; 20) with the steps:
(a) providing a continuous cover layer (5; 50) on the bottom portion (5a; 50a), on the wall portion (5b; 50b) and the peripheral portion (5c; 50c) of the recess (2; 20);
(b) processing the capping layer (5; 50) in a plasma process in which at the same time etching of the depression (2; 20) and deposition of sidewall passivation in the depression (2; 20) are achieved, and which has a depth-dependent etching rate and a depth-dependent deposition rate set such that the bottom region (5a; 50a) of the cap layer (5; 50) is etched faster than the wall region (5b; 50b) and the peripheral region (5c; 50c),
wherein the depth-dependent etching rate and the depth-dependent deposition rate are set such that a deposition of a plasma layer (10) occurs in the upper part of the wall region (5b) and in the peripheral region (5c) during processing, and

Description

The The present invention relates to a method for processing a Semiconductor structure with a recess.

From the US patent specification US 4,784,720 For example, a method of processing a semiconductor structure with a recess is known in which a cover layer is provided at the bottom, at the wall and in the peripheral area of the recess. The passivation layer is deposited primarily on the sidewall and the recess, but may also form on the recess bottom. In the peripheral region, the covering layer is formed by a mask. The cover layer in the recess is formed during a plasma process and is further processed in the course of the process, wherein at the same time an anisotropic plasma etching of the recess and a plasma deposition of the passivating cover layer in the depression takes place. During the plasma process, the process parameters for both the etching and the deposition are variable, so z. B. an increased deposition rate in the upper region of the side wall of the recess is achieved. Due to the vertical ion incidence, the bottom of the depression is etched more strongly than the sidewall and as the peripheral region which is masked. Depending on the application, the recess bottom can be exposed by suitable choice of the process parameters or a covering layer can remain there.

3a C illustrate process steps of a method for processing a semiconductor structure with a depression to explain the problem underlying the present invention.

In 3 denotes reference numeral 1 a silicon semiconductor substrate. Provided in the silicon semiconductor substrate 1 is a trench for a trench capacitor. Shown in 3a -C is just the top of the trench. On the trench walls is a capacitor dielectric 2a provided, and in the lower part of the trench a Polsiliziumfüllung located above 2 B , which is to be recognized in the beginning.

On the surrounding surface of the substrate 1 next to the ditch is a hard mask 3 . 4 consisting of a lower pad oxide layer 3 and an upper pad nitride layer 4 which previously served to form the trench.

The above the polysilicon filling 2 B lying upper trench area is referred to below as a recess 2 means that the trench in this area is initially not filled.

About the resulting structure with the depression 2 becomes a cover layer 5 deposited in the form of a silicon oxide layer, which will later serve as a collar insulation layer in the upper trench area. This corresponds to the in 3a shown process state, wherein reference numerals 5a a floor area, reference numerals 5b a wall area and Bezugszei chen 5c a peripheral region of the cover layer 5 designated.

In an ensuing process step, an anisotropic plasma etch then takes place to ultimately remove the bottom region and the underlying polysilicon fill 2 B expose and thus the surface of Polisiliziumschicht 2 B be made available for further process steps in which an electrical contact is provided.

It is in accordance with 3b initially completely removed during etching the top of the cover, wherein a thinned bottom area 5a ' the stakeout layer 5 remains as the etch rate decreases with increasing depth d.

Continuing the etch after removing the top of the cover layer around the thinned bottom area 5a ' the stakeout layer 5 to remove takes place, as in 3c shown an undesirable rounding V of the upper edges of the pad nitride layer 4 the hard mask 3 . 4 , From the cover layer 5 only the wall area remains 5b '' , which is beveled at the top and merges into the rounding V.

The removal or the rounding of the hard mask 3 . 4 as well as the slope or retreat of the upper wall area 5b '' are dependent on the time and selectivity of the plasma etching process.

It Object of the present invention, an improved method for processing a semiconductor structure with a depression create where the unwanted Rounding is avoidable.

According to the invention this Object by the method specified in claim 1 and 6 for processing a semiconductor structure solved with a depression.

The idea underlying the present invention is that in a combined, preferably anisotropic plasma process, which has a depth-dependent etch rate and a depth-dependent deposition rate, such an adjustment can be made that the bottom area of the cover layer is etched faster than the wall area and the periphery area. For certain plasma process parameters, there is some correlation between depth-dependent etch rate and depth-dependent deposition rate, and for others, these two variables can be set completely independently of each other. The latter process parameter settings have the particular advantage that the neutral point at which deposition rate and etch rate are equal can be placed in virtually any depth of well.

In the dependent claims find advantageous developments and improvements of inventive method for processing a semiconductor structure with a recess.

According to a preferred refinement, the depth-dependent etching rate and the depth-dependent deposition are set such that deposition of a plasma layer in the upper part of the wall region (FIG. 5b ) and in the peripheral area and an etching removal takes place in the lower part of the wall area and in the floor area and results in a predetermined depth in the central wall area a vanishing difference of deposition and Ätzabtrag.

According to one Another preferred embodiment, after stopping the processing Removing the plasma layer and anisotropic plasma etching of the Remains of the cover layer to expose the top of the semiconductor structure carried out.

According to one Another preferred development is the top of the semiconductor structure formed by a hard mask and the anisotropic plasma etching of Rest of the cover layer an end point detection is performed indicating the reaching of an uppermost layer of the hardmask.

According to one Another preferred embodiment, the cover layer is a collar insulation layer made of silicon oxide for a trench capacitor provided in the recess.

According to one further preferred development, the deepening widens in Connection to the peripheral area to an extended recess in the semiconductor structure. The depth-dependent etch rate and the depth-dependent deposition rate are set so that when editing a deposition of a Plasma layer in the enlarged recess and its upper side periphery takes place at a predetermined depth of the enlarged recess a vanishing difference between deposition and etching removal results and a Ätzabtrag takes place in the peripheral area, in the wall area and in the floor area; and that after stopping the machining, the wall area and the Peripheral area remain covered by a residue of the cover layer.

According to one Another preferred development, the cover layer is a Seitenwandspacerschicht of silicon oxide on the sides of adjacent gate stacks and on the intermediate substrate surface of a semiconductor memory device.

According to one Another preferred development is the plasma process in one C-F-H or C-F-O plasma, wherein the plasma layer is a polymer layer is.

According to one Another preferred development, the plasma noble gas ions attached.

According to a further preferred development, the plasma process takes place in a C ₄ F ₆ / Ar / O ₂ plasma.

embodiments The invention is illustrated in the drawings and in the following Description closer explained.

It illustrate:

1a -D process steps of a method of processing a semiconductor structure having a recess as a first embodiment of the present invention;

2a . b Process steps of a method of processing a semiconductor structure having a recess as a second embodiment of the present invention; and

3a -C process steps of a method for processing a semiconductor structure with a recess for explaining the underlying problem of the present invention.

In the same reference numerals designate the same or functionally identical Ingredients.

1a -D illustrate process steps of a method of processing a semiconductor structure having a recess as a first embodiment of the present invention.

1a shows for a combined anisotropic plasma process in a C ₄ F ₆ / Ar / O ₂ plasma a depth-dependent approximately linearly decreasing with the depth etch rate ER and a depth-dependent likewise approximately linear but more steeply descending with the deposition rate DR, for in 1b shown semiconductor structure, the already in connection with 3a corresponds explained semiconductor structure.

In this combined anisotropic plasma process in a C ₄ F ₆ / Ar / O ₂ plasma, an independent adjustment of depth dependent etch rate ER and depth dependent deposition rate DR over the process parameters pressure, gas composition, flow rate, and power can be made such that the bottom area 5a the cover layer 5 etched faster than the wall area 5b and the peripheral area 5c , The neutral point at which the deposition rate DR and the etching rate ER are the same, that is also in 1a shown net zero is in this example in a depth d = x of the recess 2 placed.

As in 1c presented, has the processing of in 1b shown semiconductor structure with the in 1a sketched combined anisotropic plasma process the impact that initially the bottom area 5a the cover layer 5 completely removed, the immediately above wall area 5b is hardly etched due to the lower etch rate and the anisotropy and a deposit on the upper part of the wall area 5b and the peripheral region where a polymer layer 10 attaches to the surface. The combined anisotropic plasma process thus leaves a modified sidewall region 5b ' and a modified peripheral area 5c ' the cover layer 5 back from silicon oxide.

Continue with reference to 1d Then there is a step of removing the attached polymer layer 10 in the upper wall area 5b ' or peripheral area 5c ' the cover layer 5 , This can be done for example by an organic solvent or with an oxygen plasma (O ₂ flash).

Subsequently, a conventional anisotropic plasma etching process (without net deposition) is applied to the resulting semiconductor structure to form the top of the semiconductor structure from the capping layer 5 to rid and the top of the pad nitride layer 4 to be released. For this purpose, an end point detection can be used, which ensures very precisely that the unwanted rounding V does not occur. But even without endpoint detection in a time-controlled plasma etching process with a corresponding process window can be with reference to 3a to 3c avoid the described rounding V.

The final process state is in 1d shown where the wall area 5b '' in the lower part of the depression 2 remains almost completely intact and in the upper part of the depression 2 bevelled. This corresponds to the in 3c shown process state with the exception of the lack of rounding V.

2a , b illustrate process steps of a method for processing a semiconductor structure with a recess as a second embodiment of the present invention.

In the second example according to 2a denotes reference numeral 1 a semiconductor substrate with not shown active circuit areas. Applied to the semiconductor substrate 1 are two gate stacks GS1, GS2 in the form of elongated tracks. The gate stacks GS1, GS2 are located on a gate dielectric (not shown). Each consists of a managerial area 1a respectively. 2a polysilicon / tungsten silicide or tungsten / tungsten nitride and a protective cap area 1b respectively. 2 B made of silicon nitride. Embedded are the gate stacks GS1, GS2 in an oxide layer 7 that a broadened depression 200 which has a stepped shape in the recess relating to the plasma process 20 passes.

On the side facing each other is a spacer layer 50 made of silicon oxide with a U-shaped profile on and between the gate stacks GS1, GS2. Here, reference numeral designates 50a a floor area, 50b a wall area and 50c a peripheral region of the spacer layer 50 with reference to the lower narrower recess. Finally, reference numeral designates 8th a silicon nitride liner on the sidewalls of the upper, wider recess 200 ,

On the in 2a structure shown is the in 1a illustrated, combined, anisotropic plasma process with the proviso applied that the neutral point x, where the net NR rate is zero, above the spacer layer 50 in the area of the widened depression 200 located.

This has, as in 2 B represented, with the result that the deposition of the polymer layer 10 ' in the area of broadened depression 200 above the spacer layer 50 takes place and the spacer layer 50 is etched overall with the etch rate increasing toward the bottom. As a result, first, due to the highest etching rate, the bottom area 50a the spacer layer 50 away. In the lower part of the wall area 50 Due to the anisotropy, almost no etching erosion occurs, whereas in the upper part of the wall region 50b and in the periphery 50c to a slight rounding, however, when exposing the substrate surface still from the residues 50b ' . 50c ' the spacer layer 50 are covered.

All materials mentioned in the above examples are chosen purely by way of example and can be chosen as desired with appropriate modification of the plasma method. Importantly, the combined plasma process has adjustable deposition and etch rates, with the deposition rate decreasing with increasing depth takes as the etch rate.

1

Semiconductor substrate

2a

Capacitor dielectric

2 B

Polysilicon filling

3

Pad oxide layer

4

Pad nitride layer

5

covering

5a, 5a '

floor area

5b 5b ', 5b' '

wall area

5c 5c '

O area

DR

deposition rate

HE

etching rate

NO

net rate

d

depth

GS1, GS2

gate stack

1a

senior Area

1b

Cap area

50

spacer

50a

floor area

50b, 50b '

wall area

50c, 50c '

O area

7

oxide

8th

Nitride liner

10 10 '

polymer layer

x

Plain Point

Claims (10)

Method for processing a semiconductor structure ( 1 . 2a . 2 B . 3 . 4 ; 1 , GS1, GS2, 7 . 8th ) with a depression ( 2 ; 20 ) comprising the steps of: (a) providing a continuous cover layer ( 5 ; 50 ) on the floor area ( 5a ; 50a ), on the wall area ( 5b ; 50b ) and the peripheral area ( 5c ; 50c ) of the depression ( 2 ; 20 ); (b) processing the cover layer ( 5 ; 50 ) in a plasma process in which at the same time an etching of the depression ( 2 ; 20 ) and depositing a sidewall passivation in the recess ( 2 ; 20 ), and which has a depth-dependent etching rate and a depth-dependent deposition rate, which are set such that the bottom area ( 5a ; 50a ) of the cover layer ( 5 ; 50 ) is etched faster than the wall area ( 5b ; 50b ) and the peripheral area ( 5c ; 50c ), wherein the depth-dependent etching rate and the depth-dependent deposition rate are set such that during the deposition of a plasma layer ( 10 ) in the upper part of the wall area ( 5b ) and in the periphery ( 5c ) and a Ätzabtrag in the lower part of the wall area ( 5b ) and in the ground area ( 5a ) takes place and at a predetermined depth (x) in the central wall area a vanishing difference of deposition and Ätzabtrag results; and (c) stopping the work after removing the floor area ( 5a ; 50a ) of the cover layer ( 5 ; 50 ). Method according to claim 1, characterized in that that the plasma process according to b) anisotropic is. A method according to claim 2, characterized in that after stopping the processing, the following steps are carried out: removing the plasma layer ( 10 ); and anisotropic plasma etching of a residue ( 5b ' . 5c ' ) of the cover layer ( 5 ) until the top of the semiconductor structure ( 1 . 2a . 2 B . 3 . 4 ). Method according to Claim 3, characterized in that the top side of the semiconductor structure ( 1 . 2a . 2 B . 3 . 4 ) from a hard mask ( 3 . 4 ) and in the anisotropic plasma etching of the remainder ( 5b ' . 5c ' ) of the cover layer ( 5 ) an end point detection is performed, which is the achievement of an uppermost layer ( 4 ) of the hard mask ( 3 . 4 ). Method according to one of the preceding claims, characterized in that the covering layer ( 5 ) a collar insulation layer of silicon oxide for one in the recess ( 2 ) Trench capacitor is provided. Method for processing a semiconductor structure ( 1 . 2a . 2 B . 3 . 4 ; 1 , GS1, GS2, 7 . 8th ) with a depression ( 2 ; 20 ) comprising the steps of: (a) providing a continuous cover layer ( 5 ; 50 ) on the floor area ( 5a ; 50a ), on the wall area ( 5b ; 50b ) and the peripheral area ( 5c ; 50c ) of the depression ( 2 ; 20 ); (b) processing the cover layer ( 5 ; 50 ) in a plasma process in which at the same time an etching of the depression ( 2 ; 20 ) and depositing a sidewall passivation in the recess ( 2 ; 20 ), and which has a depth-dependent etching rate and a depth-dependent deposition rate, which are set such that the bottom area ( 5a ; 50a ) of the cover layer ( 5 ; 50 ) is etched faster than the wall area ( 5b ; 50b ) and the peripheral area ( 5c ; 50c ), (c) stopping the work after removing the bottom area ( 5a ; 50a ) of the cover layer ( 5 ; 50 ), (d) where the depression ( 2 ) following the peripheral area ( 50c ) to an enlarged recess ( 200 ) in the semiconductor structure ( 1 , GS1, GS2, 7 . 8th ) and that the depth-dependent etching rate and the depth-dependent deposition rate are set such that a plasma layer is deposited during processing ( 10 ' ) in the enlarged recess ( 200 ) and its top periphery is located at a predetermined depth (x) of the widened recess (FIG. 200 ) yields a vanishing difference between deposition and etching removal and an etching removal in the peripheral region ( 50c ), in the wall area ( 50b ) and in the ground area ( 50a ) he follows; and that after stopping the processing, the wall area ( 50b ) and the periphery ( 50c ) of egg a remainder ( 50b ' . 50c ' ) of the cover layer ( 5 ; 50 ) remain covered. Method according to claim 6, characterized in that the covering layer ( 50 ) is a sidewall spacer layer of silicon oxide on the sides of adjacent gate stacks (GS1, GS2) and on the intervening substrate surface of a semiconductor memory device. Method according to one of the preceding claims, characterized in that the plasma process takes place in a CFH or CF plasma and the plasma layer ( 10 . 10 ' ) is a polymer layer. Method according to claim 8, characterized in that that noble gas ions are added to the plasma. Method according to one of the preceding claims, characterized in that the plasma process takes place in a C ₄ F ₆ / Ar / O ₂ plasma.