DE112006001266B4 - Parameter measurement of high-speed I / O systems - Google Patents

Abstract

A method of using a phase comparator (121) which is part of a phase tracking circuit (107), wherein the phase tracking circuit (107) is based on a phase-locked loop circuit or on or a delay-locked loop to an input-output circuit (I / O circuit) of a Test objects under test, the method comprising the steps of: receiving (702) a signal (109) at the test object, the signal (109) representing digital data; Extracting (704) a phase signal (23; 123) from the phase comparator, the phase comparator (121) generating the phase signal (123) in response to the received signal (109) so that the phase signal has one or more digital components (E, L) , wherein the one or more digital components indicate whether the phase of an input signal of the phase comparator leads the phase of a comparison signal or whether the phase of the input signal of the phase comparator lags the phase of the comparison signal, and wherein the phase tracking circuit controls the comparison signal based on the phase signal to reduce a phase difference between the comparison signal and the input signal of the phase comparator; ...

Description

background

As electronic devices, typically integrated circuits, become faster, more complex and of a denser design, testing such devices during manufacture to eliminate faulty devices has become more important. Such testing is necessary to ensure that the product using the electronic devices behaves in accordance with the performance specifications thereof. As used in this disclosure, the term manufacturing includes manufacturing the electronic devices themselves and fabricating subassemblies such as, for example, electronic devices. Printed circuit boards, and products using the electronic devices. Notwithstanding their increased performance and capability, the average selling price of electronic devices has steadily declined over the years. This has driven a relentless effort by manufacturers to reduce manufacturing costs. This effort has been very successful in generating a steep decline in device manufacturing costs. However, conventional testing techniques require time, equipment, and human resources, the cost of which has not decreased as steeply as the device manufacturing cost. As a result, the cost of testing has come to represent an increasing fraction of the total manufacturing cost. In addition, in-service testing of products using electronic devices is increasingly being used to ensure that the performance of the product is maintained throughout its service life.

High speed digital input-output systems incorporating input / output (I / O) circuits are critical components of many electronic devices, e.g. B. be used in applications such as telecommunications and information processing. As used in this disclosure, the term I / O circuit is taken to designate a transmitter circuit or a receiver circuit or both. Although I / O circuits transmit or receive signals representing digital data, the behavior of such circuits is essentially that of an analog circuit. This is particularly the case when the data rate at which the I / O circuit is transmitting or receiving increases. Effective testing of high speed I / O circuits is thus increasingly based on determining analog parameters.

The proper operation of an I / O circuit to send or receive signals representing digital data does not depend solely on the operation of the I / O circuitry itself, but in addition on the characteristics of the transmission line or wires and connectors which are connected to the I / O circuit. Thus, parameter behavior measurements of I / O circuits often have phenomena such as. Parasitic capacitance, heat effects, electromagnetic interference, signal reflection and distortion caused by loss.

A current trend is to reduce the cost of testing complex electronic devices by including test circuits on the same chip. However, testing the I / O circuits of complex electronic devices using conventional on-chip testing techniques often requires analog-to-digital (A / D) converters (A / D) or other sensitive analog circuits located on the chip. Such on-chip test circuits are often problematic in that they typically occupy too much chip area and consume too much power. Moreover, it is often difficult and expensive to provide such on-chip test circuits with sufficient speed to enable them to verify the dynamic behavior of the I / O circuits. Incorporating on-chip test circuits that can effectively test I / O circuits adds extra effort and complexity. An I / O circuit test technique occupying comparatively little chip area, having a low power consumption and capable of effectively testing analog behavior parameters is desirable.

The current testing of I / O circuits typically focuses only on transmitter circuits and typically does not test receiver circuits. This is because many receiver circuits do not provide a practical test access for measuring the signals output by the receiver circuit. Consequently, what is additionally necessary is consequently an effective way to test receiver circuits.

The US 5,568,493 A describes an integrated circuit comprising an analog operating circuit having a plurality of nodes for input signals and output signals during normal operation. The integrated circuit further comprises a plurality of scan cells connected to at least the plurality of nodes for containing signals used in selected tests of the analog operating circuitry. In the method of testing a module of an analog circuit that is part of an integrated circuit with other circuit parts, a plurality of module signal terminals are decoupled from respective normal mode terminals and coupled to a plurality of sample cells. Thereafter, at least portions of a test pattern are provided by selected scan cells and test result outputs are detected by selected scan cells.

The US 2003/0210029 A1 describes a coherent clock measurement unit that measures a phase-locked loop (PLL) jitter in a coherent manner. The coherent clock measurement unit includes a main sense circuit that provides a main clock signal of a first clock frequency. A first clock divider circuit receives the main clock signal and provides a reference clock signal at a second clock frequency. The phase-locked loop input of a test object is connected to receive the reference clock signal. A second clock divider circuit receives the main clock signal and generates an arming clock signal at a third clock frequency. A test measurement unit clocked by the arming clock signal receives the signal output at the output of the phase-locked loop, and is clocked at a predetermined interval of the signal at a predetermined time based on the arming clock signal phase-locked loop signal to measure a predetermined interval of the signal at a predetermined time based on the arming clock signal. A detection memory clocked by the arming clock signal stores the output of the test measuring unit for subsequent acquisition and refinement by a processing unit with FFT analysis.

The US Pat. No. 6,421,801 B1 describes a method and apparatus for testing an input data path of an integrated circuit. Dual transmit-and-receive delay-locked loops (DLLs) provide clocks for sending data and receiving data in a test mode. A test mode logic drives a data pattern to an input receiver, wherein the data pattern is clocked by the transmit DLL, and wherein the input receiver is clocked by the receive DLL. The output signal of the input receiver is compared with the data pattern. The transmit DLL is set relative to the receive DLL to measure settling times and hold times of the data pattern driven by the input receiver.

The US 4,774,454 A describes a method for testing and measuring distortions in electrical equipment. For signal processing and signal carrying equipment, a signal generator generates a signal of known phase, amplitude and frequency. The corresponding signal is delivered both to a test object and to a measuring unit. The measuring unit measures the amplitude, frequency and phase rotation of an output of the test object and supplies these measured values to a suppression signal generator. The suppression signal generator generates a suppression signal which is added to the output signal from the test object to suppress the fundamental of the output signal. This suppressed signal is then provided to the measuring unit where it is compared to the original output of the test object to determine distortion factors. For testing signal reproducing apparatus such as compact disc players and video tape recorders, such apparatus generates a series of signals, and a series of corresponding suppression signals are generated by the suppression signal generator. This suppression signal is added to the corresponding original signal and eliminates the rounding on each signal in the series. The suppressed signals are then compared with the associated original signals to determine distortion factors of the signal reproducing apparatus.

The US 6,313,682 B1 describes a circuit for generating shaped pulses for applications such as pin drivers of an automatic tester. The shaped pulse generating circuit uses an active feedback circuit which adds predistortion to the output pulses to compensate for the effects of the transmission system between the pin driver and the device under test. Current pulses are applied to the pin driver output transistors in conjunction with the generation of rising and falling output pulse edges to produce an edge overshoot which decreases as the pulse is transmitted to the device under test. The driver circuit can be integrated with the active feedback circuit for predistortion in a single chip. An additional programming circuit may be used to control the amount of predistortion.

Brief description of the drawings

1 FIG. 12 is a block diagram showing an example of phase tracking from which a phase signal is extracted according to embodiments of the invention. FIG.

2A Fig. 10 is a block diagram showing a first example of a test system according to a first embodiment of the invention.

2 B Fig. 10 is a block diagram showing a second example of a test system according to the first embodiment of the invention.

2C Fig. 10 is a block diagram showing a third example of a test system according to the first embodiment of the invention.

3 Fig. 10 is a block diagram showing an example of a test system according to a second embodiment of the invention.

4 Fig. 10 is a block diagram showing an example of a test system according to a third embodiment of the invention.

5 Fig. 10 is a block diagram showing an example of a test system according to a fourth embodiment of the invention.

6 Fig. 10 is a block diagram showing an example of a test system according to a fifth embodiment of the invention.

7 Fig. 10 is a block diagram showing an example of a test system according to a sixth embodiment of the invention.

8th Fig. 10 is a block diagram showing an example of a test system according to a seventh embodiment of the invention.

9 Fig. 10 is a block diagram showing an example of a test system according to an eighth embodiment of the invention.

10 Fig. 10 is a block diagram showing an example of a test system according to a ninth embodiment of the invention.

11 FIG. 12 is a block diagram of an example of a phase comparator suitable for use with the test object formed by the embodiment of FIG 10 tested test system is tested.

12 FIG. 10 is a flowchart showing an example of the processing performed by the processing circuit of FIG 10 shown system is performed.

13A Fig. 10 is a block diagram showing an example of a test system according to a tenth embodiment of the invention in a mode of operation thereof.

13B is a block diagram showing the test system used in 13A is shown in an equalizer setting mode thereof.

14A Fig. 10 is a flowchart showing an example of a test method according to an embodiment of the invention.

14B FIG. 10 is a flowchart illustrating an exemplary embodiment of block. FIG 702 shows that in 14A is shown.

14C FIG. 10 is a flowchart illustrating an exemplary embodiment of block. FIG 706 shows that in 14A is shown.

14D FIG. 10 is a flowchart illustrating another example embodiment of block. FIG 706 shows that in 14A is shown.

Detailed description

Many types of electronic devices include one or more digital input-output (I / O) circuits. An I / O circuit is a receiver circuit or a transmitter circuit or both. A receiver circuit is a circuit that receives an input signal from a transmission medium. The input signal represents digital data and is typically, but not necessarily, a differential signal. The receiver circuit extracts the digital data from the input signal and provides a digital data signal suitable for local use. A transmitter circuit is a circuit which receives a digital data signal and derives from the digital data signal an output signal suitable for transmission over a transmission medium. The output signal represents the digital data and is typically, but not necessarily, a differential signal.

As the operating speed of the digital I / O circuits increases, the digital I / O circuit has increasingly analogous behavior. This is the result of the characteristics of the I / O circuit itself and, in addition, the result of the effects on the characteristics of the I / O circuit of the transmission medium, a parasitic capacitance, a signal reflection and other phenomena related to the operating environment. For the purposes of this disclosure, a digital I / O circuit having analogous behavior will be referred to as a high speed I / O circuit. High-speed I / O circuits typically operate at data rates of 1 gigabit / second (1 Gb / s) and higher. However, the techniques disclosed in this disclosure may additionally be used to perform precision measurements on I / O circuits operating at data rates below 1 Gb / s.

Embodiments of the invention provide a test system and test method for testing the high speed I / O circuit (s) of electronic devices during manufacture of the electronic devices themselves, e.g. During semiconductor device fabrication and printed circuit board fabrication, and during manufacture of a product or subassembly incorporating the electronic device. In addition, a test system or method according to embodiments of the invention may be used during normal in-service operation of a product incorporating a high-speed I / O circuit to determine whether the I / O circuit continues to comply with the performance specifications of the same. Finally, a test system or method according to embodiments of the invention may be used during the design of an electronic device that includes a high-speed I / O circuit.

As used in this disclosure, the term test object refers to an electronic device that has a high-speed I / O circuit and that is subject to testing using a test method or system in accordance with an embodiment of the invention. The term test object additionally refers to a subassembly, end product or system having such a high speed I / O circuit and which is the subject of testing using a testing method or system in accordance with an embodiment of the invention.

A receiver circuit is typically composed of a differential input circuit, a clock and data recovery (CDR) circuit, and a sampling circuit. The CDR circuit is an example of a phase tracking circuit. The input circuit has a differential input which receives the differential input signal from the transmission medium. The CDR circuit is connected to the output of the differential input circuit and recovers the clock signal from the signal at the output of the differential input circuit. The sampling circuit is also connected to the output of the differential input circuit and additionally receives the clock signal recovered by the CDR circuit. The sampling circuit operates in response to the recovered clock signal and the signal output by the differential input circuit to regenerate the digital data represented by the differential input signal.

A typical phase tracking circuit such. B. a CDR circuit based on a phase-locked loop (PLL) circuit. Phase tracking circuits may alternatively be based on a delay locked loop. A delay locked loop based phase tracking circuit operates similarly to a phase locked loop based phase tracking circuit, and thus, the term phase locked loop as used in this disclosure is taken to cover a delay locked loop as well as a phase locked loop.

1 is a block diagram illustrating an example of a phase locked loop 10 which forms part of a typical PLL-based phase tracking circuit, namely a PLL-based CDR circuit. The PLL based CDR circuit forms part of a typical test object that is capable of being tested by a test method and a test system according to an embodiment of the invention. The PLL 10 is from a phase comparator 21 , a loop filter 25 and a VCO 27 (VCO = voltage-controlled oscillator), which are connected in series formed. An input of the phase comparator 21 is connected to an input signal 12 to receive, the other input is connected to a VCO output signal 14 from the output of the VCO 27 to recieve. In a typical receiver circuit incorporating a CDR circuit, the input signal is 12 the signal output by the above-mentioned differential input circuit (not shown). The phase comparator 21 generates a phase signal 23 , In an embodiment where the PLL 10 a digital PLL is, as in the example shown, has the phase signal 23 two digital components E and L on. The digital component E in a given state, e.g. A logic 1 state, indicates that the phase of the input signal 12 that of the VCO output signal 14 is ahead. The digital component L in a given state, e.g. A logic 1 state, indicates that the phase of the input signal 12 that of the VCO output signal 14 lags. The other states, z. Logic 0 states, the digital components E and L indicate that the input signal 12 in the same phase with the VCO output signal 14 is.

In a conventional PLL-based phase tracking circuit such. B. a CDR circuit becomes the phase signal 23 used exclusively in the PLL. The phase comparator 21 feeds the phase signal 23 only in the loop filter 25 one. The loop filter 25 Filters the phase signal to a VCO control signal 16 and provides the VCO control signal 16 to the control input of the VCO 27 , The VCO control signal 16 controls the frequency of the VCO output signal 14 in a manner that tends to reduce the phase difference between the VCO output signal 14 and input signal 12 to reduce to zero.

According to embodiments of the invention, the phase tracking circuit differs 10 from a conventional phase tracking circuit in that the phase comparator 21 the phase signal 23 to a circuit outside the phase tracking circuit 10 as a phase signal 123 outputs. The receiver circuit, part of which is the phase tracking circuit 10 forms, receives an input signal and the phase comparator 21 gives the phase signal 123 in response to the input signal. The phase signal is sampled to produce bit-level data. Sampling will continue until a sufficient set of bit-level data has been obtained. The data set is then analyzed to determine parameter information relating to the test object's I / O circuit.

In a minimalistic modification of a conventional phase tracking circuit such. B. a CDR circuit tracks are provided, the E and L component outputs of the phase comparator 21 connect to one or more pins on the device housing (not shown) of the electronic device, part of which forms the phase tracking circuit. Additionally or alternatively, the traces may extend to a processing circuit (not shown) that forms part of the electronic device, the portion of which additionally forms the phase tracking circuit. These possibilities are described in more detail below. A more typical modification involves the addition of a buffer circuit (not shown) in the path between the E and L component outputs of the phase comparator 21 and the additional housing pins or processing circuitry. The buffer circuit receives the phase signal components E and L from the phase comparator 21 and supplies buffered phase signal components E and L to the additional package pins or to the processing circuit as the phase signal 123 , The buffer circuit minimizes the effect of additionally outputting the phase signal 123 on the normal operation of the phase tracking circuit 10 ,

In one embodiment, the phase tracking circuit 10 is an analog phase tracking circuit, the phase comparator generates 21 the phase signal 23 as a single analog phase signal representing the phase difference between the input signal 12 and the VCO output 14 displays. In such an embodiment, the phase comparator outputs the analog phase signal 23 in addition to a decision circuit (not shown) that converts the analog phase signal into a digital phase signal 123 converts, which has E and L components, as described above. The decision circuit additionally minimizes the effect of additionally outputting the phase signal to the normal operation of the phase tracking circuit 10 , The decision circuit typically forms part of the on-chip test circuitry of the device under test, part of which is the analog phase tracking circuit 10 forms. In this case, the test object gives the digital phase signal 123 comprising the digital phase signal components E and L generated by the decision circuit. Alternatively, the decision circuit may be external to the test object. In this case, the test object outputs the analog phase signal generated by the phase comparator of the analog phase tracking circuit in addition to the external decision circuit. The phase tracking circuit in the test object can output the analog phase signal either directly or, more typically, via an analog buffer circuit.

As noted above, the I / O circuit with respect to which the test method or system according to embodiments of the invention determines parameter information may include the receiver circuit having the phase comparator that generates the phase signal. Alternatively, the I / O circuit to which the parameter information relates may include any transmitter circuit that provides the signal received by the receiver circuit having the phase comparator that generates the phase signal. In cases where the I / O circuit has a transmitter circuit, the parameter information related to the transmitter circuit may be determined from the phase signal generated by the phase comparator of the receiver circuit which, together with the transmitter circuit, at least one Part of the I / O circuit forms. Alternatively, the transmitter circuit may be tested using the phase signal generated by the phase comparator of another receiver circuit, such as the one shown in FIG. B. those of a receiver circuit, which is external to the test object.

In a first example, the test object's I / O circuit includes the receiver circuit and the signal received by the receiver circuit is generated by a signal generator external to the test object. In this case, the parameter information determined from the phase signal relates to the receiver circuit of the test object. The signal generator is typically external to the device under test.

In a second example, the test object's I / O circuit includes a receiver circuit and a transmitter circuit. The signal received by the test object is a bit sequence received at the input of the transmitter circuit. The output of the transmitter circuit is connected to the input of the receiver circuit. In this case, the parameter information determined from the phase signal extracted from the receiver circuit refers to both the transmitter circuit and the receiver circuit of the test object.

In a third example, the test object's I / O circuit includes a transmitter circuit, and the receiver circuit having the phase comparator that generates the phase signal is external to the test object. Parameter information for the external receiver circuit is known. The signal received by the test object is a bit sequence received at the input of the transmitter circuit. The output of the transmitter circuit is connected to the input of the external receiver circuit. In this case, the parameter information determined from the phase signal extracted from the external receiver circuit refers to a combination of the transmitter circuit of the device under test and the external receiver circuit. Since the parameter information of the external receiver circuit is known, parameter information relating to the transmitter circuit of the test object can be determined.

In a fourth example, the test object's I / O circuit has a receiver circuit and the test object is tested in service. The signal received by the receiver circuit is the in-service signal that the receiver circuit receives and processes in the course of in-service operation thereof. In this case, the parameter information determined from the phase signal extracted from the receiver circuit refers to the receiver circuit itself. No special test signal needs to be supplied to the test object and the test object can continue to operate normally while being tested.

In addition to being used to determine parameter data related to the I / O circuit of a test object, the parameter information generated as described above may additionally be used to estimate the tolerance of a receiver circuit to non-ideal input waveforms, such as z. B. to determine those caused by a non-ideal transmission medium, and a non-ideal dynamic behavior of the transmitter circuit. The parameter information may also be used to determine the tolerance of a transmitter circuit to a non-ideal transmission medium and to a non-ideal dynamic behavior of the receiver circuit. Another use of the parameter information is to determine the characteristics of a Equalizer arranged in front of the receiver circuit to compensate for the signal received at the receiver and having a non-ideal waveform.

2A . 2 B and 2C are a block diagram, the respective examples of a test system 100 according to a first embodiment of the invention. The test system 100 is configured to be a test object 101 to test that an I / O circuit 103 comprising a receiver circuit 105 having. The test system 100 generates parameter information that relates to the receiver circuit 105 Respectively. The receiver circuit 105 has a phase tracking circuit 107 in structure of the phase tracking circuit described above 10 similar. As noted above, the phase tracking circuit is 107 typically as a clock and data recovery (CDR) circuit, although the receiver circuit 105 alternatively, may incorporate another type of phase tracking circuit. The phase tracking circuit 107 has a phase comparator 121 on. The phase comparator 121 differs from a conventional phase comparator in that it also adds the phase signal 123 to a circuit external to the phase tracking circuit 107 is.

The test system 100 additionally has a processing circuit 133 on. The processing circuit 133 has an input connected to the phase signal 123 from the phase comparator 121 to recieve.

The test system 100 delivers a signal 109 to the test object 101 , Each of the examples of the test system 100 that in the 2A . 2 B and 2C are shown additionally has a signal generator 108 on, whose output is connected to the input of the receiver circuit 105 connected is. Thus, in the examples shown, the signal 109 that by the signal generator 108 is generated on the test object 101 specifically, at the input of the receiver circuit 105 , The connection between the signal generator 108 and the input of the receiver circuit 105 is typically through one or more pins of the housing (not shown) of the test object 101 provided. In another example, the signal becomes 109 supplied by a signal source (not shown) connected to the test system 100 is external. In this case, no signal generator 108 in the test system 100 available.

At the in 2A The example shown is the processing circuit 133 external to the test object 101 , The phase signal 123 that through the phase comparator 121 is typically associated with the input of the processing circuitry 133 via one or more of the pins of the housing (not shown) of the test object 101 connected. In the example shown, the housing of the test object 101 a test access gate 137 on that the connection between the phase comparator 121 and the external processing circuit 133 supplies.

In addition to 1 referring receives the receiver circuit 105 in the test object 101 the signal 109 and the phase comparator 121 in the phase tracking circuit 107 generated in the receiver circuit 105 the phase signal 123 in response to the signal 109 , In the test system 100 receives the processing circuit 133 the phase signal 123 from the phase comparator 121 that is part of the phase tracking circuit 107 forms. In the example shown, the phase signal 123 Bit level phase data resulting from the fact that the phase comparator 121 the signal 109 that through the phase tracking circuit 107 is received, with the VCO output signal 14 compares that by the VCO 27 is issued. The phase comparator 121 feeds the phase signal 123 into the processing circuit 133 one. The processing circuit 133 processes the phase signal 123 that from the phase comparator 121 was received to the parameter information 135 to determine, referring to the I / O circuit 103 of the test object 101 Respectively. At the in 2A . 2 B and 2C The examples shown relate to the parameter information 135 the receiver circuit 105 of the test object 101 , At the in 2A The example shown becomes the phase signal 123 off chip into the processing circuitry 133 fed.

In the example of the test system 100 , this in 2 B is shown, is the processing circuit 133 internally in the test object 101 , A signal path containing the phase signal 123 transported extends internally in the test object 101 from the phase comparator 121 to the input of the processing circuit 133 ,

In the example of the test system 100 , this in 2 B is shown, the phase signal 123 internally in the test object 101 from the phase comparator 121 into the processing circuit 133 fed. The processing circuit 133 processes the phase signal 123 that through the phase comparator 121 is generated to parameter information 135 to determine, referring to the I / O circuit 103 of the test object 101 Respectively. The processing circuit 133 gives the parameter information 135 from the test object 101 to a receiver (not shown) external to the test object 101 is. For example, the parameter information 135 to other devices, computers or output components (not shown) that are part of the test system 100 form. Typically, one or more pins provide the housing (not shown) of the device under test 101 the connection between the output of the processing circuit 133 and the off-chip receiver (not shown) of the parameter information 135 , In the example shown, the housing (not shown) of the test object 101 a test access gate 137 on that the connection for the parameter information 135 provides.

In test systems according to embodiments of the invention where the test object includes an I / O circuit that transmits and / or receives at a high data rate, the phase signal represents 123 a huge amount of data, ie at least one bit per clock cycle. At the in 2A As shown, it can be difficult, expensive or both, such a large amount of data with such a high data rate from the test object 101 to the embodiment of the processing circuit 133 to send externally to the test object 101 is. In addition, it may be at the in 2 B shown difficult, expensive or both, such a large amount of data in the embodiment of the processing circuit 133 that internally to the test object 101 is to save and then process.

At the in 2C shown example of the test system 100 is part of the processing circuitry 133 internally to the test object 101 and the rest of the processing circuitry 133 is external to the test object 101 , More specifically, the distributed processing circuit 133 a data reduction circuit 151 and a data analyzer 153 on. The data reduction circuit 151 is internal to the test object 101 and the data analyzer 153 is external to the test object 101 , A signal path containing the phase signal 123 transported extends in the test object 101 from the phase comparator 121 to the input of the data reduction circuit 151 , The data reduction circuit 151 has an output connected to the input of the data analyzer 153 connected is. Typically, one or more of the connector pins form the housing (not shown) of the device under test 101 the connection between the output of the data reduction circuit 151 and the input of the data analyzer 153 ready. In the example shown, the object housing has a test access port 137 on that the connection between the output of the data reduction circuit 151 and the input of the data analyzer 153 provides.

During a test of the test object 101 generates the phase comparator 121 the phase signal 123 and the data reduction circuit 151 applies a data reduction process to the phase signal 123 to a reduced data rate phase signal 155 to create. The reduced data rate phase signal 155 has a substantially lower data rate than the phase signal 123 such that the reduced data rate signal 155 comparatively easily via one or more pins of the housing of the test object 101 to the data analyzer 153 to send. The data analyzer 153 receives the reduced data rate phase signal 155 from the data reduction circuit 151 and processes the reduced data rate phase signal 155 to parameter information 135 over the test object 101 to determine. The data analyzer 153 gives the parameter information 135 out, referring to the I / O circuit 103 Respectively. Additionally or alternatively, the data analyzer provides 153 the parameter information 135 to other devices, computers or output components (not shown) that form part of the test system 100 form. Additionally or alternatively, the data analyzer outputs 153 the parameter information 135 to the test object 101 back.

The data reduction circuit 151 processes the phase signal 123 using a data compression or data filtering process. In addition, the data reduction circuit 151 considerably less complex and uses substantially less storage than the entire processing circuit 133 , Consequently, the data reduction circuit 151 essentially technically feasible in the test object 101 than the entire processing circuit 133 ,

The example of the test system 100 , this in 2C can be used to remotely test the test object 101 perform. In such an application is the data analyzer 153 at a remote location (not shown) away from the test object 101 and a data link (not shown) extends between the data reduction circuit 151 and the data analyzer 153 to the reduced data rate phase signal 155 from the test object 101 to transport to the remote location for analysis. The data link is z. As an Ethernet data link or an Internet-based data link. As described below, in some embodiments of the device under test, the I / O circuit includes a transmitter circuit (not shown) that, by nature, enables the device under test to communicate with a remote location via a data link. Such a test object can be set to a test mode in which the output of the data reduction circuit 151 is connected to the input of the transmitter circuit. The transmitter circuit then sends the reduced Data rate-phase signal 155 that through the data reduction circuit 151 is output for analysis to the remote location. In another example, a product or product module whose part is the test object 101 forms a transmitter circuit (not shown) capable of communicating over such communication link. In yet another example, the communication capability is provided by a transmitter circuit (not shown) associated with the product or product module that is the test object 101 integrated, external.

Remote testing of the type just described is typically used to test in-service the test object 101 perform. In this case, the information signal supplied to the test object 101 under service conditions, the signal 109 , Additionally or alternatively, one or more special test signals may be applied to the test object 101 be sent to the signal 109 to deliver. As another alternative, the test object 101 be able to be set to a loopback test mode where the output of a transmitter (not shown) that additionally forms part of the test object is used to signal 109 to deliver.

This in 2 B shown example of the test system 100 can also be used to remotely test the test object 101 perform. In such an application, a data link (not shown) is connected to the parameter information 135 to be received by the processing circuit 133 be generated. The data link is z. As an Ethernet data link or an Internet-based data link. The bandwidth of such a link may be less than that used to perform a remote test using the in-line test 2C to perform example shown. A transmitter circuit (not shown) that forms part of the test object or associated with the test object may be used to send the parameter information to the remote location in a manner similar to that discussed above with respect to transmitting the reduced one -Datenrate-phase signal 155 is described to a remote location.

Not all signal generators acting as signal generators 108 are capable of practically generating waveforms representing the full range of waveforms to which the receiver circuitry 105 emulate in an in-service operation, emulate exactly. Such waveforms are more conveniently generated by a transmitter circuit in response to a bit sequence. 3 is a block diagram illustrating an example of a test system 170 according to a second embodiment of the invention, in which the system additionally comprises a transmitter circuit which receives the signal 109 generated by the test object 101 Will be received. In this embodiment, the parameter information relates to the receiver circuit 105 that is at least part of the I / O circuit 103 of the test object 101 forms.

In the example of the test system shown 170 is the processing circuit 133 external to the test object 101 as stated above with reference to 2A is described. The processing circuit 133 can alternatively internally to the test object 101 be as above with reference to

2 B or part of the processing circuitry 133 can internally to the test object 101 and the rest of the processing circuitry 133 can be external to the test object 101 be as above with reference to 2C is described.

In addition to the processing circuitry 133 assigns the test system 170 a transmitter circuit 115 and a bit sequence generator 178 on. The output of the bit sequence generator 178 is with the input of the transmitter circuit 115 connected and the output of the transmitter circuit 115 is with the entrance of the test object 101 connected. The transmitter circuit 115 delivers the signal 109 to the input of the receiver circuit 105 of the test object 101 in response to a bit sequence generated by the bit sequence generator 178 is produced.

The parameter information 135 passing through the processing circuit 133 are generated, refer to the combination of the transmitter circuit 115 and the receiver circuit 105 , However, the desired parameter information related to the receiver circuit 105 from the parameter information 135 to be obtained. Regarding some types of parameter information, the transmitter circuit carries 115 slightly to the parameter information related to the combination, regardless of the behavior of the transmitter circuit 115 , With respect to other types of parameter information, the transmitter circuit 115 manufactured and / or adjusted such that it contributes slightly to the parameter information relating to the combination. Consequently, the parameter information can 135 relating to the combination, with respect to these types of parameter information than to the receiver circuit 105 to be considered alone. Concerning still other types of parameter information, the contribution of the transmitter circuit 115 to the parameter information 135 , the to be characterized on the combination. The parameter information 135 that relate to the combination can then be used for the contribution of the transmitter circuit 115 be corrected to determine the parameter information that relates to the receiver circuit 105 Respectively. In one example, the contribution is the transmitter circuit 115 to the parameter information 135 is characterized using a technique similar to that described below with reference to 5 is described.

Not all signal generators acting as signal generators 108 are capable of practically generating waveforms that accurately emulate the degradation of waveforms resulting from non-perfect transmitter circuits and non-perfect broadcast systems. 4 is a block diagram illustrating an example of a test system 180 according to a third embodiment of the invention, in which the system comprises a loading circuit which lies between the signal generator and the input of the test object. In this embodiment, the parameter information relates to the receiver circuit 105 that is at least part of the test object's I / O circuit 101 forms.

In the example of the test system shown 170 is the processing circuit 133 external to the test object 101 as it is referring to 2A is described. The processing circuit 133 can alternatively internally to the test object 101 be as referring to 2 B or part of the processing circuitry 133 can internally to the test object 101 and the rest of the processing circuitry 133 can be external to the test object 101 be as above with reference to 2C is described.

At the in 4 shown example of the test system 180 assigns the test system 180 in addition to the signal generator 108 and the processing circuit 133 a load circuit 182 on. The load circuit 182 is external to the test object 101 and lies between the output of the signal generator 108 and the entrance of the test object 101 , The load circuit 182 sets certain characteristics of the input signal 113 that by the signal generator 108 is generated, down to the signal 109 with properties that produce the ability of the receiver circuit 105 test, as by the parameter information 135 is displayed to successfully receive a non-ideal signal. In one example, the signal causes 109 that through the load circuit 182 is generated, a Nachführungsratenbegrenzung in the receiver circuit 105 ,

A load circuit, the load circuit 182 may be similar to the above with reference to 3 described example of the test system 170 between the output of the transmitter circuit 115 and the entrance of the test object 101 lie.

5 is a block diagram illustrating an example of a test system 200 according to a fourth embodiment of the invention. The test system 200 is configured to be a test object 201 to test that an I / O circuit 203 comprising a transmitter circuit 215 having. The parameter information provided by the test system 200 are generated, refer to the transmitter circuit 215 ,

The test system 200 has a phase tracking circuit 207 , a high-impedance buffer amplifier 229 and a processing circuit 233 on, all external to the test object 201 are. The phase tracking circuit 207 has a phase comparator 221 on. The high-impedance buffer circuit 229 couples the output signal 219 that by the transmitter circuit 215 is output, with the input of the phase tracking circuit 207 while adding a slight extra load to the output of the transmitter circuit 215 is imposed. In one embodiment, the input of the buffer amplifier is located 229 near the output of the transmitter circuit 215 to any reduction of the output signal 219 by a broadcast from the output of the transmitter circuit 215 to the input of the buffer amplifier 229 to minimize. However, in embodiments where there is no other load on the output of the transmitter circuit 215 is applied, the buffer circuit 229 be left out. The phase tracking circuit 207 , the phase comparator 221 and the processing circuit 233 are in structure and operation of the phase tracking circuit 107 , the phase comparator 121 or the processing circuit 133 Similar to the ones described above.

The test system 200 delivers a signal 209 to the test object 201 , The example of the test system shown 200 additionally has a bit sequence generator 208 on, whose output is connected to the input of the transmitter circuit 215 connected is. Thus, in the example shown, the signal 209 generated by the bit sequence generator 208 is generated on the test object 201 more specifically, at the input of the transmitter circuit 215 , The connection between the bit sequence generator 208 and the input of the transmitter circuit 215 is typically through one or more pins of the housing (not shown) of the test object 201 provided. In another example, the signal becomes 209 through a signal source (not shown) external to the test system 200 is. In this case, no bit sequence generator is required 208 in the test system 200 available.

To the test object 201 to test, the signal becomes 209 to the input of the transmitter circuit 215 delivered. In response to the signal 209 generates the transmitter circuit 215 a transmitter output 219 at the input of the phase tracking circuit 207 via the high-impedance buffer amplifier 229 Will be received. In the phase tracking circuit 207 receives the phase comparator 221 the transmitter output signal 219 and generates the phase signal in response thereto 223 in a manner similar to that described above. The phase tracking circuit 207 feeds the phase signal 223 into the processing circuit 233 one. The processing circuit 233 processes the phase signal 223 that through the phase tracking circuit 207 is generated to parameter information 235 to determine, referring to the I / O circuit 203 of the test object 201 Respectively.

In the example shown, the parameter information relates 235 on the combination of the transmitter circuit 215 and the phase tracking circuit 207 , However, the desired parameter information related to the transmitter circuit 215 alone, from the parameter information 235 to be obtained. Regarding some types of parameter information, the phase tracking circuit carries 207 slightly to the parameter information related to the combination, regardless of the behavior of the phase tracking circuit 207 , With regard to other types of parameter information, the phase tracking circuit may 207 manufactured and / or adjusted such that it contributes slightly to the parameter information relating to the combination. Consequently, the parameter information can 235 relating to the combination, with respect to these types of parameter information, than to the transmitter circuit 215 to be considered alone. Concerning still other types of parameter information, the contribution of the phase tracking circuit may be 207 to the parameter information 235 that are related to the combination. The parameter information 235 that relate to the combination can then be used for the contribution of the phase tracking circuit 207 be corrected to determine the parameter information pertaining to the transmitter circuit 215 relate alone. In one example, the contribution is the phase tracking circuit 207 to the parameter information 235 is characterized using a technique similar to that described above with reference to FIG 2A is described. In some embodiments of a test system suitable for testing a test object whose I / O circuit has a transmitter circuit, physical constraints require that the test object be at a substantial distance from the phase tracking circuit. 6 is a block diagram illustrating an example of a test system 250 according to a fifth embodiment of the invention, wherein the phase tracking circuit is located at a substantial distance from the test object. The test system additionally has a receiver circuit 205 on whose part the phase tracking circuit 207 forms. The output of the transmitter circuit 215 is connected to the input of the receiver circuit 205 through a broadcast medium 239 coupled by a substantial length. The test system 250 additionally has an equalizer circuit 241 on that between the end of the transmitter medium 239 that of the test object 201 is removed, and the input of the receiver circuit 205 lies. The equalizer 241 is configured to reduce the output signal 219 to be corrected by sending the output signal through the transmission medium 219 is effected. For example, the equalizer 241 be configured to remove a jitter by sending the output signal 219 via a broadcast medium 239 is effected. Removing such a jitter prevents the jitter from the waveform of the output signal 219 as by the phase tracking circuit 207 receive, degrades. Equalizers and their setting are described below with reference to FIG 10 - 12 described in more detail. Examples of a test system according to embodiments of the invention configured to be a test object 301 to test that an I / O circuit 303 comprising a receiver circuit 105 and a transmitter circuit 215 will be next with reference to 7 . 8th and 9 described. In the examples described, the processing circuitry is external to the test object. Alternatively, the processing circuitry may be internal to the test object as described above with reference to FIG 2 B is described. As a further alternative, a portion of the processing circuitry may be internal to the test object and the remainder of the processing circuitry may be external to the test object, as described above with respect to FIG 2C is described.

7 is a block diagram illustrating an example of a test system 300 according to a sixth embodiment of the invention. The test system 300 generates parameter information that relates to the combination of the receiver circuit 105 and the transmitter circuit 215 the I / O circuit 303 of the test object 301 Respectively. The parameter information that relates to the receiver circuit 105 alone and the transmitter circuit 215 can be derived from the parameter information relating to the combination alone.

The test system 300 has a loopback signal path 359 on, extending from the output of the transmitter circuit 215 to the input of the receiver circuit 105 extends. In the example shown, the loopback signal path is 359 external to the test object 301 : The loopback signal path 359 can alternatively internally to the test object 301 be. The test system 300 additionally has a processing circuit 133 on, as described above, the external to the test object 301 is.

The test system 300 delivers a signal 209 to the test object 301 , The example of the test system shown 300 additionally has a bit sequence generator 208 on, whose output is connected to the input of the transmitter circuit 215 connected is. Thus, in the example shown, the signal 209 generated by the bit sequence generator 208 is generated on the test object 301 more specifically, at the input of the transmitter circuit 215 , The connection between the bit sequence generator 208 and the input of the transmitter circuit 215 is typically through one or more pins of the housing (not shown) of the test object 301 provided. In another example, the signal becomes 209 supplied by a signal source (not shown) external to the test system 300 is. In this case, no bit sequence generator is required 208 in the test system 300 available.

In the test system 300 receives the receiver circuit 105 the signal 109 from the loopback signal path 359 , The test system 300 In addition, a signal generator (not shown), the signal generator 108 referring to the above with reference to 2A , and having a selector (not shown), the inputs connected to the output of the signal generator and the loopback signal path 359 are connected, and an output that receives the signal 109 to the receiver circuit 105 supplies, has.

The test system 300 tests the test object 301 as follows: the signal 209 is applied to the input of the transmitter circuit 215 created. In response to the signal 209 generates the transmitter circuit 215 a transmitter output 219 , The output signal 219 is connected to the input of the receiver circuit 105 through the loopback signal path 359 coupled to the signal 109 to deliver. At the receiver circuit 105 generates the phase comparator 121 the phase signal 123 in response to the signal 109 and gives the phase signal to the processing circuit 133 out. The processing circuit 133 processes the phase signal 123 that through the phase comparator 121 in the phase tracking loop 107 is generated to parameter information 135 to determine. The parameter information 135 refer to the I / O circuit 303 , ie a combination of the receiver circuit 105 and the transmitter circuit 215 ,

The parameter information 135 can be analyzed to determine parameter information pertaining to the receiver circuit 105 solely refer to the transmitter circuit 215 alone, as stated above with reference to 3 and 5 is described. To support this, additional parameter information can be added to the receiver circuit 105 by replacing a signal generator similar to that described above with reference to FIG 2A described signal generator 108 is similar to the loopback signal path 359 be received to the signal 109 to the receiver circuit 105 to deliver. The parameter information that relates to the receiver circuit 105 are then derived from the phase signal passing through the phase comparator 121 in response to the signal 109 is output by the signal generator 108 is produced. The parameter information that relates to the receiver circuit 105 can then be used to correct the parameter information related to the combination to determine the parameter information related to the transmitter circuit 215 relate alone. As noted above, some types of parameter information related to the combination refer to the transmitter circuit alone, regardless of the behavior of the receiver circuit.

8th is a block diagram illustrating an example of a test system 350 according to a seventh embodiment of the invention, which is configured to the test object 301 to test. In addition to the loopback signal path described above 359 which is different from the output of the transmitter circuit 215 to the input of the receiver circuit 105 extends, assigns the test system 350 an external phase tracking circuit 207 and a high impedance buffer circuit 229 with reference to above 5 described, and a processing circuit 333 on, all external to the test object 301 are. The high-impedance buffer circuit 229 couples the output signal 219 that by the transmitter circuit 215 is output with the input of the external phase tracking circuit 207 while adding a slight extra load to the output of the transmitter circuit 215 is imposed.

The processing circuit 333 is similar to the processing circuit 133 referring to above 2A but differs in that it has two inputs and a control input (not shown). The state of a control signal (not shown) connected to the control input is created, determines which of the inputs is activated. One of the inputs of the processing circuit 333 is connected to the phase signal 123 from the phase comparator 121 the phase tracking circuit 107 to receive that part of the test object 301 forms. The other of the inputs of the processing circuit 333 is connected to the phase signal 223 from the phase comparator 221 the external phase tracking circuit 207 to recieve.

The test system 350 delivers the signal 209 to the test object 301 , The example of the test system shown 350 additionally has a bit sequence generator 208 on, whose output is connected to the input of the transmitter circuit 215 connected is. Thus, in the example shown, the signal 209 generated by the bit sequence generator on the test object 301 more specifically, at the input of the transmitter circuit 215 , The connection between the bit sequence generator 208 and the input of the transmitter circuit 215 is typically through one or more pins of the housing (not shown) of the test object 301 provided. In another example, the signal becomes 209 supplied by a signal source (not shown) external to the test system 300 is. In this case, no bit sequence generator is required 208 in the test system 300 available.

In the test system 350 receives the receiver circuit 105 the signal 109 from the loopback signal path 359 , The test system 350 In addition, a signal generator (not shown), the signal generator 108 similar to that above with reference to 2A and a selector (not shown), the inputs connected to the output of the signal generator and the loopback signal path 359 are connected, and an output that receives the signal 109 to the receiver circuit 105 supplies, has.

The test system 350 tests the test object 301 as follows: the signal 209 is applied to the input of the transmitter circuit 215 created. In response to the signal 209 generates the transmitter circuit 215 the transmitter output signal 219 , The output signal 219 is to the input of the external phase tracking circuit 207 through a high-impedance buffer circuit 229 coupled. In the external phase tracking circuit 207 generates the phase comparator 221 the phase signal 223 in response to the output signal 219 , The processing circuit 333 is set to activate the input thereof, which is connected to the phase signal 223 to recieve. The processing circuit 333 processes the phase signal 223 that through the phase comparator 221 in the external phase tracking circuit 207 is generated to parameter information 135 to determine, referring to the combination of the transmitter circuit 215 of the test object 301 and the external phase tracking circuit 207 Respectively. The parameter information is the transmitter circuit 215 can concern alone from the parameter information 135 be extracted as it is with reference to above 5 is described.

The state of the control signal (not shown) applied to the processing circuit 333 is delivered, is changed to the input of the processing circuit 333 to activate, which is connected to the phase signal 121 to receive that through the phase comparator 121 in the receiver circuit 105 in response to the signal 109 is produced. The processing circuit 133 processes the phase signal 123 that through the phase comparator 121 is generated to the parameter information 135 to determine, referring to the I / O circuit 303 of the test object 301 Respectively. In the example shown, the parameter information relates 135 on the combination of the receiver circuit 105 and the transmitter circuit 215 , The parameter information that relates to the receiver circuit 105 can relate alone, from the parameter information 135 be extracted as it is with reference to above 3 is described. The parameter information that relates to the transmitter circuit 215 alone, obtained as just described, may be used in the process of extracting the parameter information relating to the receiver circuit 105 relate alone.

In some cases, the transmitter circuit generates 215 Symbol pattern representing a typical signal generator belonging to the signal generator 108 resembles, can not deliver, but which are needed to the receiver circuit 105 under load conditions to test. 9 is a block diagram illustrating an example of a test system 400 according to an eighth embodiment of the invention. The test system 400 is configured to the test object 301 to test. More specifically, the test system tests 400 the receiver circuit 105 the I / O circuit 303 , optionally under load conditions, using a symbol pattern generated by the transmitter circuit 215 the I / O circuit is generated.

The test system 400 , this in 9 is based on the test system 350 referring to the above 8th and corresponding elements are indicated using the same reference numerals. The test system 400 additionally has the load circuit 182 on. The input of the load circuit 182 is with the recovered data output of the external Phase tracking circuit 207 connected so that the load circuit 182 a clean input signal 113 receives that from the output signal 219 the transmitter circuit 215 by the external phase tracking circuit 207 is derived. The output of the load circuit 182 is connected to the input of the receiver circuit 105 over a short, high-quality signal path 439 connected to the signal 109 to the test object 301 to deliver.

During a test of the test object 301 generates the transmitter circuit 215 the output signal 219 in response to the signal 209 by a test programmer 208 is produced. The external phase tracking circuit 207 performs a clock and data recovery operation on the output signal 219 by. The clock and data recovery operation removes any errors in the quality of the output signal 219 and presents a clean input signal 113 to the input of the load circuit 182 , Consequently, all waveform defects are in the signal 109 those who intentionally go through the load circuit 182 be introduced.

10 is a block diagram showing a test system 500 according to a ninth embodiment of the invention. The test system 500 is configured to be a test object 501 to test that an I / O circuit 503 comprising a receiver circuit 105 and a variable equalizer 563 having. The test system 500 sets the variable equalizer 563 in response to the parameter information input from the phase signal 123 are derived by the receiver circuit 105 is output to compensate for errors in a signal present at the input of the receiver circuit 105 in the test object 501 Will be received. In the example shown, the I / O circuit 503 of the test object 501 additionally the transmitter circuit 215 on. In other examples, the I / O circuit 503 only a receiver circuit.

At the test object 501 is the variable equalizer 563 between the input pins of the housing (not shown) of the device under test 501 and the input of the receiver circuit 105 connected in series. The input pins are the pins of the case that are in an in-service operation of the test object 501 receive an input signal and that when the test object 501 is tested, the signal 109 receive. In an in-service operation of the test object 501 equalizer equalizes 563 the signal that is present at the input pins of the test object 501 is received, and passes an equalized input signal 567 to the input of the receiver circuit 105 ,

At the in 10 example shown has the test system 500 in addition a broadcast medium 559 which is external to the test object 501 from the output of the transmitter circuit 215 to the input of the equalizer 563 extends. If the test object 501 is tested, the equalizer receives 563 the signal 109 from the output of the transmitter circuit 215 over the broadcast medium 559 , The equalizer 563 equalizes the signal 109 and passes an equalized signal 567 to the input of the receiver circuit 105 , The length and signal transmission quality of the broadcast medium 559 are such as to enable the broadcast medium 559 emulates a typical or worst case broadcast medium that provides an input to the device under test during in-service operation 501 supplies. Alternatively, the output of the transmitter circuit 215 and the input of the equalizer 563 be linked by a load circuit, the load circuit described above 182 ( 9 ) is similar. The characteristics of the load circuit are set to cause the signal 109 emulates a typical or worst case input signal through the test object 501 during an in-service operation.

Alternatively, the signal 109 supplied by a signal source (not shown) connected to the test system 500 is external. For example, the test system 500 used to make the variable equalizer 563 during an in-service operation of the test object 501 adjust. In this case, the broadcast medium becomes 559 left out and the signal 109 is an in-service input signal passing through the test object 501 during an in-service operation is received by the transmission medium (not shown) connected to the input pins of the device under test 501 connected is.

The test system 500 additionally has an equalizer control 565 on, which has an input connected to the output of the processing circuit 133 is connected, and an output connected to the control input of the equalizer 563 is connected has. The equalizer control 565 receives the parameter information 135 passing through the processing circuit 133 and provides an equalization control signal 568 to the equalizer 563 ,

In one example, the equalizer is similar 563 and the equalizer control 565 in structure those by Seet et al. in the U.S. Patent No. 6,760,551 B2 are described. The parameter information 135 supply the input through the equalizer control 565 is needed to get the equalization control signal 568 to generate the properties of the equalizer 563 is defined such that the equalizer causes adverse effects of the broadcast medium 559 on the signal 109 picks up and thereby that equalized signal 567 optimized.

At the in 10 The example shown is the processing circuit 133 and the equalizer control 565 internally to the test object 501 , Alternatively, the processing circuit 133 external to the test object 501 be as above with reference to 2A or part of the processing circuitry 133 can internally to the test object 501 and the rest of the processing circuitry 133 can be external to the test object 501 be as above with reference to 2C is described. The equalizer control 565 may alternatively be external to the test object 501 be. In another alternative form the equalizer control 565 and the processing circuit 133 at least a part of an operating circuit, during an in-service operation of the test object 501 with the test object 501 connected is.

In embodiments in which the processing circuit 133 or the equalizer control 565 or both externally to the test object 501 are, assigns the test object 501 additionally a memory circuit (not shown) which stores a parameter indicating the setting of the equalizer 563 displays. This allows the equalizer 563 continues to provide the appropriate equalization when the test object 501 is placed in the service. The memory circuit can, for. B. part of the equalizer 563 be. In this case, the stored parameter is the value of the equalizer control signal 568 that through the equalizer 563 is received when the equalization process described below is completed. In another example, the memory circuit is part of the equalizer control 565 and the parameter stored is the value of the parameter information 135 by the equalizer control 565 are received when the equalization process described below is completed.

11 is a schematic drawing showing an example of a phase comparator 521 shows that as the phase comparator 121 in the phase tracking circuit 107 the receiver circuit 105 of the test object 501 can be used. The phase comparator 521 generates an embodiment 523 of the phase signal 123 from which phase information necessary for controlling the variable equalizer 563 are suitable, can be obtained easily. In this example, the phase tracking circuit is 107 a clock and data recovery circuit (CDR circuit) which receives a clock signal CLOCK in response to transitions in the equalized input signal 567 generated by the equalizer 563 is issued. The receiver circuit 105 derives from the signal 567 an input signal INPUT, which is in the phase comparator 521 is entered.

The phase comparator 521 is made of D type flip flops 571 . 572 . 573 and 574 , a latch 575 , an inverter 576 and two-input Exclusive-Or-gates (XOR gates; XOR = exclusive OR) 577 . 578 . 579 . 580 and 581 composed. The clock signal CLOCK, through the phase tracking circuit 107 is generated with the input of the inverter 576 , the clock input of the flip-flop 574 and the ENABLE input of the latch 575 connected. The output of the inverter 576 is with the clock inputs of the flip-flops 571 . 572 and 573 connected. Thus, the flip-flops receive 571 - 573 an inverted version of the clock signal CLOCK.

The input signal INPUT is connected to the D input of the flip-flop 571 and the D input of the flip-flop 574 connected. The D input of the flip-flop 572 is with the Q output of the flip-flop 571 connected, the D input of the flip-flop 573 is with the Q output of the flip-flop 572 connected and the D input of the latch 575 is with the Q output of the flip-flop 574 connected. The Q outputs of the flip-flops 571 . 572 . 573 and the latch 575 provide intermediate signals A, B, Z and T, respectively. The state of the intermediate signal T represents the state of the input signal INPUT at the present transition of the clock signal CLOCK. The states of the intermediate signals A, B and Z represent the states of the input signal INPUT at the opposite direction transitions of the clock signal CLOCK half clock period later, half clock period early and one and a half clock periods earlier than the current transition of the clock signal CLOCK, respectively.

The Q output of the flip-flop 571 (Intermediate signal A) is connected to one input of each of the XOR gates 577 and 580 connected. The Q output of the flip-flop 572 (Intermediate signal B) is connected to an input of the XOR gate 578 connected. The Q output of the flip-flop 573 (Intermediate signal Z) is connected to the other input of the XOR gate 577 and with an input of the XOR gate 579 connected. The Q output of the latch 575 (Intermediate signal T) is with the other input of each of the XOR gates 578 . 579 and 580 connected. The output of the XOR gate 577 provides a phase signal component L and is in addition to an input of the XOR gate 581 connected. The output of the XOR gate 578 is with the other input of the XOR gate 581 connected. The output of the XOR gate 581 provides a phase signal component ZATB. The output of the XOR gate 579 provides a phase signal component ZT and the output of the XOR gate 580 provides a phase signal component E. The phase signal components E and L indicate whether the current transition of the clock signal CLOCK is early (E) or late (L) relative to the current transition of the input signal INPUT. The phase signal component ZATB is the exclusive-OR of the intermediate signals Z, A, T and B. The phase signal component ZT is the exclusive-OR of the intermediate signals Z and T.

When the phase signal components ZT and ZATB are in opposite states, ie when ZT ⊕ ZATB is true, where ⊕ XOR, the state of the phase signal component ZT or the state of the phase signal component ZATB indicates whether the input signal INPUT is under- or over-equalized. When the phase signals ZATB and ZT are in opposite states, the states of the phase signal components ZATB and ZT together encode PULSE events (sequences of 0, 1, 0 or 1, 0, 1 in the signal INPUT) and RUN events (sequences of 0 , 0, 0 or 1, 1, 1 in the signal INPUT) and indicate in common whether the equalizer 563 provides too much or too little equalization. The phase signal components ZT and ZATB, which are in opposite states, ie ZT ⊕ ZATB is true, indicate the presence of a transition in the input signal INPUT. In addition, the state of the phase signal component ZATB, which is true for more than half of the transitions, indicates that the input signal INPUT is under-equalized. The state of the phase signal component ZATB true for less than one-half of the transitions indicates that the input signal INPUT is over-equalized. The state of the phase signal component ZATB true for half of the transitions indicates that the input signal INPUT is optimally equalized.

If the state of the phase signal component ZATB is within a defined tolerance for half of the transitions, this indicates that the input signal INPUT is acceptably equalized. In contrast, if the state of the phase signal component ZT is valid for more than one half of the transitions, this indicates that the input signal INPUT is over-equalized. If the state of the phase signal component ZT is valid for less than half of the transitions, this indicates that the input signal INPUT is under-equalized. If the state of the phase signal component ZT is valid for half of the transitions, this means that the input signal INPUT is optimally equalized. If the state of the phase signal component ZT is valid for half of the transitions within a defined tolerance, this indicates that the input signal INPUT is acceptably equalized.

At an in 10 shown example of a test system 500 subtracts a processing circuit 133 the phase signal components ZATB and ZT arithmetically to generate a three-state signal having three possible states (-1, 0 and +1). An equalizer control 565 integrate this with a reference voltage of zero and scales and compares the same adequately with the same, around an equalizer control signal 568 provide. In this example, the equalization control loop is operative to null the integrated three-state signal.

12 FIG. 10 is a flow chart showing the flow through another example of a processing circuit 133 in the test system 500 performed processing shows. An execution starts at block 585 , blocks 586 and 587 are performed during a measurement period. In block 586 a count is made of the total number of transitions of the input signal INPUT occurring during the measurement period. Each transition is indicated by the phase signal components ZATB and ZT being in opposite states (ZT ⊕ ZATB == true). In block 587 For example, a count of the number of transitions of the input signal INPUT taking place during the measurement period when the phase signal component ZATB holds is performed. Alternatively, the number of transitions of the input signal INPUT, which take place during the measurement period when the phase signal component ZT holds, in block 587 be counted.

The remaining operations are performed during a computation period that may occur subsequent to the measurement period described above or concurrently with a next measurement period. In block 588 will be in block 587 counted number of transitions by the total number in block 586 divided transitions counted to get a ratio. In block 590 0.5 is subtracted from the ratio to determine a residue R.

An optimal setting of the equalizer 563 is indicated by a value of the remainder R of zero (ie, in block 588 calculated ratio is equal to 0.5), and an acceptable setting of the equalizer 563 is indicated by a value of the remainder R at a predetermined tolerance of zero. The tolerance depends on the criticality of the application, with smaller tolerance in more critical applications. In block 592 a test is performed to determine if the remainder R is within tolerance. A YES result in block 592 causes the processing to block 593 advances where the processing stops when the equalizer 563 within one of the blocks 592 used tolerance corresponding accuracy is set. alternative causes in an embodiment in which the equalizer 563 is adjusted continuously to fluctuations in the signal 109 , which provides the transmission conditions at its entrance, to take into account a YES result in block 592 that processing to block 586 returns to await the beginning of the next measurement period.

A NO result in block 592 causes the processing to block 594 advances where the equalizer control signal 568 responsive to the amount and sign of the remainder R, in block 590 was determined, is changed. The processing then returns to block 586 back to wait for the beginning of the next measurement period.

13A shows a block diagram of a test system 600 according to a tenth embodiment of the invention, in which accurate parametric information is obtained, despite the fact that the test object is located remotely from the test system. In the example shown, a test object 301 an I / O circuit 303 on, which in turn is a transmitter circuit 215 (not shown) and a receiver circuit 105 (not shown). The test system 600 is outside the test object 501 and has a predistortion equalizer 601 , a standard equalizer 602 , a bridge circuit 603 , a phase tracking circuit 207 and a processing circuit 223 in the foregoing with reference to 5 described as well as an equalizer control 565 in the foregoing with reference to 10 described on.

The test system 600 is about a broadcast medium 604 having non-ideal transmission characteristics with the test object 301 connected. The distal end of the broadcast medium 604 that from the test system 600 is removed, is connected to the output of the transmitter circuit and the input of the receiver circuit of the test object 501 connected. The proximal end of the broadcast medium 604 is with the bridge circuit 603 connected. In the bridge circuit 603 is also an input to the output of the predistortion equalizer 601 and an output to the input of the standard equalizer 602 connected. In the standard equalizer 602 is also an output to the input of the external phase tracking circuit 207 connected.

The predistortion equalizer 601 has an input that provides a clean input signal 613 ie, an input signal with little or no waveform degradation. In one example, the clean input signal 613 by a signal generator (not shown, but similar to that described above with reference to FIG 2A described signal generator 108 ), which forms part of the test system 600 forms. The predistortion equalizer 601 predistorted the clean input signal 613 to a predistorted signal 607 to create. The predistorted signal 607 is via the bridge circuit 603 to the broadcast medium 604 Posted. The broadcast medium 604 sends the predistorted signal 607 to the test object 301 to a signal 109 that on the test object 301 , in particular at the input of the receiver circuit, is provided. The non-ideal transmission characteristics of the broadcast medium 604 set the waveform of the predistorted signal 607 down. However, this is similar to the predistortion equalizer 601 applied predistortion resulting from a transmission through the transmission medium 604 resulting waveform degradation. Thus, the signal points 109 connected to the input of the receiver circuit of the test object 301 is received substantially the same waveform as the clean input signal 613 on. Subsequently, parametric information regarding the receiver circuit of the test object 301 from the phase signal output by the receiver circuit of the test object 301 in a manner similar to that described above with reference to FIG 2A . 2 B or 2C received, as if the clean input signal 613 would be applied directly to the input of the receiver circuit.

The transmitter circuit of the test object 301 generates a transmitter output signal 219 that's about the broadcast medium 604 to the test system 600 is sent. The transmitter output comes in the test system 600 as a returned signal 608 whose waveform is relative to that of the transmitter output 219 as a result of a broadcast over the broadcast medium 604 is lowered. In the test system 600 has the signal 609 at the node between the bridge circuit 603 and the broadcast medium 604 a predistorted signal 607 and a returned signal 608 on. The bridge circuit 603 subtracts the predistorted signal 607 from the signal 609 and gives a returned signal 608 to the standard equalizer 602 out. The standard equalizer 602 the same as the shipment through the broadcast medium 604 the reflected signal 608 imposed waveform reduction and generates a transmitted output signal 606 , The transmitted output signal 606 has the same waveform as the transmitter output 619 generated by the transmitter circuit of the test object 301 is spent on.

Parametric information 235 with respect to the transmitter circuit of the test object 301 are then applied by applying the transmitted output signal 606 to the input of the external phase tracking circuit 207 receive.

As mentioned above, the predistortion equalizer 601 and the standard equalizer 602 identical characteristics. The effectiveness of the remote test process just described depends on adjusting the characteristics of the equalizers 601 and 602 to the non-ideal broadcast characteristics of the broadcast medium 604 from. A method that can be used to determine the characteristics of equalizers 601 and 602 to match the broadcast characteristics of the broadcast medium 604 will now be related to 13B described.

The output of the processing circuit 233 is also connected to the input of the equalizer control 565 connected. The output of the equalizer control 565 is with the control inputs of both the predistortion equalizer 601 as well as the standard equalizer 602 connected. The equalizer control 565 receives parametric information 235 from the processing circuit 233 and generates an equalizer control signal in response to the parametric information 568 showing the equalization characteristics of the predistortion equalizer 601 and the standard equalizer 602 controls.

To the characteristics of the equalizer 601 and 602 to the broadcast characteristics of the broadcast medium 604 is that of the test system 600 remote end of the broadcast medium 604 through a degree 610 completed. The conclusion 610 is an electrical no-load circuit or an electrical short-circuit. The clean input signal 613 becomes the predistortion equalizer 601 fed, the equalized signal 607 is over the bridge 603 into the broadcast medium 604 fed and that through the transmission medium 604 output signal 109 falls to the degree 610 at. The conclusion 610 reflects the signal 109 as a reflected signal 620 back to the broadcast medium 604 ,

The reflected signal 620 returns as a returned signal 618 to the bridge circuit 603 back. The bridge circuit 618 subtracts the equalized signal 607 from the signal 619 at the node between the bridge circuit 603 and the broadcast medium 604 and gives the returned signal 618 to the standard equalizer 602 out. The standard equalizer 602 receives the returned reflected signal 618 and equalizes the returned reflected signal to produce an equalized reflected signal 616 to create. The external phase tracking circuit 207 receives the equalized reflected signal and the phase comparator 221 in the phase tracking circuit generates the phase signal in response to the equalized reflected signal 223 , The processing circuit 233 generates parametric information 235 from the phase signal 223 , The equalizer control 565 is responsive to the parametric information 235 effective to an equalizer control signal 568 to generate the predistortion equalizer 601 and the standard equalizer 602 is supplied.

The predistortion equalizer 601 and the standard equalizer 602 have identical relations between their equalization characteristics and the equalizer control signal 568 on. The equalizer control signal sets the characteristics of the predistortion equalizer 601 and the standard equalizer 602 one until the equalizers collectively respond to the clean input signal 613 through the tour through the broadcast medium 604 Correct imposed waveform impairments. The equalizers 601 and 602 have identical characteristics, and the transmission medium 604 has identical transmission characteristics with respect to transmission in the forward direction, ie, from the test system 600 to the test object 301 , and in the reverse direction, ie, the test object 301 to the test system 600 , on. Consequently, the equalizer adjustment process just described allows the predistortion equalizer 601 by the shipment through the broadcast medium 604 Wavelength reduction caused in the forward direction compensates individually and allows the standard equalizer 602 by the shipment through the broadcast medium 604 In the reverse direction caused waveform reduction individually compensated. The equalizer setting method just described is performed before the test object 301 using the test system 600 is tested remotely.

14A is a flowchart illustrating an example of a method 700 according to one embodiment of the invention for using a phase comparator to test the I / O circuit of a test object shows. In block 702 a signal is received at the test object. In block 704 a phase signal is extracted from the phase comparator. In block 706 For example, parametric information regarding the I / O circuit of the device under test is determined from the phase signal.

In one example of the embodiment just described, the I / O circuit includes a receiver circuit and the phase comparator is part of a phase tracking circuit forming part of the receiver circuit, as described in connection with FIG 2A - 2C described I / O circuit 103 of the test object 101 the case is. In this example, the parametric information relates to the receiver circuit. The signal received at the test object is indicated by a Signal generator supplied to the input of the receiver circuit. Alternatively, in one embodiment of the method used to perform in-service testing of the test object, the signal received at the test object is an in-service signal.

In another example, the I / O circuit has a transmitter circuit, the phase comparator is part of a phase tracking circuit that is independent of the transmitter circuit, and the signal received at the test object is received at the input of the transmitter, as in the previous one regarding 5 described I / O circuit 203 of the test object 201 the case is. The phase comparator is located outside the test object. The signal received at the input of the transmitter circuit may be provided by a bit sequence generator or may be an in-service signal. In this example, the parametric information relates to the transmitter circuit.

In yet another example, the I / O circuit includes a transmitter circuit and a receiver circuit, and the phase comparator is part of a phase tracking circuit that forms part of the receiver circuit, as described in connection with FIG 7 described I / O circuit 303 of the test object 301 the case is. The signal received by the test object is received at the input of the transmitter circuit. The phase comparator is built into the test object. In this example, the parametric information relates to the combination of the receiver circuit and the transmitter circuit. The parametric information for the combination may be processed as described above to derive parametric information only for the transmitter circuit. Parametric information relating solely to the receiver circuit may be obtained by additionally receiving a signal at the input of the receiver circuit, as with reference to FIG 7 described.

14B FIG. 10 is a flowchart illustrating an exemplary embodiment of a block. FIG 702 a procedure 700 referred to above with reference to 14A is described shows. In block 710 For example, a signal source is selected according to the parametric information to be determined. Examples of such signal types include a loopback signal path like the one described above 7 described, an in-service signal source that provides a signal similar to the signal seen by the test object during an in-service operation, and a source of a loaded signal that provides a waveform that corresponds to an ideal waveform is deliberately distorted.

In block 712 signal properties are selected. Examples of signal characteristics that can be selected include the signal pattern and the waveform characteristics. Examples of waveform characteristics are frequency, phase and waveform. Using a stress circuit to modify the signal, it is possible to introduce specific characteristics into the signal to emulate desirable operating phenomena and other characteristics.

In block 714 the signal gets from the one in block 710 selected source and with the in block 712 selected characteristics are applied to the test object.

14C shows a first exemplary embodiment of a block 706 of the procedure 700 referred to above with reference to 14A is described. In block 720 the phase signal is processed in the test object. In block 722 the result of the processing is sent off-chip. Examples of the result of the processing include a data-reduced version of the phase signal and the parametric information derived from the phase signal. Additionally or alternatively, in block 724 the result of the processing is used to control a circuit, for example an equalizer forming part of the test object or located outside the test object but used together with the test object, as described above with reference to FIG 10 is described.

The test object may be structured to include a digital signal processor (DSP) used to block the phase signal 720 to process in certain embodiments of the invention. The use of a DSP to perform some of the processing described herein by way of example is described in U.S. Patent Application No. 2005 0 243 950 A1.

14D shows a second exemplary embodiment of the block 706 of the procedure 700 referred to above with reference to 14A is described. In block 730 the phase signal is sent off-chip to an external processing circuit. In block 732 the phase signal is processed off-chip. Optionally, in block 734 the result of the processing used to make a circuit, for example a Equalizer forming part of the test object or located outside of the test object but used together with the test object.

In block 730 For example, the phase signal may be sent off-chip via a high speed port, such as a JTAG test access port.

In one embodiment, the parametric information determined from the phase signal is included in at least a portion of a comprehensive test sequence. A comprehensive test suite used in certain embodiments of the invention is described below under the heading Comprehensive Test Sequence. The parametric information included in the comprehensive test sequence may be used to determine if the test object behaves according to performance specifications.

Clock data recovery circuit

When used as a clock and data recovery circuit, examples are of the above-described phase tracking circuit 107 in each case a phase-locked loop (PLL) and a sampling circuit which extracts the data signal from the input signal. The PLL typically has a low-pass characteristic that allows the PLL to track the phase of the input signal up to a maximum frequency. Frequencies below the maximum frequency are known as frequencies within the band, whereas frequencies above the maximum frequency are known as out of band frequencies.

Embodiments of a phase tracking circuit in which a two-point PLL is incorporated generate the phase signal having a phase-earlier phase signal component (E-phase signal component) and a phase-delayed phase signal component (L-phase signal component). The phase signal components E and L together represent three digital states, namely phase early (E), phase late (L), or no edge. If resources allow simultaneous detection and / or analysis of both phase signal components E and L, both phase signal components are used as the phase signal. In embodiments where the resources are limited but the states of the input signal to which the phase signal is responsively generated are known, only one of the phase signal components E and L may be used as the phase signal. The methods and test systems described in this disclosure may operate on a phase signal having either a phase signal component E or L or both phase signal components E and L.

In the example just described, the phase signal components E and L are one-bit binary signals, one of which indicates whether the VCO signal is early in the input signal and the other indicates whether the VCO signal is late relative to the input signal is. In other examples, each phase signal component is a more than one-bit signal representing the time offset between the VCO signal and the input signal. Substantial additional parametric information regarding the test object may be extracted from a phase signal in which each phase signal component is a two-bit binary signal. Phase signals in which each phase signal component is a more than two-bit signal are also possible.

The phase comparator converts the result of a phase comparison between the input signal and the VCO signal in the PLL into a phase signal composed of one or both of the phase signal components E and L. The phase signal components E and L are conventionally used by a proportional, integral, three-mode PID (proportional, integral, derivative) control loop to vary the phase and frequency of the VCO to produce a VCO signal whose phase is locked to the edges of the input signal. The phase signal components E and L provide a simple binary indication of whether an edge of the input signal takes place before (early) or after (later) an edge of the VCO signal generated by the VCO, i. h., it leads or hurries. A circuit that judges whether the PID phase comparator is leading or lagging the reference phase is used to generate a digital signal that is equivalent to the phase signal. The phase signal can be used in conjunction with the PID loop equation parameters to measure the data phase deviation independent of the test object.

As mentioned above, receiving an input signal having a known bit pattern in the test object allows only one of the phase signal components E and L to be used as the phase signal. The missing phase signal component can be performed by, for example derived a correlation of the phase signal with the known bit pattern of the input signal. The processing circuit 133 performs a pattern matching procedure between the edges of the phase signal component and the edges of the bit pattern of the input signal. The pattern matching process aligns the edges of the phase signal component with the edges of the bit pattern of the input signal. Once the patterns match, those edges of the bit pattern for which there are no corresponding edges of the phase signal component are the edges of the other phase signal component. In one example, the known bit pattern is a pseudo-random bit sequence (PRBS). The processing circuit 133 can perform operations in the U.S. Patent No. 6,760,551 and U.S. Patent Application Publication No. 2005-0243990 mentioned above. The processing circuit 133 may be implemented as software running on a computer, digital signal processor or other programmable device. Alternatively, the processing circuit 133 be executed in hardware.

By extracting the phase signal 123 from the phase tracking circuit 107 and processing the phase signal using the processing circuit 133 , where common techniques such. Autocorrelation, cross correlation, average behavior spectral density, discrete Fourier transform, etc., as well as heuristic processing methods such as those described below with reference to Example 1, may include parametric information related to the dynamic behavior of the test object's I / O circuitry, be generated. As mentioned above, the generated parametric information may be used as part of a comprehensive test suite.

Comprehensive test suite

A comprehensive test suite includes tests and measurements that may be performed during or after the manufacture of an electronic device and that ensure that the electronic device behaves according to a set of predetermined parametric specifications called a behavioral specification. A comprehensive suite of tests can be applied in test contexts such as characterization, manufacturing, calibration and in-service monitoring. You can apply the entire test suite or a subset of them. A test suite consists of a set of test system configurations and the appropriate methods that fit the test context, e.g. B. Available computational resources and test time. For example, in in-service monitoring in which the test object operates as designed, the tests are those that can be performed while the test object is operating with a live in-service input signal, the signal is the in-service input and the circuits performing the test form part of the test object. In addition, in this test mode of testing, it must be taken into account that the memory available for storing the phase signal and the computational resources available for processing the phase signal are limited.

A comprehensive test suite identifies defects in the test object in each test context by performing a specific test protocol designed to optimize detection of the defects in that test context.

In the characterization context, testing verifies the functional and dynamic behavior of the device design over simulated specifications, with a tolerance defining a test boundary. This implies that a value as close to an absolute value of the measurement as is practically feasible is shown. Since the measurement is derived from data that is not directly related to the metric being calculated, calibration may be required to determine the tolerance of the value. The goal of a characterization test is to match the behavioral specifications, to determine the effects of process variations, and to predict whether behavior in mass production will meet the behavioral specifications. Characterization testing is often done in a laboratory bench environment where high speed signals and low noise signals can be guaranteed. The use of larger data sets extracted from the phase comparator is possible, since measurement resolution and accuracy are paramount.

In the manufacturing test context, testing is performed to show that metrics of functional and dynamic behavior of each production test object match the device design behavior specification. Testing is typically optimized to match the test object with the behavioral specification in minimal test time and using minimal test resources to minimize the cost of testing. Certain embodiments of the invention use the parametric information obtained by processing the phase signal in many manufacturing test contexts. According to embodiments of the invention that can be seen from the Phase comparator extracted phase signal to obtain parametric information having a behavioral metric for such behavioral characteristics as random jitter + deterministic jitter (rj + dj = deterministic jitter) of the transmitter circuit, harmonic transmitter circuit jitter (part of rj) proportional and provide integral loop constants for the phase tracking circuit in the receiver circuit, input offset of the receiver circuit, and equalization behavior (ie, dj suppression or reduction) of the receiver circuit. In further embodiments, additional parametric measurements such. B. harmonic contamination inside and outside the tape and Nachpendelverhalten used. To address any manufacturing defect, the test context and measurement hardware combine with the architecture to access the required data being analyzed using a DSP to quantify the manufacturing defect. A suitable stimulus applied to the test object, along with access to the parametric information and processing thereof, results in a parametric measurement. In other words, the fabrication test may require the application of a stress signal (with either an internal or external source) along with accessing and processing data that is difficult to monitor.

In the calibration context, the test system is embodied as a self-test circuit (BIST circuit) built into the test object. The parametric information generated by the test system is used to decide whether control parameters can be adjusted to optimize dynamic behavior of the test object. The test system may perform the calibration operation immediately after an original reset of the test object. The signal received by the test object in this mode may be a specific training pattern. Alternatively, the calibration may be performed using an in-service signal. Calibration testing, which may be performed using an in-service signal, may be performed continuously during normal in-service operations of the test object.

In the in-service monitoring context, the test system performs a non-invasive measurement that does not affect normal operation of the test object. The parametric information generated by the test system (representing characteristics such as a phase tracking error or a processed derivative) may need to be compressed or simply expressed as success / failure data. The in-service monitoring context may include testing for degradation of the properties of the test object's I / O circuitry during in-service functionality.

Certain embodiments of the invention are capable of identifying defects in a given test context for a test object. In such embodiments, the parametric information derived from the phase signal is used to identify such errors in such a test context.

Examples

Examples of specific tests for use in various of the test contexts described above are described below. The examples illustrate various embodiments of the invention. The specific example disclosed can be changed and the same or similar result can be obtained.

Example 1 Receiver Receive Offset Test

As mentioned above, typical embodiments include a receiver circuit 105 a differential input circuit in which a non-zero input offset voltage causes due to a difference in the middle phase between the rising and falling edges of the input signal.

Regarding 2A . 2 B or 2C provides a test system 100 for measuring an input offset, an ideal differential input signal having a known bit pattern as a signal 109 to the input of the receiver circuit 105 , One through a phase comparator 121 generated phase signal 123 becomes the processing circuit 133 fed. The processing circuit 133 records the phase signal and analyzes the same as described above. In the analysis, the bits forming the phase signal are applied to the corresponding transitions in the bit pattern of the signal 109 customized. The bits of each phase signal component (E or L) representing the phase signal 133 , which are adapted to the rising edges of the bit pattern, are counted, and the bits of each phase signal component applied to the falling edges of the bit pattern are counted. In addition, the rising edges are counted to determine the number of rising edges, and the falling edges are counted to determine the number of falling edges. A first probability of each phase signal component received with a rising edge is calculated, and a second probability of each phase signal component received with a falling edge is calculated. Unequal probabilities indicate a non-zero input offset. Optionally, the input circuit of the receiver circuit can be adjusted to reduce the input offset to zero, as indicated by the probabilities being equal, or to reduce the input offset to an acceptably small amount, as indicated by the probabilities differ by less than a threshold.

In the characterization mode, the relationship between the difference in probabilities and input offset for a given device design can be determined by imparting known input offsets to the signal 109 and measuring the resulting probability differences. The probability differences can then be correlated to the input offset. Subsequently, the processing circuit processes the phase signal in the manner described above in the manufacturing test mode for manufacturing to generate a probabilistic difference as the parametric information. A probability difference of less than one threshold value corresponding to the input offset voltage specification for the device design indicates that the input offset of the device under test corresponds to the input offset behavior specification of the device design.

Example 2 - Phase Tracking Circuit PLL Loop Equation

The system embodiments described above can be used to measure phase locked loop equation parameters from which it can be determined if there are defects in the test object. In this example, the loop equation is calibrated to obtain optimum performance over a variation in parameters such as voltage and temperature. The calibration compensates for expected variations in the manufacturing process. The remaining Dynamic Behavior parameters can be compared to design specifications to accept or reject the part. The loop equalization parameters are determined by monitoring the phase signal, while the phase tracking circuit determines one embodiment of the signal 109 which has a repetitive step in its phase or frequency responds. Alternatively, the embodiment of the signal 109 also have a linear phase modulation.

In all test contexts, the signal just described becomes the signal 109 used. The phase signal extracted from the phase comparator of the phase tracking circuit is correlated to harmonic information. In one example, the phase signal is externally recorded and processed as in the 2A shown embodiment. This becomes the external processing circuit 133 imposes a high resource load as the data rate of the phase signal 123 is very high. The example of the above with reference to 2 B described test system 100 This can be the high data rate that is required to get the phase signal 123 off-chip by arranging the processing circuitry 133 within the test object 101 to reduce. This leads to a compromise in the nature of the result, since the on-chip embodiment of the processing circuit 133 usually less powerful than an off-chip embodiment is. Alternatively, as discussed above with reference to FIG 2C is described, a part of the processing circuit 133 within the test object 101 and the rest of the processing circuitry 133 can be outside the test object 101 are located. In one example, a data reducer 151 perform a filtering operation on-chip to obtain the desired data reduction. The resulting data-reduced phase signal 155 will be off chip via a data port 137 which, in one example, is a JTAG test access port, to the data analyzer 153 Posted.

In the calibration context, a longer test time is generally available than in a fabrication test context. A longer test time allows for more complex phase and / or frequency modulation for the signal 109 can be used. This allows a more comprehensive and / or more accurate measurement result.

Example 3 - Phase tracking circuit tracking characteristics (tracking limit)

A tracking rate limit test performed on the phase tracking circuit is an extreme version of a behavioral test within the band. In the tracking rate limit test, the signal 109 configured to drive the behavior of the two-point phase tracking circuit to its control limits. The signal 109 is phase-modulated with a sinusoidal waveform or triangular waveform having a sufficiently large amplitude to cause the control loop of the phase tracking circuit to be saturated. The control boundary of the phase tracking circuit is detected by analyzing the phase signal to detect detection of saturation provided by sweeps of phase prematures or phase lag states occurring where transitions are expected.

In the manufacturing test context, the tracking rate limit of the phase tracking circuit is typically tested using an embodiment of the test system in which the processing circuitry 133 located outside of the test object, as in the above with reference to 2A described example of the test system 100 the case is. The signal 109 is a pseudorandom bit sequence (PRBS) that is phase modulated with a sinusoidal waveform or triangular waveform that has an amplitude sufficient to cause the control loop of the PLL to be saturated, as described above. Using conventional digital signal processing or a digital state machine, phase-advanced or phase-delayed states are filtered out of the phase signal to emphasize the saturated regions. The resulting data is then autocorrelated. A large data set is used for this, so that white noise can be averaged out of the analysis.

If the phase tracking circuit is properly tracking the input signal, the phase signal is random, however, the modulation signal that is part of the signal 109 forms are extracted from the result of the autocorrelation. When the phase tracking circuit is saturated, the phase signal is no longer completely random but has runs of the same state. Consequently, the result of the autocorrelation has gaps in the modulation signal extracted from the result of the autocorrelation. As noted above, the phase signal outside the device under test may be applied to the processing circuit 133 be sent. Alternatively, the above may be described with reference to 2C described embodiment of the test system 100 be used. In this case, the phase-earlier or phase-delayed states are determined by an on-chip data reduction circuit 151 filtered, and filtering results are filtered by an off-chip analyzer 153 processed further.

The shape of the signal 109 and the test system 100 Also just described may be used to test the behavior of the phase tracking circuitry within the band. In such a test, the signal is pointing 109 Characteristics that are within the range of input signal characteristics that is specified to track the phase tracking circuit, ie, the signal 109 is phase modulated with the phase modulation having a sinusoidal waveform or triangular waveform whose amplitude is insufficient to cause saturation of the control loop. A stochastic digital signal processing of the phase signal 123 indicates whether the phase tracking circuit was capable of the phase modulated signal 109 Trace successfully.

Example 4 - deterministic jitter / transfer jitter

The term jitter refers to dynamic changes in the timing of transitions from their nominal timings. A jitter has unique identifiable components. Deterministic jitter (dj) typically results in cases of bandwidth limitations in the transmitter circuit, signal feed-in from other core clocks in the test object, or reflections in the transmission medium. A bandwidth limitation on the output of the transmitter circuit causes jitter when the signal changes the fastest, e.g. When bits in opposite states are adjacent (eg, 1, 0, 1, 0, ...). The bit patterns that provide the most effective display of deterministic jitter depend on the severity of the bandwidth constraint. A jitter that depends on the bit pattern is also referred to as inter-symbol interference (ISI).

A jitter characterizes the extent to which a jitter present at the output of the test object is transferred to the output of the test object. The transmission jitter behavior of a test object can be determined using the test system 200 referred to above with reference to 5 is described. The transmitter circuit of the device under test receives a PRBS as a signal 209 , The output signal generated by the transmitter circuit 219 is via a high-impedance buffer circuit 229 to an external phase tracking circuit 207 delivered. Alternatively, the above may be described with reference to 7 described test system 300 be used, where the output signal 219 the transmitter circuit via a loopback signal path 359 the input of the internal receiver circuit 105 is supplied, wherein the phase signal through the phase comparator 121 is issued. Before receiving the output signal 219 become the external phase tracking circuit 207 or the internal phase tracking circuit 107 calibrated using a signal from a known jitter. It becomes the processing circuit 233 or the processing circuit 133 used to get the corresponding phase signal 223 or 133 to analyze the jitter of the transmitter output signal 219 to eat. Transmission jitter is calculated using this jitter calculation and the jitter value of the signal 219 rated.

A similar test to that just described may be used to determine defects such as ISI and associated harmonic. The injection of harmonic signals into sensitive areas of the test object results in a jitter having components that correlate with the injected signals. These signals are embedded in random phase noise, but DSP techniques can be used to extract the signal components.

Example 5 - Receiver Equalizer

A receiver equalizer is an adjustable equalizer circuit which filters an input signal to reduce ISI caused by bandwidth limitations. An example of a receiver equalizer is included 563 in 10 shown. When the receiver equalizer is set optimally, the phase error is as due to the phase signal 123 regardless of the bit pattern and the rise and fall times of the input signal. On to the transmitter circuit 215 delivered signal 209 is usually a data signal. That from the phase comparator 121 the phase tracking circuit 107 the recipient equalizer 563 downstream receiver circuit 105 extracted phase signal 123 is through the processing circuit 133 processed to parametric information 135 provide. The parametric information 135 become the equalizer control 565 that the equalizer control signal 568 generated, provided. The equalizer control signal 568 becomes the equalizer 563 to cause the equalizer to minimize jitter over the defined range of waveform degradation that is the input signal 219 the transmitter circuit through the transmission medium 559 or a load circuit (not shown) representing the output of the transmitter circuit 215 with the input of the equalizer 563 linked, imposed. More information regarding this example may be found in the above description of the 10 - 12 being found.

Example 6 - Random / Deterministic On-Chip Phase Tracking Harmonic Jitter Within the Band

The phase signal may be processed to determine the spectral characteristics of a jitter resulting from a signal fed from a source external to the phase tracking circuit to the phase tracking circuit. Such jitter has random and deterministic components. Deterministic jitter is caused by bandwidth limits in the broadcast signal or by fed periodic signals.

This aspect of the behavior of the test object can be tested using a test system with a loopback signal located inside or outside the test object. Optionally, the loopback signal path comprises a load circuit as described above with reference to FIG 9 is described. In embodiments in which the loopback signal path comprises a broadcast medium, an equalization of the broadcast medium may be required to prevent a deterministic jitter caused by a bandwidth restriction in the broadcast medium from obscuring the deterministic jitter caused by the bandwidth constraint of the transmitter circuit. In this test, the processing circuit sets 133 the phase signal 123 average power spectral density (APSD) analysis to extract the spectral characteristics of the phase signal. Information regarding the jitter can be extracted from the spectral characteristics. Sources of deterministic jitter can be identified by correlating the spectral information extracted from the phase signal and spectral information relating to signals inside or outside the test object. Random jitter manifests itself as a spectrum that has no specific structure. Such a spectrum is white noise. Software that configures a digital signal processor to perform such analysis is commercially available.

This disclosure describes the invention in detail using illustrative embodiments, but the invention defined by the appended claims is not limited to the precise embodiments described.

Claims (42)

A method of using a phase comparator ( 121 ), the part of a phase tracking circuit ( 107 ), wherein the phase tracking circuit ( 107 ) is based on a phase-locked loop circuit or on a delay locked loop to test an input-output (I / O) circuit of a device under test, the method comprising the steps of: receiving ( 702 ) of a signal ( 109 ) on the test object, the signal ( 109 ) represents digital data; Extract ( 704 ) of a phase signal ( 23 ; 123 ) from the phase comparator, wherein the phase comparator ( 121 ) the phase signal ( 123 ) in response to the received signal ( 109 ), such that the phase signal comprises one or more digital components (E, L), the one or more digital components indicating whether the phase of an input signal of the phase comparator is leading the phase of a comparison signal, or if the phase of the input signal of the phase comparator is phase lags the comparison signal, and wherein the phase tracking circuit controls the comparison signal based on the phase signal to reduce a phase difference between the comparison signal and the input signal of the phase comparator; and determining ( 706 ) parametric information relating to the I / O circuit of the test object, from the phase signal. The method of claim 1, wherein: the I / O circuit has the phase comparator; and the determination is performed within the test object. The method of claim 2, wherein: the test object additionally has a test access gate; and the method additionally comprises outputting the parametric information via the test access port. The method of claim 1, wherein the determining is performed outside the test object. The method of claim 4, wherein: the I / O circuit has the phase comparator; the test object additionally has a test access gate; and the method additionally comprises outputting the phase signal via the test access port. The method of claim 1, wherein: the I / O circuit has a receiver circuit, the receiver circuit having the phase comparator and having an input coupled to the phase comparator; the method additionally comprises the following steps: Providing a transmitter circuit having an input and an output, and Coupling the output of the transmitter circuit to the input of the receiver circuit; and the receiving comprises receiving the signal at the input of the transmitter circuit. The method of claim 6, further comprising, prior to issuing, exposing the phase signal to data reduction. The method of claim 6, wherein the I / O circuit additionally comprises the transmitter circuit. The method of claim 1, wherein: the I / O circuit has a transmitter circuit having an input and an output; the method additionally comprises the following steps: Providing a phase comparator, which is located outside of the test object, and Coupling the output of the transmitter circuit to the input of the phase comparator; and the receiving comprises receiving the signal at the input of the transmitter circuit. The method of claim 1, further comprising, prior to determining, the step of subjecting the data reduction phase signal to data reduction. The method of claim 10, wherein the data reduction comprises either filtering or compressing. The method of claim 1, wherein the determining comprises determining one of a random sender jitter (rj), a deterministic sender jitter (dj), and a harmonic sender jitter as the parametric information. The method of claim 1, wherein the determining comprises determining one of a receiver clock and data recovery proportional and integral loop constant, a receiver input offset, a receiver functional error, a parametric receiver error, and a receiver equalization behavior as the parametric information. The method of claim 1, wherein: The receiving comprises receiving the signal at the I / O circuit; the I / O circuit has the phase comparator; and the parametric information represents deviations between transitional timings of the phase signal and nominal transitional timings. The method of claim 14, wherein the signal has a known transition timing accuracy. The method of claim 1, wherein the parametric information additionally has an average performance spectral density. The method of claim 1, wherein receiving comprises receiving a pseudorandom bit sequence as the signal. The method of claim 1, wherein the receiving comprises the steps of: Providing a bit sequence; and periodically shifting the bit sequence in phase through non-integer unit intervals to produce the signal. The method of claim 1, wherein the receiving comprises the steps of: Providing a bit sequence; and sinusoidally modulating the bit sequence in phase to produce the signal. The method of claim 1, wherein the receiving comprises the steps of: Providing an input signal; and Subjecting the input signal to a waveform degradation to provide the signal. The method of claim 20, wherein the receiving comprises the steps of: Providing an input signal; Predistorting the input signal to provide a predistorted input signal; Transmitting the predistorted input signal to the test object via a transmission medium, the transmission exposing the predistorted input signal to the waveform reduction; and Calibrate the equalization to compensate for the waveform degradation. The method of claim 21, wherein: the transmitting comprises transmitting the predistorted input signal through the transmission medium from a proximal end to a distal end; the equalizing applies a first predistortion; and the calibration comprises the following steps: Terminating the distal end of the mailpiece with a reflective finish; at the proximal end of the broadcast medium, subtracting the predistorted input signal from an overlay of a predistorted reflected signal and the predistorted input signal to obtain the predistorted reflected signal, the predistorted reflected signal resulting from a reflection of the predistorted input signal at the termination; Equalizing the predistorted reflected signal with a second equalization to obtain a reflected signal, the second equalization equaling the first equalization; and Adjusting the first equalization and the second equalization until the reflected signal matches the input signal. The method of claim 1, wherein said extracting comprises converting a linear phase signal into a digital phase signal. A test system ( 100 ) for testing a test object having an input-output circuit (I / O circuit) ( 103 ), the test system comprising: a phase tracking circuit ( 107 ), which has a phase comparator ( 121 ) operable to provide a phase signal ( 123 The phase tracking circuit is configured to control the comparison signal based on the phase signal to reduce a phase difference between the comparison signal and the input signal of the phase comparator, and wherein the phase comparator is configured to generate the phase signal in response to a signal received on the test object representing digital data, such that the phase signal comprises one or more digital components (E, L), the one or more digital components indicating whether the phase an input signal of the phase comparator leads the phase of a comparison signal, or whether the phase of the input signal of the phase comparator lags the phase of the comparison signal; and a processing circuit ( 133 ) connected to receive the signal generated by the phase comparator, the processing circuitry being operable to provide parametric information ( 135 ) related to the I / O circuit can be determined from the phase signal. The test system of claim 24, wherein the processing circuitry is external to the test object. The test system of claim 24, wherein: the I / O circuit is a receiver circuit ( 105 ) having; and the phase tracking circuit forms part of the receiver circuit. The test system of claim 26, wherein the processing circuitry is within the test object. The test system of claim 26, wherein: the processing circuit is located outside the test object; and the test system additionally has a connection between the phase comparator and the processing circuit. The test system of claim 26, wherein the processing circuit comprises a data reduction circuit (12). 151 ), which is located inside the test object, and an analyzer ( 153 ) located outside the test object. The test system of claim 29, further comprising a communication link between the data reduction circuit and the analyzer. The test system of claim 26, wherein: the receiver circuit has an input; and the test system additionally a load circuit ( 182 ), which is connected upstream of the input of the receiver circuit. The test system of claim 24, wherein: either the I / O circuit or the test system includes a transmitter circuit (15); 215 having an output; and the phase tracking circuit ( 207 ) has an input coupled to the output of the transmitter circuit. The test system of claim 32, wherein the I / O circuit comprises the transmitter circuit. The test system of claim 32, wherein the transmitter circuit is outside of the test object. The test system according to claim 32, additionally comprising a load circuit ( 182 ) between the output of the transmitter circuit and the input of the receiver circuit. The test system according to claim 35, additionally comprising an additional phase tracking circuit ( 207 ) between the output of the transmitter circuit and the input of the load circuit. The test system of claim 36, wherein: the I / O circuit comprises the transmitter circuit; the additional phase tracking circuit has an additional phase comparator ( 221 ), wherein the additional phase comparator an additional phase signal ( 223 ) generated; and the processing circuitry is additionally connected to receive the additional phase signal and additionally operable to determine additional parametric information related to the I / O circuit from the additional phase signal. The test system of claim 24, wherein: the I / O circuit ( 503 ) a receiver circuit ( 105 ) and a receiver equalizer ( 563 ) which are connected in tandem with the receiver circuit; the parametric information relates to the receiver equalizer; and the test system additionally an equalizer control ( 565 ) connected to receive the parametric information and operable in response to provide the equalizer control signal to the receiver equalizer. An integrated circuit comprising the test system of claim 24. An electronic device comprising: a digital input-output circuit ( 103 ) comprising a phase tracking circuit ( 107 ), wherein the phase tracking circuit is based on a phase locked loop circuit or a delay locked loop, wherein the phase tracking circuit comprises a phase comparator ( 121 ) operable to provide a phase signal ( 123 ) in response to a signal received at the electronic device, and wherein the phase tracking circuit is configured to control the comparison signal based on the phase signal to reduce a phase difference between the comparison signal and the input signal of the phase comparator; and a signal path for the phase signal, the signal path extending from the phase comparator to a processing circuit external to the phase tracking circuit, wherein the processing circuit is configured to determine parametric information related to the digital input output circuit from the phase signal , The electronic device of claim 40, wherein the signal path extends to a location outside the input-output circuit. The electronic device of claim 40, wherein the phase signal comprises an early phase signal component and a late phase signal component.

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