DE1278150B - Data processing arrangement - Google Patents

Description

FEDERAL REPUBLIC OF GERMANY GERMAN ^ ¥ ^ PATENTAMT Int. α .:

G06f

EDITORIAL

German class: 42 m3 - 15/00

File number; P 12 78 150.9-53 (W 42603)

Filing date: October 18, 1966

Opening day: September 19, 1968

The invention relates to data processing systems and multiple processor orders to increase the "real-tinie" data processing capacity.

The many applications of data processing include cases called "real-time" requirements to be placed on the data processing system, pin very important example of such The case is a modern communication system for voice and / or data. An embodiment such a system is in the journal "Bell System Technical Journal", September 1964, part 1 and 2. “Real-time” demands on data processing also occur with many scientific applications, for example in controlling ascent and landing of spacecraft. Furthermore, in a number of industrial applications, for example the Control of critical processes in production lines, data processing on a "real Tlme" basis necessary. The basic ideas of the invention are presented here for illustration purposes only Described in connection with a telephone exchange. The invention can be used to advantage however, it can also be used in the other areas mentioned.

At least two requirements are placed on a data processor. On the one hand, the processor must meet the "real-time" requirements; on the other hand, one is extraordinary high reliability of the system required. The term "real-time" used here means that the processor must meet all requirements without significant delay. The expression "reliability" means that the plant, despite all the weaknesses, is a man-made work must remain operational.

Communication exchanges are used all over the world. Every place of use of such However, the system has special requirements. For example, a high There is a concentration of subscriber stations, each of which has only a relatively small amount of conversation have relatively few participant positions at another location are each high traffic. From a data processing standpoint, an operator can in these apparently different cases be very similar as all the traffic generated by the participants is almost the same. on the other hand An increase in the subscriber concentration can lead to a substantial increase in the data processing requirement lead at the location of a plant.

Data processing arrangement

Applicant:

Western Electric Company, Incorporated,

New York, N.Y. (V. St. A.)

Representative:

Dipi-Ing. H. Fecfat, Dipl.-Ing. PG Blumbach
and Dipl.-Phys. Dr. W. Weser, patent attorneys,
6200 Wiesbaden, Hohenlohestr. 21

Named as inventor:
Robert Louis Brass, Colts Neck, NJ;
Joseph Bernard Connell, Lineroft, NJ;
John Allen Harr, Fair Haven, NJ (V. St. A.)

Claimed priority:
V. St. v. America October 20, 1965
(498 673)

In addition, there can be very different requirements for different types of equipment changing from place to place Services are available. For example, in a residential community there may only be a small need for the many there are new and highly advantageous features of switching systems that deal with HiKe a program control can be achieved. In a business district, however, a switching system will be required that is the various businesses provides complicated special operating features. These special features can be used without additional data processing capacity. Although the one standing in two plants Traffic almost equal to its canoe, is for the Plant where there is a need for the new and modern operating features are available, a data

809-6 W / 270

Processors with greater processing capacity depending on the limitations when considering the requirements Unit of time required. considered attached to a message system or other

A telephone switching system is becoming more common "real-time" data processors with appropriate wisely set up to take into account the existing requirements. None of the known traffic requirements one location area is sufficient. It takes into account the 5 orders in a satisfactory way However, the probable growth must also take into account the following problems: a community. It is not out-

usually that an office ^{grows ten times, or L} growth of the "^^ - ^" - data processing more. ' It is then not economical to have a capacitance, with the input signals of the plant

to replace such office, if the maximum ver io are treated ^{as a whole;}

sweeping capacity of the originally installed 2. Reliability of the system;

nesting is achieved. The basic idea behind the invention is that the _{common use of} large storage devices can be used economically in the normal _effective manner without inadmissible mutual

Growth of a data processing system, for example disruption to access

assign a message switch to 15

to meet the increased processing requirements. The invention aims to solve these problems are sufficient, regardless of whether these requirements come from a data processing arrangement with from an increasing number of participants, to a main processor, with a memory that contains increasing traffic or increasing data with which the main processor Operating requirements result .. .. ao works with a storage manifold system,

The data processing capacity of a given processing facility by the main processor is witnessed by many factors, optionally encoded memory read and limited. Among the factors primarily related to memory write commands to the main processor Contribute to such a restriction, which include an optional read and write access to the memory cycle time, the response time of the processing 25 rather allows with an input-output circuit and the physical distance between systems, the input information for the master Components of the processor. Currently processor supplies and produced by the main processor the trend is towards faster input-output commands, and with it Storage and components. Economic over an input-output manifold system for However, limitations and other factors limit the transmission of the input information and the always the practical data processing capacity input-output commands from input-off Processor. . gangs system to the main processor, and vice versa.

Systems are known in which more than one The invention is characterized in that the

Processor is used to carry out all work functions assigned to the processor data processing arrangement. A stored program-controlled auxiliary processor example of such arrangements is a telephone that has a switching system connected to the memory busbar system with crossbar switches. When the main processors work, as well as, a wired logic circuit, the auxiliary storage bus system. that with the help of work functions can only be carried out one after the other from those generated by the auxiliary processor. When operating several different coded Hilfsspeicherlese- and Hüfsspeicherschreib operation requirements so multiple Mar- details the auxiliary processors an optional Merer be active simultaneously, and different ⁴⁵ read and write access to the auxiliary memory enabled marker can be used to carry out successive light, and that the auxiliary processor an access control gender related to work functions. Contains a single arrangement that can be used on certain of the memory operating requirements. Such long-read and .Speicherschreibkommandos responds to processing arrangements working together with the aid of the auxiliary memory reading and auxiliary memory apparently independent circuits. The data processing ⁵ ° write commands and the auxiliary memory collective processing capacity of the system is therefore directly dependent on the line system of the main processor and a choice of the number of installed circuits. .Assign read and write access to auxiliary memory

Enable in the field of data processing systems.

similar attempts were made at high speed.

undertaken to use more than 55 according to jointly in an effective manner by the main one Processor uses the data processing request processor and the auxiliary processor, struggling to be sufficient for a system. In general - Advantageously use both the main processors with these arrangements either for the overworker or the auxiliary processor machine cycles transmission connections between two processors with the same duration. A clock circuit in the auxiliary provided, so that one processor at a time becomes the input processor in phase with one of the main clock peeling output devices the other represents, or it .tang held in the main processor and. on two transmission links between storage points are synchronized. The first point defines the intended. The above information regarding the start of a main processor machine cycle, State of the art are only very general and the second point defines discrete times, because the number of known or suggested 65 of the main processor machine cycle. Of the Genetic multiple processing orders is too large, auxiliary processor leads relatively complicated to be taken into account here. All commands are issued whose execution cycle many have known However, arrangements may involve severe machine cycles. An auxiliary processor

5 6

Execution cycle can be temporarily used by the main auxiliary processor from the main processor as storage processors are interrupted. The memory read is addressed, the main processor pro- and memory write commands of the main program, the data from the shared memory only interrupt an execution cycle, use sooner, if auxiliary use is not available of the auxiliary processor, the work functions of the worker are not changed significantly, since the when the command is received, the main processor then has direct access to them machine cycle has ended. Has memory locations in the event of an interruption. This creates an orderly citation the auxiliary processors that of the main processors grow the computing capacity of a per received Save command. After termination program-controlled switching system with minimal the work functions in connection with these changes to the main processor program and With this command, the auxiliary processor proceeds to enable individual switching. Ending the interrupted execution cycle The auxiliary processor advantageously performs before he Further. Storage commands served by the main processor,

The data processing capacity of a program is tested to ensure that it is not Controlled data processing system is processed with pre-15 straight information or accordingly teij is significantly increased by the fact that an auxiliary processing information works from that memory worker is provided that come to a storage point of the shared storage, transfer order of the main processor linked by the command from the main processor pelt and is specified jointly by storage commands from. Since access to the common Main processor and memory used by program instructions by the main processor only controls that are made from a common used with the help of the auxiliary processor is not a Large storage systems can be obtained. further storage blocking is required in order to

The work in the facility is carried out by the main-side disrupting the use of the common

and auxiliary processors to avoid working together on the following store.

Basis stated: 25 The invention is intended in the following in connection with

a) The auxiliary processor carries out the »real-time« - the drawings are described in more detail. It

- ■■ gangs-output functions a limited, da- ^ze | Block diagram of an implementation

associated with data processing and certain,. . ^& , "... _. , ... ,, °

other output functions for which less gjg ^»6 ^ ^eme data processing system after the

strict time requirements apply; ° _p . _g _ ^ _mehj . _{mg emzeme walking block circuit} .

b) the main processor maintains the more complicated picture of an embodiment for a message work function with reference to data provided by the auxiliary switching system, the worker according to the invention and supplies the data, is organized and with the main sections of the those of the auxiliary processors at the outgoing radio switching system and the flow of information used; see the main sections of the plant

c) the auxiliary processor independently provides errors,

and errors relating to its own operation, Fig. 3 shows the block diagram of an embodiment

the operation of the input-output system ^{s game for an} auxiliary processor working in a data

and the shared storage units ⁴ ° processing plant according to the invention are used

with whom he is associated. Can be seen

lent the diagnosis and correction of fixed- F1 g. 4 the block diagram of a main processor,

errors made depends on the auxiliary processor ^Fi S · ^{5 a} timing diagram showing the mutual

however completely from the main processor. Represents relationships of timing signals that the

45 logical operations in an auxiliary processor

This assignment of work generally sets the taxes

"Real-time" requirements for the main processing unit. 6 and 7 in the assignment according to FIG. 9 one step down. In this exemplary embodiment of the invention, the synchronization between a main processor of the auxiliary processor to the same input / output 50 and an auxiliary processor is coupled to the transmission transmission system, with the FIG. 8 the interrupt order of the main help the transfer between the main processor including the interrupt and the input-output system takes place. These possibilities when operating a main processor by arrangement are made possible with advantage by the ancillary processor mentioned above. level common assignment of input-output 55
Gang work to the main and auxiliary processors. contents

As indicated above, the main processor has _A ,., _A,. ".

Access to the auxiliary processor with the help of the same general description of the system (Fig. 1)

Memory read and memory write commands, the description of the switching system

can be used optionally by the main processor, 60 as an exemplary embodiment (FIG. 2)

to access the storage units of the main _XT . ... _Tr

to obtain processor memory. In the case of a system, message transmission within the switching

at the due to the limited requirements

Visible to the data processing, no auxiliary processor input-output system 180

is required, the main processor 65 must accordingly be the central pulse distributor 143

perform functions a) and b) yourself. However, since main scanner 144

an auxiliary processor is not provided, the switching network 120

Features c) not required. In addition, since the Mixed Units 174

Central processor 100 storage system 176 are stored. The data-

Main processor 101 (Fig. 4) processing is developed by main processor 101

Main processor program memory 102 speaking program instructions carried out, which are in

Master Processor Patent Storage 10a storage system 176 are stored. The memory

Auxiliary processing store 172 ⁵ system 176, which contains the second main section of the

Substitute processor 171 (Fig. 3) of the central processor 100 is connected to the main

ÄUber processing of call processor 101 via a main memory transfer

Linking transmission system 106 connected. Program instructions, data and certain. Tax information is provided by the

Maintenance transfer and synchronization ₁₀ master processor 101 to storage system 176 and

(Fig. 6 and 7) vice versa with the help of the main memory transfer

Operation time control in auxiliary processor 171 transmission system 106 transferred.

Holding Auxiliary_processor 171 Storage system 176 includes one of many

Interrupting the main processor 101 units existing main processor memory 103,

Interaction between main and auxiliary 15 in that. Program information and other information

processing mations of a semi-permanent type and also in-

Main storage conimandos for auxiliary processor 171 * ^orn f ^ti T ° i can be saved for the

frequent changes with normal speed

Auxiliary memory command for auxiliary processing _e i _t ^ he system are required. The main _{storage 172 ao} worker 101 is associated with the main processor storage

Comparison of critical addresses 103 with the help of main memory commands in Ver

binding via the main memory transfer

General Besehreibung exceed the plant (Fig. 1) ^s y ^{stem X06} f ^to the main processor memory 103

will wear. The main processor memory 103

The main sections of a data processing unit 25 executes the main memory commands and gives the system according to the invention are shown in FIG. either the requested information on the main data processing unit 101 via the transmission system 106 is subdivided into a central processor 10ft and a back or written with a storage command ent-input-output system 180. The data held in a prescribed location within the central processor 100 and the input / output 30 half of the main processor memory 103 enter. The system. 180, the main processor 101 processes both the input / output system 175 and the input / output system 180 and from the input / output system 180

The input-output system 180 can dispense with a main processor memory 103 obtained data Group of circuits include their speaking program instructions from the main processor operation "Real-time" requirements with regard to 35 memories 103,

your program control includes. An example of the storage system 176 further includes one

Such an input-output system is the processing auxiliary processor 171 and an auxiliary processing network with the associated control memory 172. The auxiliary processor 171 is a circuit of a telephone exchange. The special purpose data processing device leading to the input-output system 180 contains information 4 ° implementation of those repetitive and sources which serve as input signals for the central, time-consuming functions of the input and output processor 100 and which it processes. The input-output system 180 also contains circuits ultimately implemented by the main processor 101 that would perform the operational functions of the input, the "real-time" capacity of the central input-output system 180 corresponding to input, - 45 processor 100 in controlling the operation of output command information from central input-output system 180 has been restricted. Processor 10.0. steer. This command information- The auxiliary processor 171 is functionally un-

Typing is dependent on the central processor 100, but dependent on the command of the main processing subject to its program, in its memory terminal, and it transmits to the main system 176 stored data and the inbound 5.0 processor 10.1 those information that are required for the information from the input-output system 180 main processor 10.1 to carry out the compass generated, More sophisticated data processing operations are required

The central processor 100 represents a central process for the functions of the incoming-outgoing person Datenververarbeitungeinric.htung represent * the system ISO to be able to execute and the for Execution of the various operating, maintenance 55 the maintenance of the system necessary complicated and administrative functions are used to be able to carry out data processing. Control of the input-output system 180. The auxiliary processing memory 172 is in this

are required. The central processor 10 receives a verbal embodiment captures input information from input-output storage system of high capacity and with random access system 180 via the input-output-Uber- 60 Hchem access in which the program for control transmission system 175. The central processor 100 of the auxiliary processor 171 and the data stored transmits control and command information about the being with which the auxiliary processor 171 is working. the Input-output system 180 via the input ^ - message transmission between the auxiliary processing output transmission.ssys.tem 175. worker 171 and the auxiliary processor memory 172

The central processor 100 includes a main 65 follower by means of the auxiliary storage transmission system processor 101, the data processing functions 173. The auxiliary processor 171 creates auxiliary memory with Reference to data from the input-output system commands and transmits them. via the transmission and with reference to data stored in a system 173. to employee memory 172. The

9 10

Auxiliary processor memory 172 carries out this command is synchronized by control signals from the dos and outputs either from the command. Main processor 101, which via the control cable 213 retrieved data or program information is transferred back to the auxiliary processor 171. Under or writes data or program information, control of from the auxiliary processor memory 172 those contained in the command are processed into an acquired program by the auxiliary processor Storage location within the auxiliary processor 171 the information that it receives from the input memory 172 a. Output system 180 receives and information

The main processor 101 stands with the auxiliary processor from the auxiliary worker memory 172 to service and Worker 171 in the same way as if these management requests from the operating scarf part of main processor memory 103 would be. From the input-output system 180 functions to the main processor 101 sent out and to the auxiliary know. When the auxiliary processor 171 information Foreman 171 has addressed main memory commands that are available for further processing by the wWare carried out by auxiliary processor 171. Standing by on main processor 101 will be normal-reason from main memory commands from the main way this information in one of a lot of processors 101 the auxiliary processor 171 maintains a number of storage areas in the auxiliary processor Speider the following functions: rather 172 stored, which are known as "funnel".

1 τ,., T, τ c ■ Typically, the following machining

1. jerk disclosure of information from a reasonable _t ^ eser information by the Hauptverarbeigebenen register m himself on the over- | _{Q1 / ur E of} i _n f _ormat i _on s which the transmission system 106 to the main processor 101; _{ao necessary control operations of} the input-output

2. Define writing of program or data entry system 180. This tax information, the functions contained in the memory command are stored in suitable memory areas (commands are, in a specified register in the auxiliary buffer register) of the auxiliary processor memory 172 self; given. The auxiliary processor 171 removes the

3. Obtaining with the help of an auxiliary memory 25 control information to the memory 172 and gives the commands to auxiliary processor memory 172 corresponding input-output commands for of program or data information from input-output system 180. The activity of the a place within the memory 172, the auxiliary processor 171 can thus roughly be identified Draw the main storage command specified: it collects from main processor 101 is, and this information is returned to 30 processing data, is sent to "funnel" in the auxiliary department Main processor 101 via the transmission processor memory 172 with this data and exchange system 106; accepts and processes information provided by the

4. Write program and data information master processor 101 to the auxiliary processor memory information entered in the main memory command.

are held in a specified memory location in the 35. The above explanation shows that this is a Auxiliary processor memory 172 using an indirect message transfer between the Auxiliary memory commands; Main processor 101 and auxiliary processor 171

5. carrying out one of a plurality, in the main ^{with the aid of the} auxiliary processor memory 172 is memory command specified Wartungsfunk- This type of Nachnchtenübertragung is the ability of the main processor 101 _ones by _t j 40 allows,

address the auxiliary processor memory 172 so as to

If an addressed to the auxiliary processor 171 as if it were part of the master processor memory 103

Main memory command is received, the would hold. Thus, the auxiliary processor memory 172 becomes

Auxiliary Processor 171 operates independently from Main Processor 101 and the Auxiliary Processor

long enough to share main memory command 45 171, both as a source

to be able to perform. The auxiliary processor 171 sets for data as well as a destination for data,

then the execution of his own work radio- As the auxiliary processor 171 from the main processor

functions in accordance with its program, which is addressed as memory in the 101, programs

Auxiliary processor memory 172 is stored. of the main processor 101, which the auxiliary processor

The auxiliary processor 171 cannot use the same data obtained in 50 memories 172

input information from the input-output system can be changed significantly if no auxiliary processing

180 how the main processor 101 is received and ter 171 is provided, since in this case the auxiliary

can, like the main processor 101, from the input processor memory 172 in the main processor memory

Output system 180 would contain input output 103 to which the main processing

Generate gangs commands. The auxiliary processor 55 ter 101 has direct access.

171 can therefore according to its own pro- The auxiliary processor 171 independently establishes errors and according to the results of the data gymnast and mistakes of his own working method and processing by the main processor 101 corresponds to the operation of the auxiliary processor memory 172 the time-consuming operations involved in the creation as well as the input-output system 180. the input-output commands and errors detected during 60 diagnosis and correction Relieve the reception of input information. However, performed by main processor 101. Of the Subsequently, the auxiliary processor 171 performs the routine main processor 101 which may in the auxiliary processor operations and the highly re-stored information 172 accordingly fetching data processing operations for which information introduced by the main processor in the other case the main processor 101 requires 65 memory 103 have been obtained. In this way would be borrowed. The main processor 101 and the auxiliary processor 100 are used to increase the data processing capacity of the central processor with the aid of the auxiliary processing 171 work simultaneously and independently. Your ope-

11 12

to worsen the situation and, without specialized arrangement, to double certain control functions in various dimensions that cut through the switching system for the desired high level. Are necessary for the reliability of the system. Expression in this intermediary chosen as an example - “. ,, ....,. , ", ^ R. A central impulse distributor suitable for information transmission is used in the transmission of messages within the switching _{5 of the} above-mentioned reference from "Bell System Anlage (Fig. 2) Technical Journal" in a beginning on p. 2255

The main sections of an exemplary long-distance essay are described

Intercom with a program control _Λ .

In accordance with the invention, main scanners 144 are shown in FIG

shows. Many sections of the switching system and io The main scanner 144 is used for monitoring

their components are essentially identical to certain circuit elements of the switching system

that of a telephone exchange that uses the current operating status

reproduced in the above-mentioned reference from »Bell der Anlage. The monitoring state

System Technical Journal «, September 1964, this selected circuit element is via the

is written. In the following explanation of the received as 15 manifold 109 and is of use

The telephone exchange system chosen is to be used in the maintenance of the system and the fault

therefore often to the abbreviation mentioned literary diagnosis. The main scanner 144 is a proportion-

turstelle are referred to. moderately fast working circuit and can maxi-

A functional description for each major time once every 11 microseconds from either the

Block in FIG. 2 becomes in the immediately following processing 20 main processor 101 or from auxiliary processor 171

cut given. This description is followed by a general address.

my explanation of the way in which the main scanner 144 contains a ferrod matrix

Speech functions from the connection (ferrite rod matrix) selected as an example for incoming circuits that

location as a whole. are to be monitored, and facilities for elective

,.,.,. ,,. ,,, 35 via the bus 108 of the transmission

Subsequent transmission within the switching _system 175 to the main processor 101 and to the

^ai " ^a S ^e auxiliary processors 171 the monitoring states of a

A large number of bus systems and selected groups of monitored circuits on cable systems provide the transmission paths for control reason of a network command to transmit signals and information between the elements 30 via the bus 104 of the transmission of the central processor 100 and between this system 175 from the main processor 101 or from and various other portions of the intermediary auxiliary processors 171 . In general, a collective turn in this embodiment of a line contains a large number of wire pairs, the scanner suitable for inductive communication is an information destination or destination journal in the literature cited above between an information source or sources and 35 from Bell System Technical «Are linked in an essay starting on p. 2255. Data is described via a.

Collective line in parallel form as short pulses switching network 120

that arrive at the destination at the same time. 40. The switching network 120 provides a primary Multicore discrete cable, two-sided overall portion of the input-output system 180 of this hosted transmission paths between selected waste management example. It is optional metallic sections of the central processor 100 and other compounds forth to with The wire connections subscriber lines with subscriber lines, pairs of these cables are either inductive or di- 45 subscriber lines with connecting lines, directly coupled with the source for control signals and their connecting lines with connecting lines to detuning. bind as well as subscriber lines and connection in F i g. 2 the various bus lines with sound sources, signal transmitters, signal and cable systems, the transmission paths between receivers, maintenance circuits and other operating circuits to connect different parts of the switching system, which provide service circuits for special ones, are not shown in detail. In Fig. 2, telephone functions are required. The structure merely shows the flow of information between certain sections of the switching system which are suitable for use in this exemplary embodiment, in order to indicate to a switching system which sections of the switching network 120 are each function block input information in the above-mentioned literature system «Receives in two roles. A more detailed explanation of certain clauses are described, which begin on p. 2193 or 2221 of the transmission of messages within the center.

len processor 100 follows later. The switching network 120 only provides transmission

^. . "" _ "Transmission routes, means for producing such transmission

Entrance-exit system 180 _{6o tra} ° _un | _swe | _{e and means of} monitoring the paths

Central impulse distributor 143 _{obsessed The central} processor 100 contains a list

The central pulse distributor (Central Pulse District drawing of the occupied and idle status of all network

butor) 143 is an electronic high-speed factory connection as well as the structure of each security converter, the transmission path set on the basis or reserved via the cable 111 via CP £> commands (input-output command 65 the switching network 120. These recording commands), those from the main processor 101 and from the gene are in the main processor data store. Auxiliary processor 171 is transmitted 103 via the cable 107. The record relating to the becoming-busy provides output signals. These signals carry the state of the network elements is commonly called

13 14

Network storage plan called. The central network, such as 123, 127, 135 and 139, are there workers 100 interprets connection requirements between relatively fast-working circuits see certain components and certain components and can use network commands with a maximum-free transmission path via the switching network repetition speed of once per work 120, in which it addresses the requirements for the 5 11 microseconds,
binding and the mentioned busy-free state of the network control circuits, which checks connection paths when this is possible. Management example of a switching system used In this exemplary switching system, the control of the switching network 120 and the "Bell System Technical Journal" in an article beginning on its various monitoring circuits 123, io p. 2221 are described in the above-mentioned literature. A loading 127, 128, 135, 136, 139, 140 etc. based on the writing of scanners and signal distributors, the network commands (input-output commands are used in this embodiment) that can be sent from the auxiliary processor 171 to the switching , can be found in an article that begins on p. 2255 network 120 via the manifold 104 of the above-mentioned reference. With the exception of carrying system 175 are transmitted. The indirect control of the switching network 120 operations required for understanding the invention is not described further here, and the control and monitoring of the switching network 120 is not further described.
Network 120 connected elements is on a _., _XT,. ,. ,, ",
Number of control and monitoring circuits Mixed network units 174
distributed. This distribution provides an efficient and convenient buffer between the central processing example of a switching system is a high-speed 100 and the slower teletype unit, a card writer for the network control and monitoring circuits. Main processor memory 102 and a charging die Main control and monitoring elements of the calculation tape unit. These parts of the system are switching network 120 : 25 are not necessary for an understanding of the invention

"__,,,, .. ·, ·.," "And are not described here.

1. Network control circuits, e.g. 122

and 131, the network commands from the auxiliary central processor 100

Processor 171 take up and contact _{The central} processor 100 is a centralized one

Chen selectively to these commands parts nverarbeitungseinrichtung _{30 Date} that connect to the implementation of a selected transmission path over which _{the various} Pernsprech-, maintenance and Ver-switching network 120, or loading _wa i _tU features fully a telephone exchange Indeterminate test or Wartungsfunküonen Removing _{ankge used The central} processors 100 ^drove ; can be divided into five main parts:

2. Network scanners, such as 123, 127, 35 _{Λ TT x} , ... * _M
135 and 139, each of which has a Ferrod-Ab- ^L main processor 101,

tastmatrix contains, to the elements of the system, 2nd main processor program memory 102,

for example subscriber lines, interconnection 3. main processor data store 103,
connection lines and connector circuits, to the 4th auxiliary processor memory 172,
Observation of their surveillance status 40 5 Auxiliary processors 171
are switched and based on network commands from auxiliary processor 171 via main processor 101 (Fig. 4)
the trunk 108 of the transmission system

175 on the auxiliary processor 171 information relating to the in F i g. 4 shown main processor leads the

Lich the monitoring status of a selected processing function according to the program, overcommands a group of circuit elements which are carried out in the main processor program; memory 102 are stored. The program includes

³ ÄStfis

, j _DD . _1jr ', .. _<m . 50 decision-making orders as well as non-decision-making

Commands from auxiliary processor 171 on a _fe that are to be executed one after the other,

selected output connection actuation * or processing of data in the main processor

arithmetic functions are used in the

The network control circuits, such as the generation of data from the memories used, for example

122 and 131, and the network signal distributors, such as the host processor program memory 102

for example 128, 136 and 140, are ratio 60 and the main processor data store 103.

moderately slow working circuits and to the non-decision commands are in traffic with

Each entity outside of the main processor 101 and can ensure completion of a task

of these circuits with network commands for moving and processing data.

a maximum repetition speed of speaking the commands of the command words used.

addressed once every 25 milliseconds. It incite 65 non-decision orders in addition to

however, commands can be sent to different networks.

factory control circuits to the main processor 101 at intervals of 11 micro-transmission operations

Seconds. The network scanners, executing the next command in the sequence. Some

15 16

Few non-decision orders are called unconditional divorce orders leading to a continuation on the jump orders. These commands indicate that the next command of the current sequence leads; a jump from the current sequence of Pro switches the adder-one circuit 454 the address program command words to another sequence of Be in the program address register 451 and passes the incorrect words without one Decision should be made. 5 forwarded address back to the program decision commands are used to store pre-address registers 451. The adder-one circuit 454 changes due to changes in the state of part- can also be used as a general-purpose increment circuit subscriber lines or connecting lines that are used for data, that are serviced in one of the indexes of the exemplary switching system, such as 464 or 465, are stored in, or of state changes with respect to the io.

To arrange maintenance of the system. Decision The main processor program memory responds to commands indicating that a decision is to be made with reference to memory commands which are transferred by the program to certain observed registers addressed by the instruction address register 451 , and specifies the specified conditions. The information from the specified memory location about the result of the decision causes the main processor to take route 456 back to the main processor. The additional information returned by the next command in the sequence is transferred to the command word missword or entered in register 457 on a command. The command includes a jump to another sequence of command words. The main processor 101 processes based on the data address field and a check field. Those of the command word strings data and generated and over- 20 levels of the command word register 457, which contain the operation carries commands for the control of other units tion field, are with the command word decoder system. These signals are used to connect the encoder 458 . Decoder 458 provides main processor program memory 102, main DC output signals to decision processor data stores 103, slave processor logic 459, and instruction combination gate circuit 171 and input / output circuit 460. The combinations of DC current Control arrangement 180 . Output signals are discretely associated with the instruction reproduced by the main processor 101 operations field. The internal gate functions of the main

A. Multi-level flip-flop registers, processor 101, which respond to the receipt of a command

B. decoding circuits, 30 from the main processor program memory 102

C. Private collective service ^systems for messages> are thus defined by the operational field of the transmission between different EIe commands.

elements of the central controller, ^the data address field of the command can be as

r, - ^, ^ χ * !. 1 - Operand for the index adding arrangement 461 or as

D. Receipt to receive a, operand for the logic circuit 467 are used, input information, ^ _{index addition} ° _order | _{66 combined} optional

E. Circuits for sending commands have _the data address field with the content of one and other control signals, _{or none of the} index registers, such as 464

F. Sequential Circuits, and 465. That in index adder assembly 466

G. Clock sources, 40 generated word can be used as the address of a memory H. Gate circuits for combining time commands for the Hairpt processor data memory 103,

^{Control impulses with one} s memory commands derived in the system for the auxiliary processor

th DC conditions. ^{171 or to} obtain information from the

Main processor program memory 102 is used

The main processor will be a synchronous plant in 45 The address generated by the index adder arrangement 466 in the sense that its functions under control are available from the memory addresses of a multi-phase clock circuit 461 , which checks the time decoder 467, which supplies input signals to the control signals for carrying out all functions, command combination gate circuit 460 in order to be able to operate within the Processor supplies. The timing control. Contents clef "index adder 466 signals from the clock circuit 461 are transmitted direct-speaking to one of the above-mentioned use current signals from a number of sources for purposes of instruction.

half of the processor in the command combination from the main processor data memory 103 or

Gate circuit 460 combined. The output signals obtained from the auxiliary processor 171 become data

of the gate circuit 460 are received via the multi-wire in the data buffer register 468 . The registry

Command cable 462 to the appropriate points in 55 468 is used to carry information from

transferred within the main processor. to receive these sources as well as data

Fig. 4 shows the main elements of the main processing of these sources.

Beiters 101. It should be noted that the Gat- The main path for moving data between

switch circuits which are used for selective transmission from the main data sources of the main processor 101

Data and the by signals on wires of the command 60 and the various destination registers in the

kabeis 462 exercised internal control required main processor 101 contains the general purpose logical

are not shown in this figure. Processing circuit 469. This circuit combines

The main processor 101 interacts with the main defined logically two operands in the transmission

processor program memory using the pro one of the operands within the processor. Of the

The gramme address register 451 and the transfer 65 first operand always contain the content of the register

route 463 in connection. In the case of execution 470, while the other operand consists of a

obtained from non-decision orders (except unconditional selected source of the main data sources

Jump commands) and when executing Ent. The main data sources are the buffer register

17 18

468, the index registers, such as 464 and the interrupt levels H and / enter into un-

465, accumulator register 472, register 473 even and even intervals of 5 milliseconds

and the index adder assembly 466. The two on. During these interruption times, the

Operands can be processed by the logical functions Main processor 101 data processing from the

AND, OR, EXCLUSIVE-OR are linked within a strict time frame

den, whereby provision is made for a complementation of the.

resulting data word is met. The remaining levels G to A are fault

Logical function used is indicated by the operational interruptions, each specific

field of the command word specified. The interferences correspond. The interruption level F

The io generated in the processing circuit 469 represents, for example, a command failure

Data word can be sent via bus 474 to or a fault in auxiliary processor 171

Data buffer register 468, a selected one of the index occurrences of a level F interrupt

register, such as 464 and 465, the accumulator- the F-stage program first the source of the

mulator logic 471, the register 473, the index interrupt signal and then proceeds to

Adding arrangement 466 or the adder-one circuit 15 further measures to avoid the displayed fault

454 are transmitted. to eliminate. Level F interrupt signals

As noted above, the first operand is for the will be from auxiliary processor 171 to register 479

Processing circuit 469 transfers the contents of the register in the main processor 101.

470. Data from the following _TT , .. ". ,., ._

which (sources are transferred: (a) the input ao main processor program memory 102

embed via path 475; (b) the index adder is the main processor program memory 102

arrangement via route 476; (c) the data - a storage system organized by words of higher level

address field of the command word register; (d) Sam random access capacity. With this one

line 477; (e) the manifold 478th specific embodiment of the invention

The accumulator logic 471 provides an additional 25 magnet wire memory organized by words Device for processing data. You using a magnetic card coding and contains arrangements for linking two with non-destructive reading to advantage than Operands by the functions AND, OR and storage element of the main processor program addition. Memory 102 used. The naturally semiper-

Decision logic 459 includes circuitry 30 of permanent master processor program memories 102

to analyze data that is on the aggregate to store the more permanent information

line 474 and used in the accumulator logic 471 in the system. These include those from the main

the execution of decision commands processor 101 executed programs and a

step. The outputs of the decision logic including number of translator information

459 include direct current signals for the command 35 of the telephone number-port number translation and the

combination gate circuit 460. Information regarding the service class of

The input-output converter 475 provides the subscriber lines. The organization and control

Transition between the main processor 101 and a storage arrangement which is used as the main processor

the input-output system 180. The reworker program memory 102 can be used,

Setter 475 uses data stored in the accumulator 40 in the above-cited reference »Bell

Logic 471 or in register 473 according to System Technical lournal «on page 2097 ff.

output signals of the command combination gate switch writes.

tion 460 occur to input-output command _TT . . _. , ^ _n .

dos for the input-output system ISO to be main processor data memory 103

witness. 45 The main processor data store 103 is a

The operation time of the main processor 101 is higher according to the word organized storage system according to the schedule of FIG. 8 organized. This plan contains a basic level, which is stored at the very bottom of certain information of the plant, in FIG. 8 is shown, on which the greater part of the frequent changes are required. The work of the main processor is carried out. 50 Main processor 101 can use the data transfer system 106 to write information into or from the main processor data store 103 used with near "real-time" requests, a high percentage of the processing can read it. Since information is carried out in the main without precise time requirements, the processor data store 103 can easily be dealt with by the. The data processing which can be changed at a normal speed of the plant, a certain temporal accuracy, is information for which frequent and rapid changes are required, and the data processing which is urgently required changes are stored in it. To will count this information on one of the interruption levels K to A.
carried out according to FIG. K is the lowest., _T -. . "-, - tr, ·
Interruption level and A the highest. A higher 60 * · information related to the processing of interrupt level interrupts functions that are received ^of service requests, the auxiliary vomι a lower interrupt level or on the processor 171 (eg GeGrundstufe be performed. Sprachssignalmformationen)

The lowest interruption level is ² information relating to recent changes

Auxiliary processing request interruption. These 65 struggled to convert phone numbers to

Interruption level K indicates that the auxiliary connection numbers,

atbeiter 171 an urgent message for the main 3. Recent changes to information from the

processor 101 has. Participant service classes,

4. administrative information,

5. Subscriber information and connection line-busy-free information,

6. Busy-free information for network routes,

7. Lists and series of works in the facility.

The control and maintenance systems for a memory of the type used here as the main processor data memory 103 are described in detail in the above-mentioned reference "Bell System Technical Journal" on page 2147 ff.

Auxiliary Processor Storage 172

The auxiliary processor memory 172 is a word-organized, high-capacity random access memory system in which the program for controlling the auxiliary processor 171 and the data with which the auxiliary processor 171 operates are stored.

The information, namely both the program and the data, are retrieved from the memory 172 by an auxiliary memory command from the auxiliary processor 171 , which specifies the position of the desired command word or data word. Correspondingly, information is written into the auxiliary processor memory 172 on the basis of an auxiliary memory command from the auxiliary processor 171 which specifies the storage location which is to contain the data and which is accompanied by the data to be written in the specified storage location.

A storage system suitable for use as auxiliary processor storage 172 is described in the above-cited reference "Bell System Technical Journal" on page 2147 ff. A detailed explanation is therefore not given here. Those functions of the memory 172 which are necessary for an understanding of the invention are, however, to be explained briefly in each case in the following part of the description.

The information stored in the auxiliary processor memory 172 includes

1. the program of command words which control the operation of the auxiliary processor 171 when it does not respond to memory commands from the main processor 101 ,

2. The data generated and used by auxiliary processor 171 in performing its programmed data processing operations.

The information stored in the auxiliary processor memory 172 is thus a mixture of command words and data words. The data stored in memory 172 includes

1. Information relating to service requirements, such as changes in the monitoring status, received via the auxiliary processor 171 from the switching network 120 and mixed management circuits of the switching system,

2. information relating to call connections received via auxiliary processor 171 from main processor 101 for processing by auxiliary processor 171 ;

3. Lists and series of works in the facility.

Auxiliary processor 171 (Fig. 3)

The auxiliary processor 171 is a stored program controlled special purpose data processor that performs selected data processing functions in accordance with instructions optionally read from a ferrite plate memory, referred to herein as the auxiliary processor memory 172. The auxiliary processor 171 leads

ίο those repetitive time consuming ingress and egress functions which, if performed by the main processor 101 , would limit the overall call handling capacity of the switch to a greater extent. The functions of the auxiliary processor 171 fall into three main classes:

1. The auxiliary processor 171 collects input information from sources outside the central processor 100 (ie, the input-output system 180) and processes and stores this state change information in selected areas of the auxiliary processor memory 172. The main processor 101 then reads out the stored information from the memory 172 by means of the auxiliary processor 171 and performs the remaining more complicated processing functions.

2. The auxiliary processor 171 performs those data processing operations which are necessary for the generation and transmission of output commands for external equipment of the plant (ie the input-output system 180) which operate more slowly than the central processor 100 or which have a special time control require. The data to be processed by the auxiliary processor 171 are entered by the main processor 101 via the auxiliary processor 171 into the auxiliary processor memory 172 or into selected registers within the auxiliary processor 171 itself.

3. The auxiliary processor 171 performs maintenance functions which quickly detect malfunctions arising in itself, and notifies the main processor 101 that malfunctions have occurred.

For explanation, the one shown in FIGS. 1 and 3 subdivide auxiliary processors 171 shown into four basic areas, namely a message transmission area 181, a control area 182, a ^ data processing area 184 and a

Maintenance area 183. The message transmission area 181 of the auxiliary processor 171 contains those circuits with the help of which information from the auxiliary processor 171 is received and sent out. It is connected to a large number of manifold systems 106, 173, 108, 104 and cables 109 , via which information is received and transmitted. It includes bus selection and transmission gates which select the particular bus within a bus system for receiving or broadcasting information, and a number of registers within auxiliary processor 171 that serve as an immediate source or destination for information sent or sent by auxiliary processor 171 be received.

The messaging area 181 contains

1. Message transmission gate circuits 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, the information and control signals optionally transmitted to auxiliary processor 171 from outside sources record and the optional information and control signals from the auxiliary processor 171 transferred to other components of the switching system,

2. Register 9CCAR, lOCCDR, 12ASR, 13/2 ?, 21Bi? and 2i.AR, which store control information received from either main processor 101 or auxiliary processor memory 172, or which serve as a source of information sent out by auxiliary processor 171.

The control area 182 of the auxiliary processor 171 comprises that part of the auxiliary processor 171 which djrekt responds to information received from the main processor 101 and received from the auxiliary processor memory to determine the type of from the auxiliary processor 171 to determine the required action and the corresponding sequential gate signals to perform the required operations.

The control area 182 generally includes

1. Decoding circuits 10 CCD and 13 / OD, which contain those in registers 9 CCAR and 13 //? decode information stored in communication area 181 and provide output signals defining the type of operation required by auxiliary processor 171,

2. a clock circuit 47 CLK, synchronized with the clock circuit 461 of the main processor 101, which controls two separate timing pulse trains, namely T-pulses and C-pulses (FIG. 5), for controlling the sequential gate operations within the auxiliary processor 171,

3. A multiplicity of sequential circuits 2 SEQ, which are advanced by the auxiliary processor 171 through a multiplicity of sequential states during the execution of main memory commands and various machine commands and which supply output signals which define the sequential progress of the auxiliary processor 171 in the execution of a specific sequence of prescribed operations and steer,

4. an instruction combination gate (OCG) circuit 42 OCG which combines the signals from the sequencing circuits 2 SEQ, the clock circuit 47CLK, the decoders 10 CCD and 13 / OD and other sources within the data processing and maintenance area 184 and 183 of the auxiliary processor 171, to generate the gate control signals indicating the sequential operations to be performed by auxiliary processor 171 in performing a particular operation,

5. a start-stop control 485S, the specific Operations of the auxiliary processor 171 based on control signals received from the main processor 101 are received or due to certain circuit states within the auxiliary processor 171 blocks itself,

6. An interrupt controller 49 / C, which transmits interrupt signals to the main processor 101 based on certain circuit states within the auxiliary processor 171.
5

The data processing area 184 of the auxiliary processor 171 includes a plurality of multi-stage flip-flop registers 19 QR, 20KR, 21BR, 21AR, 22JR, 22LR, 22XR, 23YR, 24PR and 25FR. In

ίο each of these registers can copy data from a hidden (masked) manifold be given 30 MB. From each of these registers, data can be fed to an uncovered (unmasked) bus line 30 UB.

The concealed bus line 30 MB and the uncovered bus line 30 E / B are connected to one another via the logical combination circuit 30 CBL. Information can be given from one register to another register via the uncovered bus 30 UB, the logical combination circuit 30 CBL and the hidden bus 30 MB. This information can go unchanged from the uncovered bus 30 UB via the logical combination circuit 30 CBL to the hidden bus 30MB, or it can be modified by logical operations that are carried out by the logical combination circuit 30 CBL in accordance with gate control signals that are stored in the OCG- Circuit 42 OCG are generated. In addition, the logical combination circuit 30 CBL can use the information on the uncovered bus 30 UB in combination with the contents of the registers 22Li? and 19 process QR logically. The content of the other two registers 13 IR and 12 RSR can be given to the uncovered collecting line 30 UB . However, information from the hidden bus 30MB cannot be entered into registers 13 IR and 12ASR.

The contents of any of the above-mentioned registers within the data processing area of the auxiliary processor 200 can be given directly either to the auxiliary processor memory 172 or to the main processor 101. In order to write the contents of a register into the memory 172, it must first be given to the uncovered bus line 30 UB and transferred to the concealed bus line 30 MB via the logical combination circuit 30 CBL. The concealed bus 30 MB is connected to the bus selection gates 209, via which data are transmitted to the auxiliary processor memory 172 with the aid of the auxiliary memory transmission system 173.

The data processing area 184 of the auxiliary processor 171 generally contains

1. a large number of multi-stage flip-flop registers 19QR, 20KR, 21BR, 21AR, 22JR, 12LR, 22, XR, 23Γ / ?, 24Pi? and 25Fi ?; some of these have certain independent data processing options,

2. a data processing bus system which has an uncovered bus 30 UB connected to the outputs of the multi-stage flip-flop registers specified above ^{, a concealed bus 30 1} MB connected to the inputs of the multi-stage flip-flop registers indicated above and a logical combination

23 24

30 CBL , which contains the unpublished and used information obtained from these

Covered bus line 30 UB with the covered onen for diagnosing fault conditions.

Manifold 30MB connects and logical

Modifications to the uncovered Sam- General call processing functions

Line 30 UB to the concealed collecting line 5

In general, the auxiliary processor 171 receives

3. supply a variety of indicator flip-flops 32SC2, input information from the Netzwerkabtastern, the outputs on which data encryption ™ ^s example, 123.127, 135 and 139, and based the processing decisions can main scanner 144 as a result of periodic power

lo work commands from auxiliary processor 171. These in-

4. A variety of special purpose data processing information is received via the scanner response and translator circuits 30 OD, 14 BSL, bus 108. The auxiliary processors 145SP, 14LCC, 205PM, 23ROD, 24NCT and 171 then process this input information, 25CPDT, the special data processing _{radio to} determine whether any action is being carried out. _{15 are} required. If this is the case, the

Auxiliary Processor 171 an advertisement in a particular

The maintenance area 183 of the auxiliary processor 171 storage location (funnel) of the auxiliary processor memory corresponds to the secondary status of the auxiliary processor 172 entered.

171. The primary function of the auxiliary processor 171, the main processor 101 commands periodically entbesteht is the "Real-TimeÄ-Verarbeitungsmög- ₂₀ speaking his from the main processor memory liabilities of the main processor 101 to increase. In 102 the program obtained by the auxiliary processor in this sense, the auxiliary processor 171 is a second 171, indicated memory locations of the auxiliary processor to read the data processing device with reference to memory 172, and the equipment of the auxiliary processor 171 is to be returned to the main processor 101 give on 25. During the execution of such a storage an independent display of errors and error commands will learn the entire data processing and a dependent diagnosis and correction will be directed to the auxiliary processor 171 apart from the errors indicated for the memory. In other words, the command required is paused until the store auxiliary processor 171 is configured to detect a save command executed by the main processor 101 - most of the errors or mistakes that result in FIG.

himself or in other components of the plant. The main processor 101 then determines

may occur with whom he is associated. Using his program and that from the However, if errors are found, the auxiliary main processor data memory 103 is retrieved processors 171 with regard to their evaluation, slide data the type of measure required and ergnose and correction entirely from the main processor 35 witnesses information defining the action. addicted. This information is then provided by the principal

The maintenance area 183 of the auxiliary processor 171 is transferred to worker 101 to the auxiliary processor 171 and generally contains of this stored in memory 172. Other un-

_Λ . _ΛΤ . ι ,, "j ". " _Π · ^ dependent data processing operations within the

™ L ί ti Ζ " ¹ S \ rT ^gS ^ rr ^P " Ä " ⁴ ° Auxiliary processors 171 are stopped again, ISS?« ^M £ ' \ £ L · ™? £' ™ ^CSC > until the 37 SPE AQCSE and 26CPDM, which ends the comparable _{arbeiterl01 verlang} \ _s operation. different ways of working and Transfer- _{the HiIfsverarbeiter m then uses his EIGE}

types of Hüfsverarbeiters control 171 and _the arrival _{aug Speicherl72} obtained program to show for eventual mistakes and errors detected ₄₅ ^s received _{from the} main processor 101 infor mation 'to be processed and the required input

2. Parity generators UPG to generate the parity calculation output commands, which supply to and displays for an even or non-execution of the required measure through even parity, which are used to check information elements of the input-output system 180 are used by the auxiliary processor 171 50 ren. The main processor 101 thus white sent or received, then the more complicated data processing operations.

3! ^{a display circuit} for kinetic address tionen> while the auxiliary processors 171 the more with a flip-flop register 12C ^ i? and performs routine operations, such as example comparison circuit 12CAM to determine ^w ? ^is the scan control, the control of the conditions under which both the auxiliary network, the time control of the plant processors 171 and the main processors and elementary data processing operations. 101 are busy with data that have the same number of separate sequential data

Storage location within the auxiliary processors storage processing operations of both the auxiliary processors 172 are stored. ^{171 as audl of the} main processor 101 is required

60 borrowed in order to meet all

The main processor 101 enters into the task of performing maintenance control operations. Man area 183 of the auxiliary processor 171 with the help of the eighth that not a single operator mentioned above Main memory commands in progress or telephone connection complete binding that cause the auxiliary processor 171 to be processed before the processing of other specified Register in itself information integration begins. Every data processing step ascribing or reading from these. This is a different way of operating with other similar steps the main processor 101 controls the status of requests or telephone calls of the various maintenance register flip-flop group mixed. Furthermore, any similar data transfer will

25 26

Processing step for several connections ended, transferred to auxiliary processor 171 and vice versa before the next step is started. signals are given. Storage _{commands Λτ} , ..,, ",. .. are transferred from the main _{processor 101 to the auxiliary processing maintenance transfers and synchronization ter m with} the auxiliary / _a bus system _{within the intermediate main processor 101 and the} main memory transfer system 106 to the auxiliary processor 171. The responses to this memory com-As already explained, the invention has the commands from the auxiliary processor 171 to main increase the data processing capacity of a center processor 101 via a separate bus terminal processor 100 by the inclusion of a system within the main memory transfer auxiliary processor 171 Target. The main processor io systems 106 transferred. Since the auxiliary processor 171 101 can take all necessary measures for an automatically interrupting (ie stopping) its operation, communication switching system. He has explained how to process storage commands, but there is often a need for larger data processing capacity 15 to interrupt their cases. To be taken under certain conditions. The basic data processing conditions, mainly fault interpretation of the main processor 101, are not required, but the main processor 101 must change when an auxiliary processor 171 is able to start the operation of the auxiliary processor 100 in the central processor . It must always be able to stop temporarily. Since, in addition, the one communication link between the auxiliary processor 171 with regard to the fault diagnosis of the main processor 101 and the auxiliary processor 171 is completely dependent on the main processor 101 and since the auxiliary processor 171 must display the main processor 101 to the main processor 101 from time to time, that the auxiliary processor- _H c. ,,, _TT, ■ 1 "- memory 172 has no Pufferspeicherlcapazität,

1. Storage commands from the main processor ΙΟΙ there _{is a need for} transmission from subprocessor to auxiliary processor 171, which correspond to the memory break signals from auxiliary processor 171 to commands for memory 103; Main processor ΙΟΙ. Continue to have to from time to time

2. Normal answers from auxiliary processor 171 time of auxiliary processor 171 to main processor to main processor 101; 101 give notice that he is certain

3. Interrupt signals, namely both malfunction functions terminated and urgent information for as well as normal interrupt signals that main processor 101 has. In this last of the Auxiliary processor 171 for the main processing case, auxiliary processor 171 arranges the EinterlOl; position of a certain flip-flop in the main processing

4. Timing synchronization signals from the beiterlOl. When this flip-flop is set, is Main processor 101 to auxiliary processor 171; 35 there is an indication that the principal

5. Interruption signal (stop signals) from the main worker 101 to a specific memory location in the auxiliary processor 101 to auxiliary processor 171. processor memory 172 is to be read.

According to FIG. 9 merged F i g. 6 and 7 operation timing in auxiliary processor 171

schematically show part of the circuits shown in FIG

Main processor 101 and in auxiliary processor 171 The auxiliary processor 171 is a synchronous system,

are provided to ensure the transmission of certain, since all functions in it under control of a lot of the above-mentioned information between the main phase microsecond clock circuit 47 CLK processor 101 and the auxiliary processor 171 to exist, the timing signals act as the basis for. The main processor 101 is equipped with a 45, all sequential logic functions within the 2-MHz clock oscillator 461 B. This auxiliary processor 171 delivers. The clock oscillator timing signals are applied to the microsecond clock from the clock circuit AlCLK through the circuit 461, to which it is connected via the line 6107 to OCG circuit 42 OCG with signals from one. In addition, is the output of the 2 MHz number from other sources within the auxiliary clock oscillator 4612? Combined in the main processor 101 over 50 workers 171 and serve as a temporal connection to the wire 2MC of the cable 213 with the auxiliary processing basis for the generation of gate control signaling 171. The signals on the wire 2MC len through the OCG circuit 42 OCG.
correspond to that at any given point in time. The microsecond clock circuit 47CLK is in

Output signal of the clock oscillator 461 B shown in the main Fig. 7 as a simplified block diagram, processor 101. This 2 MHz signal represents a syn- 55 It contains a counting circuit 4701, which is used by the chronization stage for the timing of 2 MHz square wave is acted upon by the operations in auxiliary processor 171. Main processor 101 via wire 2MC of the cable

A second stage of timing synchronization 213 comes. The 2 MHz square wave is accompanied by a phase signal (phasing signal) by means of the output signal, the microsecond clock circuit 461 on wire 60 via wire TSYNC of cable 213 from the main TSYNC . This phase control signal on processor 101 is received. The phase signal of the TSYNC wire occurs at the beginning of each machine, causing the clock cycle of the main processor 101 to be synchronized. As a result, 461A turns on in main processor 101 and the signal appears once every 5.5 microseconds. Clock circuit 47 CLK in auxiliary processor 171. The wire TSYNC is also connected via cable 213 65 synchronization signal on wire TSYNC to auxiliary processor 171. Receive and. Intervals of 5.5 microseconds

Before explaining the FIG. 6 and 7, one shall be used to reset the counting circuit 4701. Summary of the data provided by the main processor 101. As a result, the counting circuit 4701 is in its phase

27 28

The derivation of the time control worker 101 was matched exactly to the clock circuit 461 in the main generator 4703. Signals in the pulse group T resume from the positions of the counting circuit 4701. However, since the signals in the pulse group C derived clock pulses are still supplied by the pulse generator 4702 through two pulse generators 4702 and 4703 into two groups, the auxiliary processor 171 can be converted to main memory. A pulse group is derived from the pulse commands from the main processor 101 address generator 4703 and designated as a “T” pulse group and certain critical maintenance operations. The other impulse group will lead through the.

Pulse generator 4702 derived and used as a "C" pulse stop of auxiliary processor 171

group called. The main difference between io

These pulse groups C and T consists in the start-stop control 48 SS responding to

the formation of pulses in the pulse group T knows combinations of circuit conditions can be halted without influencing the formation of pulses in the pulse group C within the auxiliary processor 171 and on certain pulse group C. This halting of signals from the main processor 101 to through is effected by a signal from the start-stop control 15 blocking the pulse generator 4703 to the auxiliary circuit 4855 on the wire 48 PLC . A signal on worker 171 to cause his independent operator to temporarily sew on wire 48 PLC controls the pulse generator 4703. The conditions in such a way that the formation of the pulse group T is stopped without those of the auxiliary processors 171, who-influencing the pulse group C generated by the pulse generator 4702 is derived from a number of sources, the pulse group C is blocked. If the formation of the 20 is mainly blocked in the maintenance area 183 of the auxiliary pulse group T in this way, the processor 171 will be located. These sources include auxiliary processors 171 as suspended indications for errors sensitive to the message traffic. This stoppage has been detected without interruption between the auxiliary processor 171 and other interruptions of the operation of the counter circuit 4701 cut through the switching system, since such a disturbance is both pulse groups T 25, as well as for errors that would affect data processing and C. operations by the auxiliary processor 171 were determined, and errors that occurred in the generation of worker 171, which in this embodiment of clock pulses by the clock circuit 47 CLK, 5.5 microseconds, is in 22 time intervals of Main memory command ^{information divided by 1} A microseconds in length, which have resulted in 30 main processors 101 and program instructions labeled 0Γ1 to 21Γ0 and OCl to 21C0 from auxiliary processor memory 172. The clock pulses generated by the pulse generators 4703 and 4702 the start-stop controller 4855 are shown in FIG. For the conditions specified above during the relief, time segments with "bTe" and the catch segment of a machine cycle are excited. The "bCe" denotes, where b is the the time züge- 35 OCG circuit 42 OCG switches the start-stop Related number, at which the time period begins, controller 4855 is automatically during the last and e associated with the time number to portion every machine cycle. So it will be the end of the period. For example, defined makes a clock pulse signal of the import, 171 to start the auxiliary processor again during each machine cycle, the test geder Expression 8 Γ10, pulse group T, which at the beginning of the eighth programmable time 40 The pulse generator 4703 is so constructed as to Valls with ¹ U microseconds of the machine cycle of automatically timing signals begins in the pulse 5.5 microseconds and returns at the beginning of the group T , starting with the tenth time interval with ¹ U microseconds of the pulse 2Γ4 of the machine cycle that ends that machine cycle. Correspondingly, this defines the following, in which the start / stop control 4855 ab-expression 8C10 a signal of the pulse group C, which has been switched 45. At the beginning of the eighth time interval with ¹ AsMiIoO- 171, the auxiliary processor will begin his independent operation with the clock second of the machine cycle and at the impulse 2 Γ 4 of the next machine cycle will resume the tenth time interval with ¹ U microseconds, if not the condition which ends at Erredes machine cycle. the start-stop control 4855 led,

As stated above, the timing 50 will continue to exist or will be re-established, pulses from the clock circuit 47 CLK of the If, as will be described later,

OCG circuit 42 OCG is used as a time base for the generation of an input signal from decoder 10 CCD of the generation of all gate control signals which all OCG circuit 42 OCG indicates that a main rations of auxiliary processor 171 are controlling. The memory command signals from the main processor 101 to the pulse group T are generally captured for the derivation 55, for which the auxiliary processor 171 has internal gate signals to control the independent process, so the OCG transmits programmed operations of the auxiliary processing circuit 42 OCG Signal to start-stop control 171 used. The signals in the pulse group C tion 4855 via a wire of the command cable 4209. are generally used to derive gate signals.This signal excites the start-stop control 4855, which transmits messages between 60, which then sends a signal to wire 48 PLC , that prevents the auxiliary processor 171 and the main processor from generating clock pulses T by the pulse, as well as the execution of the main memory generator 4703 for the next following machine command of the main processor 101 by the auxiliary cycle.

Processor 171 and other critical operations with If during transfer between the

Relation to the maintenance of the plant and the error 65 auxiliary processors 171 and the main processor 101, control display. So if the derivation of the impulse to the switching network 120 or the central group Γ is blocked, the auxiliary processor 171 holds impulse distributor 143 errors are detected its independent operations until the impulse error indications in the maintenance registers of the

29 30

processing area 183 of the auxiliary processor 171 provides control signals from the OCG circuit 42 OCG, which. These fault indications will cause the interrupt controller 49 / C to be energized.
Start-stop control 4855 energized and the derivation If errors in traffic between the auxiliary

stopped by pulses in pulse group T processor 171 and the auxiliary processor memory will. 5 172, the central pulse distributor 143 or the

A direct connection for stopping the auxiliary switching network 120 is established between the main processor, the information on these errors from registers in 101 and the auxiliary processor 171 in the form of the wire maintenance area 183 of the auxiliary processor 171 from the STOPSP of the cable 213. The main store. This information means that the sub-worker 101 can over this connection a sequence io break control 49 / C on the wire 50 SSPT of the pulses to the auxiliary processor 171, cable 5000 transmits an emergency interrupt signal to the intervals of which the main processor 101 transmits a machine cycle. Also, will be, (5.5 microseconds). These pulses are received by the auxiliary processor 171 near the end of the comparison operation when a critical operation to be described below is received by the auxiliary processor 171 through each machine cycle. They are passed to 15 and this comparison operation applies the start-stop control 4855 and makes it necessary to act on an emergency interrupt signal, so that the generation of pulses T on wire 50 SSPT to main processor 101 is halted. As explained above, the start-stop will give. In addition to the signal on wire control 4855 automatically during the last SOSSPT , the interrupt control transmits part of each machine cycle shutdown. The Si 20 49 / C a synchronization signal on the wire signals from the main processor 101 are in the Ma- SOSPSYN of the cable 5000. This signal excites the machine cycle after the automatic shutdown AND gate 7103 in the main processor 101, so that the start-stop control 4855 received. As long as the accompanying signal on wire 50 SSPT hfilts the pulse sequence from main processor 101 to set flip-flop SPOT in main processor 101, auxiliary processor 171 remains paused. 35 can. The SPOT flip-flop in the main processor 101 The auxiliary processor memory 172 contains one of several flip-flops, the limited storage capacity set, which is used by the auxiliary processor status in the main processor 101, a sub-171 as a buffer memory. This includes initiating a level F break program sequence,
the "funnels" mentioned above. As already explained, the auxiliary processor depends on the implementation

In addition to the input-output functions, the 30 171 provides information in the auxiliary diagnosis and the initiation of remedial worker memory 172 with regard to a detailed malfunction auxiliary processor 171, and then it reads the data completely from the main processor 101. The main processor 101 monitors this information from the auxiliary processor 171 from its internal BeSpeicher 172 and, as a function of this, carries out the operation and operation of other complicated logical processes assigned to it. For the 35. If the entire buffer memory in the auxiliary processing 50 SSPT is used as a fault indicator for the main worker memory 172 is filled, the auxiliary processor 101 can and allows this an interrupt processor 171 to execute further input program sequences of the stage Introduce F. As in Fig. 8 functions not continue until the main processor 101, a fixed processor 101 executes the command failure entered in the buffer memory or the information has been taken from the main processor 101. Since the entry last of a protected area (a special exit work with a high temporal area in the memory) must be carried out precisely within the main processor, a fully 101 itself would also interrupt the operation of the permanently filled buffer memory Stage F. Main processor 101 undertakes interrupt at auxiliary processor 171. Therefore, 45 of the detection of an interrupt signal that is encountered when a full buffer memory is encountered, step F. The main processor 101 undertakes a certain program command from the auxiliary processor to determine the state of the auxiliary processor 171, which employs the auxiliary processor 171 and executes , if necessary, has remedial measures taken and the transfer of a subordinate.

50 As described above, when the buffer is empty. During the execution of this program memory capacity of the auxiliary processor memory 172 commands, the OCG circuit 42 OCG gives a signal that is exhausted, the auxiliary processor 171 to the main sales one wire of the command cable 4209, which the start worker 101 with the help of an interrupt signal stop control 4855 excited and the auxiliary processing knowledge that his intervention is urgently stopped. The generation of the under- 55 is required. When the capacity of the buffer refraction signal is described below. Memory in the auxiliary processor memory 172 is exhausted _{TT,,, T} τ,. _ΛΜ , there is a jump to a specific Ma interruption of the main processor 101 machine command of the program information stored in the auxiliary processor memory 172 by the auxiliary processor 171. The execution The interrupt controller 49 / C responds to this command, causes the OCG circuit to know detected error and error displays and 42 OCG to transmit an excitation signal to certain programmed operations and via a wire of the command cable 4209 to subordinate and transmits interrupt signals to interrupt controller 49 IC. The interrupt control main processor 101 via the cables 5000 and 213. tion 49 / C then transmits an interrupt signal. The fault and error indications found are transmitted to the main 65 via the wire 5055ΡΛΙ of the cable 5000 in general from the maintenance registers in the processor 101 from maintenance area 183 of auxiliary processor 171 supplies a synchronization signal on wire SPSYN. The programmed operations lead to the cable 5000 accompanied. The synchronization

31 32

signal excites the AND gate 7102, so that the Si worker program memory 102 stored input on the wire 50 SSPA the flip-flop & Ρ £ λ4 in the direction information.

Main processor 101 can hire. If the If a communications switch whose

Flip-flop SPOA is set, the main processing center processor 100 initiates an auxiliary processor 171 worker 101 an interrupt program on which 5 is started up for the first time, stage K. the main processor 101 writes with the help of the

As already explained, an interruption of the auxiliary processor 171 the auxiliary processor program level K is the lowest interruption level of the interrupt priority shown in information in the auxiliary processor memory 172 FIG. It is a. If there is a serious malfunction in the auxiliary processor 101 operation of the main processor memory 172, there is only one interruption if there is currently a possibility that the auxiliary processor program will not be affected by an interrupt function of a higher level of information. Stage executes. In this case, the main processor 101 brings the break of stage K , the main processor takes information in the auxiliary processor memory 172 101 the necessary measures for removal 15 again, so that this the correct auxiliary association of a part of the information from the Buffer memory contains worker information, in auxiliary processor memory 172. as already with reference to the start-stop control

As part of the independent program sequence of the 48SS , the main processor auxiliary processor 171 can execute an instruction 101 when executing a program sequence that when the auxiliary processor 171 executes a certain work function and an urgent message temporarily pauses. When the main processor 101 has given in a predetermined one for the main processor 101 directly to an element of the switching network storage location of the auxiliary processor memory 172 or to the central impulse distributor. If this command is carried out, 143 _m connection must be made, the auxiliary energized the OCG circuit 42 OCG the sub-workers 171 must be stopped in order to generate interruption control 49 / C with the aid of a signal from interfering network or CPD commands one wire of the command cable 4209. This signal helps him to avoid. This stopping of the auxiliary has the effect that the interrupt controller 49 / C becomes a processor 171 with the aid of the above-explained synchronization signal on the SOPSYN wire, the signals on the STOPSP wire of the cable 5050 beKabels 5000 and an interrupt signal on the 30 acts. The signals are generated once during each wire 50 SSPB of the cable 5000 to the main processor machine cycle as long as the main 101 is transmitting. By the synchronization signal on processor 101 successive commands for the wire 50APSYiV the AND gate 7101 er elements of the input-output system 180 is energized, so that the flip-flop SPOB in the main _{processor testifies} , such as for the switching network-101 by the signal on the SOSSPB wire 35 factory 120 and the central impulse distributor 143. can be set. The main processor 101 D asks _he can main processor 101 every two machine

corresponding to its own progeny obtained from the main internal cycle of an input / output command create worker program memory 102. The auxiliary processor 171 regularly requires three meshes from the flip-flop SPOB. Therefore, if the auxiliary processor 171 is currently fetching an input memory 172 with only a small delay, the urgent message is sent from the auxiliary processor to generate such a command. Generates output command, he runs this Opera - ",,,.,. , j _DD . ... tion through to the end, although a stop signal

Interactions between Master Processor Master Processor 101 has been received.

101 and the auxiliary processor 171 _{of the hoof} £ _{erarbeiter m holds} d ^ _{ar run} ⁸ _on the G

Generally speaking, the foregoing stop signal from main processor 101 concerned its description the interconnections between ren independent processing operations on, however the main processor 101 and the auxiliary processor he ends the started generation of the input 171, those for synchronizing the auxiliary processor output commands.

are required with the main processor 101 As already described, the micro-

and which give the auxiliary processor 171 the possibility of 5 ° second clock circuit 47 CLK in the auxiliary processor, to alert the main processor 101 to such states 171 two groups of timing pulses T within the auxiliary processor 171 and C provided. The timing signals that deserve urgent attention by the pulse group T will be in the execution of the er main processor 101. As explained above, the first machine cycle of the sequence of three machines need both the main processor 101 and 55 cycles used by the auxiliary processor 171 to give the auxiliary processor 171 access to the auxiliary generation of an input-output command processor memory 172, both to the Needed. The clock pulses in pulse group C are read as well as for writing. This means that both the main processor 101 during the second and third machine cycles and the auxiliary processing of the three processors 171 for generating such a command work with data that uses the cycles required in the auxiliary processor 60. So if a stop memory 172 are stored. In addition, the signal in the auxiliary processor 171 from the main processor requires the main processor 101, if a message 101 is received before the first machine cycle switching system is set up and, based on an operation to generate a command, the possibility of correct maintenance conditions has begun, this will be executed Operation auxiliary processor program information in Fig. 65 suspended by auxiliary processor 101. However, if the auxiliary processor memory 172 can be written in, the stop signal during the first or second manen. The program information for the auxiliary machine cycle of the sequence of three cycles received worker 171 comprises a part that is in the main process, if the operation for generating the grain

33 34

mandos is terminated before the auxiliary service is stopped.

worker 171 takes effect. worker 101 can indicate that the auxiliary processor

171 accompanying the main memory command

Main memory commands data in a specified register in the auxiliary processor

for the auxiliary processor 171 5 171 should register himself. In this case it will be

the data accompanying the main memory command

As already mentioned, the auxiliary processor 171 is received from the transmission system 106 via the collective with the main processor 101 via the same line gate circuit 203 and connected in the re-transmission system 106 which stores the main register 10 CCDR . This register is connected to the main server via processor data memory 103, which connects the buffer bus line 10 BB with various processors 101. Accordingly, the auxiliary circuitry within the auxiliary processor 171 is processor 171 from the main processor 101 to the bound. The information in the buffer group is addressed in the same way as the various storage lines 10 BB can with the aid of the logical combi-memory that form the main processor data memory 103 national circuit 30 CBL on the concealed group. Each from the main processor 101 via the _i5 line 30 MB will be given. Consequently, the transmission system 106 sent out main memory information on the buffer bus 10 BB command is received by the auxiliary processor 171 via the each register in the data processing area 184 of the bus gate circuit 201 and supplied to auxiliary processor 171, to which the CCAR stored in register 9. The contents of the reverse manifold has 30MB access. Extra register 9 CC AR is decoded by the decoder 10 CCD _ao dem can decode the information on the buffer group in order to determine which type of operation line 10 BB signals directly through the corresponding gattertion, if at all, from the auxiliary processor 171 each of the maintenance register flip-flop Groups is requested by the main processor 101. When address information is passed to the main memory command in the maintenance area 183 of the auxiliary processor 171. In this way, the master can define the auxiliary processor 171, processor 101 provides operational data or instructions to the decoder 10 CCD input via the input to the data processing area 184 and ECG cable 4600 to the OCG circuit 42 OCG. This can also control the status of the flip-flop groups, this signal defines the type of the auxiliary processor in the maintenance area 183. 171 required surgery. One of the Folgeschaltun- A main memory command from Hauptverargen 2SEQ is then passed through a signal from the OCG- _30-workers 101 may indicate that the auxiliary processor circuit started 42 OCG, and there are certain 171 a particular memory location in the auxiliary processor independent internal operations of the Hilfsverarbei- memory 172 reads and the information obtained in this way getersl71 by the start / stop control 48 AS is locked to the main processor 101. The OCG circuit 42 OCG combines time returns. In this case, the main memory control signals in the pulse train C of the clock ₃₅ includes command from the main processor 101 Adresseninforschaltung 47 CLK with input signals of subsequent mation that define a memory location in the auxiliary processor circuits 2 SEQ, from the decoder 10 CCD and memory 172nd This address information to other circuits within the auxiliary processor is transmitted via an access circuit UCMA and the 171 to generate the corresponding gate signals on the bus gate circuit 204 to the auxiliary processor command cable 4209. These signals control ₄₀ worker-memory 172 by means of the Übertragungsdie execution of the command supplied to the memory from the system 173rd The address information main processor 101 required operation. When other auxiliary memory command information is sent to the operation, the start-stop control 48 SS stops the information that specifies the action to be carried out by the auxiliary processor-dependent operating mode of the auxiliary processor 171 memory 172, and the ₄₅ The memory 172 reads the information from the abnormal operations continue. As already explained, the auxiliary processor 171 can return this memory location to the auxiliary processor 171, on main memory commands from the main processor Address main memory commands. A ₅₀ gate circuit 210 received and in the main memory command register can indicate that the 10 CCDR is stored. Its content is then managed by auxiliary processor 171 to read the information stored in a specified transmitter from the buffer bus line 10 BB via the collective registers line gate circuit 202 and is to be transmitted to the main processor 101 with the help of and. In the transmission system 106 to the main processor in this case, the content of the specified Re- ₅₅ 101 is transmitted.

gisters to the uncovered collecting line 30 UB and the main storage command from the main processing

from there to register 10 CCDR . The informer 101 can indicate that the auxiliary processor mation in the register 10 CCDR is then via the 171 the data sent out by the main processor 101 accompanied by the buffer bus line 10 BB and via the collecting main memory commands in the line gate circuit 202 and with the help of the transfer 60 writes a specified memory location in auxiliary processing transmission system 106 to main processor 101 via memory 172. In this case it will wear. In this way, the main processor can determine address information defining the storage location in the auxiliary 101 the content of each register within the auxiliary processor memory 172 from the transfer processor 171, which covers access to the unsystem 106 via the bus gate circuit 30 UB Has. These registers received 65 201 and stored in register 9 CCAR , stern include those in data processing Gate circuit 203

35 36

received and stored in register 10 CCDR. The address information which the memory location in the circuit 42 OCG which defines the machine auxiliary processor memory 172 is identified by command, which is stored in an auxiliary memory com by the command word in the auxiliary processor 171 - Register 13 IR is defined. Due to periodic mando inserted and then to the auxiliary processor 5 timing pulses, which are transmitted by the clock circuit memory 172 in the same way as received 47 CLK , the input signals received from the decoder above for the read operation at the auxiliary processor 13 / OD and others ter memory has been written to. The data stored in the register input information that indicates the presence of 10 CCDRs are given via the Sam intermediate steps in the execution of the multi-line gate circuit 209 and together specify the machine command, causes the OCG circuits with the address information via the transmission 42 OCG that one of the sequential circuits 2 SEQ transmission system 173 is transmitted to the memory 172. The successively the states of an internal sequence in memory 172 then responds to the auxiliary memory. The status of the sequential circuits 2 SEQ command and writes the data that accompanies the command in connection with periodic pulses from the data into the memory location specified in the auxiliary memory command in the clock circuit 47 CLK and the memory location given by the decoder. 13 / OD and other sources within the auxiliary

processor 171 signals delivered by the OCG

Auxiliary memory commands for circuit 42 OCG for generating gate control

Auxiliary processing memory 72 ^ Sf "AS signals are transmitted via the

^F 20 command cable 4209 transmit and control the logi-

A single command word received by the auxiliary ^processing operations of auxiliary processing 171 from auxiliary processing memory 172 during 171 of ^{the one or} more machine cycles which control the logical operations required by auxiliary execution of the machine instruction, processing 171 sequentially with reference to either Immediately before the execution of each Maschiein single data word or nenbefehls terminated on a group of ^DA-2 and 5 are carried out as part of execution tenworten. The auxiliary processor of this machine command will be the next instruction memory 172 represents a memory for both the word of the corresponding program sequence from the program instructions and for data that are generated and used by the auxiliary processor memory 172 with the aid of a storage auxiliary processor 171. Read the reading commands from the auxiliary processor 171 from the information stored in the auxiliary processor memory 172. This ensures the continuity of the independent animations are a mixture of instructions and programmed operations of the auxiliary processing and data words. beiter 171 ensured.

Instruction words from that stored in memory 172. When executing a machine instruction stored program and in the memory 172 the auxiliary processor 171 is information in a stored The auxiliary processor wins data words 35 correct storage location of the auxiliary processor memory

171 is to write in with the help of auxiliary processor memory read 172, an auxiliary processor command. These commands are generated with the memory write command. The address execution of the various machine instructions in the information that defines the memory location is generated in the program of the auxiliary processor 171. Address data to be written is derived from the same sensor information as the memory location in the memory 4 ° sources as in the case described above

172, from which a command word or an auxiliary processor read command is to be taken, and if the data word is to be taken, are transmitted via the transmission system 173 to the memory 172 depending on the specific, currently executed. The machine instructions to be written into the memory 172 in one of the registers 21 ^ 42 ?, 21BR, the data are from the hidden collection or 12,4Si? saved. The content of the corresponding 45 line 30 MB via the bus gate switch register is conducted via the access circuit 209 and via the transmission system 173 to the UCMA and transmitted as part of the auxiliary storage auxiliary processor memory 172. These commands via the bus gate circuit formation can originate from any source within the auxiliary service 204 and via the transmission system 173 to the processor 171, which transmit access to the uncovered auxiliary processor memory 172. 5 <> th collecting line 30 UB, for logical combination

On the basis of a memory read command from the control circuit 30 CBL or to the concealed collective auxiliary processor 171, the memory 172 reads the line 30 MB . The respective source from which the memory location, which is obtained from the data in the command, depends on the address contained in it is then identified. This word carried out machine commands. Due to the auxiliary, it is transferred to auxiliary processor 171 and, if 55 processor memory commands are written the store is the first command word of the machine command, rather 172 the data accompanying the command is entered simultaneously in the command register 13 IR and the memory location indicated by the im Komd entered data register 21BR. If the command contains address information specified machine command contains more than one command word,
the following command words due to 6 °

additional memory read commands only in the data comparison of critical addresses

register 21BR entered.

The first command word is generated by the decoder. As stated above, there is a possibility

13 IOD for commands and additional, optional mutual interference between the auxiliary processing failures is decoded in order to identify the special worker 171 and the main processor 101 on the basis of the machine command given by the fact that both have access at any given time in the command register 13 IR have the same memory, namely the auxiliary processor is defined information available. The signals memory 172. To view the content of any memory

place in the memory 172, either the secondary processor 171 or the main processor 101 read the information in this memory location, then change the information and finally the return changed information to the same memory location. If happened to both the auxiliary processor 171 and the main processor 101 are working simultaneously with the same memory location, so will that processor who returns as the last information ap the memory location that was provided by the other Destroy the modification made by the processor. This can create uncomfortable confusion occur that lead to serious malfunctions.

About the occurrence of this interaction between the secondary processor 171 and the main processor 101, a backup called a "critical comparison" is provided in the auxiliary processor 171. This safeguard prevents the main processor 101 from writing information into a memory location from which the auxiliary processor 171 has obtained data that it is currently processing.

As part of the execution of each machine instruction in the program of the auxiliary processor 171 is an indication stipulates whether a critical comparison should be carried out or not. Generally speaking this measure is only taken if the auxiliary processor 171 is currently data from a critical Storage location in the auxiliary processor memory 172 can be obtained. Every time the auxiliary processor

171 communicates with the memory 172, the address part of the auxiliary memory command transmitted from the auxiliary processor 171 to the memory 172 is entered into the register 12 ASR . The register 12ASR always contains the last one, to the memory

172 transmitted address information. It can now be ₃ j prevents the main processor 101 writes information into that memory location of the memory 172, which is defined by the information stored in register 12 CAR address information.

As described above, the main processor 101 causes information to be written into the auxiliary processor memory 172 by transmitting main memory commands which are encoded to identify the auxiliary processor 171 and also the location in the memory 172 in which the information is to be written. The main memory command is received and stored in register 9 CCAR. That part of the main memory command which defines the address in the auxiliary processor memory 172 is transmitted to the comparison device 12CAM for critical addresses. The comparison device 12CAM compares the critical address information previously stored in the register 12CAR with the address information of the main memory commands received and stored in the register 9 CCAR. If the address information in both registers 12CAR and 9 CCAR match, the comparison device X2CAM supplies an output signal. Otherwise, no output signal is generated.

The maintenance area 183 of the auxiliary processor 171 contains a circuit 335Cl which indicates whether the information processed by the auxiliary processor 171 at a certain point in time originates from a critical address. If this is the case and an output signal is detected by the comparison device 12CAM , further operations in the auxiliary processor 171 which are required for generating an auxiliary memory command on the basis of the main memory command are blocked. So no data is transferred from auxiliary processor 171 to auxiliary processor memory 172. In addition, as already described, the interrupt controller 49 / C causes the transmission of an interrupt signal on the wire SO SSPT to the main processor 101 if a critical comparison is positive. Consequently, the memory location from which the data currently being processed by the auxiliary processor 171 originate remains undisturbed by transmissions from the main processor 101 until the processing of this data by the auxiliary processor 171 has been completed and a new address has been entered in the register 12CAR .

Claims (22)

Patent claims: 1. Data processing arrangement with a main processor, with a memory that contains data with which the main processor works, with a memory bus system which, with the aid of optionally encoded memory read and memory write commands generated by the main processor, give the main processor an optional read and write access to the memory, with an input-output system that supplies input information for the main processor and executes input-output commands generated by the main processor, and with an input-output busbar system for transmitting the input information and input-output commands from the input -Output system to the main processor, and vice versa, characterized in that the arrangement has an auxiliary processor (171) controlled by a stored program, which is connected to the memory bus system (106), and also an auxiliary memory (172), the programs for tax ung of the auxiliary processor (171) and data with which both the auxiliary processor and the main processor (101) work, and an auxiliary storage manifold system (173), which with the aid of the auxiliary processor (171) generated optionally encoded auxiliary memory read and Auxiliary memory write commands allow the auxiliary processor (171) optional read and write access to the auxiliary memory (172), and that the auxiliary processor (171) has an access control arrangement (e.g. B. 9CCAR, lOCCDR, WCCD, 42OCG, 2SEQ, WCMA) , which responds to certain of the memory read and memory write commands to the main processor (101) with the help of the auxiliary memory read and auxiliary memory write commands and the auxiliary memory bus system (173) the main processor (101) - To enable write access to the auxiliary memory (172). 2. Data processing arrangement according to claim 1, characterized in that the auxiliary processor (171) has a plurality of registers (e.g. 21BR, 19QR, 325C2) and that the access control arrangement (e.g. 9 CC AR, 10 CCDR, 10 CCD, 42 OCG , 2 SEQ) responds to other of the memory read and write commands to enable optional read and write to enable access to the corresponding registers ( e.g. 21BR, 19QR, 32 SC 2). 3. Data processing arrangement according to claim 1, characterized in that the auxiliary processor (171) is coupled to the input-output busbar system (175) and thus the input information from the input-output system (180) receives that the auxiliary processor (171) input-output commands generated on the basis of certain data contained in the auxiliary memory (172), and that the generated input-output commands via the input-output bus system (175) are transmitted to the input-output system (180). 4. Data processing arrangement according to claim 3, characterized in that the auxiliary processor (171) Input-output service requirements from the input-output system (180) supplied input information and in the auxiliary memory (172) contained data determined and generate the service request data defining each service request, that the main processor (101) using the service request data and im Memory (103) contained data with reference to the state of the system in action and Generates data that define the necessary measures in the plant, and that the specific ones Data in the auxiliary memory (172), the data generated by the main processor (101) with reference to the necessary measures in the system. 5. Data processing arrangement according to claim 1, characterized in that each of the specific memory write commands is coded so that it specifies the auxiliary processor (171), a memory location in the auxiliary memory (172) and data to be written into the memory location, and that the access control arrangement (e.g. 9 CCAR, IQCCDR, 10 CCD, 42 OCG, 2SEQ, UCMA) in the auxiliary processor (171) responds to each of the specific memory write commands and generates a corresponding auxiliary memory write command which is coded in such a way that the memory location in the auxiliary memory (172) and the in specifies this data to be written. 6. Data processing arrangement according to claim 5, characterized in that the auxiliary processor (171) has a display arrangement for critical addresses (12CAM, 12CAR, 12 ASR, CCAR) for displaying a critical address status, which consists in that at the moment from the auxiliary processor (171) processed data have been read from the auxiliary memory (172) at a memory location which is indicated by a received command of the specific memory write commands. 7. Data processing arrangement according to claim 6, characterized in that the auxiliary processor (171) has a blocking arrangement (48 ÄS) which is controlled by the display arrangement for critical addresses (e.g. HCAR, 12CAM, ASR, 9 CCAR) and prevents that the access control arrangement (for example 9CCAR, IQCCDR, IQCCD, 42OCG, 2SEQ, UCMA) of the auxiliary processor (171) generates the corresponding buffer memory write commands. 8. Data processing arrangement according to claim 7, characterized in that the auxiliary processor (171) contains one of the display arrangement for critical addresses (12CAR, 12CAM, 12ASR, 9 CCAR) controlled interrupt control arrangement (49 / C), which an interrupt signal (eg SSPT) to Main processor (101) transfers. 9. Data processing arrangement according to claim 1, characterized in that each of the specific memory read commands is coded so that it indicates the auxiliary processor (171) and a storage location in the auxiliary memory (172), and that the access control arrangement (e.g. 9 CCAR, IQCCD, 42 OCG, 2SEQ, IICMA) of the auxiliary processor (171) responds to each of the specific memory read commands and generates a corresponding buffer memory read command which is encoded in such a way that it indicates the storage location in the auxiliary memory (172). 10. Data processing arrangement according to claim 9, characterized in that the auxiliary processor (171) has a transmission arrangement (e.g. 210, IQCCDR, IQBB, 202) controlled by the access control arrangement (e.g. 9 CCAR, 10 CCD, 42 OCG, 2SEQ, 11CMA) which transfers the data read from the specified memory location in the auxiliary memory (172) to the main processor (101) via the memory bus system (106) with the aid of the corresponding auxiliary memory read command. 11. Data processing arrangement according to claim 2, characterized in that each of the other memory write commands is coded in such a way that the auxiliary processor (171) has to write one of the registers (e.g. 19 QR) and into this register (e.g. 19 QR) Indicates data, and that the auxiliary processor (171) contains a transmission arrangement (e.g. 10 BB, 30 CBL, 30MjB) controlled by the access control arrangement (e.g. 9CCAR, IQCCDR, IQCCD, 42 OCG, 2SEQ) on the basis of each of the other memory write commands, to transfer the specified data to the specified register (e.g. 19 QR) . 12. Data processing arrangement according to claim 2, characterized in that each of the other memory read commands is coded so that it indicates the auxiliary processor (171) and one of the registers (z. B. 19 QR) and that the auxiliary processor (171) a transmission arrangement (z B. 30 UB, IQCCDR, 202), which is controlled by the access control arrangement (e.g. 9 CCAR, IQCCD, 42 OCG, 2 SEQ) on the basis of each of the other memory read commands in order to store the data in the specified register (e.g. B. QR) via the storage manifold system (106) to the main processor (101). 13. Data processing arrangement according to claim 1, characterized in that the auxiliary processor (171) has a first clock pulse source (4703), the first output signals (T-pulses) for controlling the operation of the sub-processor (171) with reference to that in the auxiliary storage (172J supplies data in accordance with the programs contained in auxiliary memory (172), as well as a second clock pulse source (4702), the second output signals (C-pulses) for controlling other operations of the auxiliary processor (171) including the operation of the access control arrangement (e.g. 9 CCAR, IQCCDR, IQCCD, AlOCG, 2SEQ, UCMA) and thereby enables the main processor (101) to access the auxiliary memory (172). 14. Data processing arrangement according to claim 13, characterized in that the Auxiliary processor (171) includes a halt control arrangement (4855) responsive to the particular memory read and write commands respond and the delivery of the first output signals (T-pulses) by the first clock pulse source (4703) stops. 15. Data processing arrangement according to claim 14, characterized in that the first clock pulse source (4703) and the second clock pulse source (4702) with a main clock pulse source (e.g. 461, 4615) in the main processor ao (101) with the aid of output signals (e.g. TSYNC, 2MC) are synchronized from the master clock pulse source (e.g. 461, 4615). 16. Data processing arrangement according to claim 14, characterized in that the auxiliary processor (171) contains a clock control arrangement (42 OCG, 4855) which periodically starts the first clock pulse source (4703) in synchronism with the second clock pulse source (4702). 17. Data processing arrangement according to claim 14, characterized in that the auxiliary processor (171) contains a clock control arrangement (42 OCG, 4855) which starts the first clock pulse source (4703) in synchronism with the second clock pulse source (4702) when the response of the access control arrangement ( e.g. 9 CC AR, IfSCCDR, 10 CCD, 42 OCG, 2SEQ, UCMA) of the auxiliary processor (171) has ended on one of the specific memory write and read commands. 18. Data processing arrangement according to claim 2, characterized in that the auxiliary processor (171) contains a blocking arrangement (4855) which responds to the specific and the other memory commands and the response of the access control arrangement (e.g. 9CAR, lOCCDR, IQCCD, 42OCG, 2SEQ, HCMA) of the auxiliary processor (171) blocks subsequent data storage commands for a predetermined time interval. 19. Data processing arrangement according to claim 1, characterized in that the im Auxiliary memory (172) contained programs sequences of machine instructions that the Auxiliary processors (171) respond to each of the machine instructions by generating at least one of the Auxiliary memory read commands responds which are coded so that they have a memory location in the auxiliary memory (172) specify, and that the auxiliary processor (171) on certain machine commands responds by generating one of the auxiliary memory write commands which are encoded so that they indicate a storage location in the auxiliary memory (172) and data to be written into it. 20. Data processing arrangement according to claim 7, characterized in that the auxiliary processor (171) contains means (183) which respond to the programs contained in the auxiliary memory (172) and the control of the blocking arrangement (4855) by the display arrangement for critical addresses (e.g. 12 CAR, 12 CAM, 12 ASR, 9 CCAR) switches on and off. 21. Data processing arrangement according to claim 19, characterized in that the auxiliary processor (171) contains an error display arrangement (183) for displaying data processing and transmission errors and an interrupt control arrangement (49 / C) which responds to certain displayed data processing and transmission errors and an emergency interrupt signal (e.g. SOSSPT) to the main processor (101) and which responds to certain machine commands and transmits a no-emergency interrupt signal (e.g. 50 SSPB) to the main processor (101). 22. Data processing arrangement according to claim 21, characterized in that the error display arrangement (183) contains indicators (z. B. 37 SPE, 40 CSE) , the detected defective transmissions between the auxiliary processor (171) and the input-output system (180) and that the interrupt control arrangement (49 IC) responds to the indication of a detected faulty transmission with the input-output system (180) and gives an emergency interrupt signal (e.g. 50 SSPA) to the main processor (101). In addition 3 sheets of drawings