DE1316146T1 - Schaltung zur erzeugung von differentialsignalen niedriger spannung - Google Patents

Schaltung zur erzeugung von differentialsignalen niedriger spannung

Info

Publication number
DE1316146T1
DE1316146T1 DE1316146T DE01966496T DE1316146T1 DE 1316146 T1 DE1316146 T1 DE 1316146T1 DE 1316146 T DE1316146 T DE 1316146T DE 01966496 T DE01966496 T DE 01966496T DE 1316146 T1 DE1316146 T1 DE 1316146T1
Authority
DE
Germany
Prior art keywords
circuit
low voltage
differential signals
voltage differential
generating low
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE1316146T
Other languages
English (en)
Inventor
V Ghia
M Menon
P Schultz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xilinx Inc
Original Assignee
Xilinx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xilinx Inc filed Critical Xilinx Inc
Publication of DE1316146T1 publication Critical patent/DE1316146T1/de
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264Arrangements for coupling to transmission lines
    • H04L25/0272Arrangements for coupling to multiple lines, e.g. for differential transmission
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175Coupling arrangements; Interface arrangements
    • H03K19/0185Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507Interface arrangements
    • H03K19/018521Interface arrangements of complementary type, e.g. CMOS
    • H03K19/018528Interface arrangements of complementary type, e.g. CMOS with at least one differential stage
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/151Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264Arrangements for coupling to transmission lines
    • H04L25/028Arrangements specific to the transmitter end
DE1316146T 2000-09-05 2001-08-31 Schaltung zur erzeugung von differentialsignalen niedriger spannung Pending DE1316146T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/655,168 US6366128B1 (en) 2000-09-05 2000-09-05 Circuit for producing low-voltage differential signals
PCT/US2001/027233 WO2002021684A2 (en) 2000-09-05 2001-08-31 Circuit for producing low-voltage differential signals

Publications (1)

Publication Number Publication Date
DE1316146T1 true DE1316146T1 (de) 2003-11-27

Family

ID=24627795

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1316146T Pending DE1316146T1 (de) 2000-09-05 2001-08-31 Schaltung zur erzeugung von differentialsignalen niedriger spannung

Country Status (6)

Country Link
US (2) US6366128B1 (de)
EP (1) EP1316146B1 (de)
JP (1) JP5016176B2 (de)
CA (1) CA2419936C (de)
DE (1) DE1316146T1 (de)
WO (1) WO2002021684A2 (de)

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US6815980B2 (en) * 2003-02-27 2004-11-09 International Business Machines Corporation Termination circuit for a differential transmission line
US6819142B2 (en) * 2003-03-13 2004-11-16 Infineon Technologies Ag Circuit for transforming a differential mode signal into a single ended signal with reduced standby current consumption
US6888369B1 (en) 2003-07-17 2005-05-03 Altera Corporation Programmable on-chip differential termination impedance
US6888370B1 (en) 2003-08-20 2005-05-03 Altera Corporation Dynamically adjustable termination impedance control techniques
US6859064B1 (en) 2003-08-20 2005-02-22 Altera Corporation Techniques for reducing leakage current in on-chip impedance termination circuits
US6864704B1 (en) 2003-09-24 2005-03-08 Altera Corporation Adjustable differential input and output drivers
US6943588B1 (en) 2003-09-24 2005-09-13 Altera Corporation Dynamically-adjustable differential output drivers
US7245144B1 (en) 2003-09-24 2007-07-17 Altera Corporation Adjustable differential input and output drivers
US7256624B2 (en) * 2003-10-28 2007-08-14 Via Technologies, Inc. Combined output driver
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JP4509737B2 (ja) * 2004-10-28 2010-07-21 株式会社東芝 差動信号生成回路および差動信号送信回路
US20060119382A1 (en) * 2004-12-07 2006-06-08 Shumarayev Sergey Y Apparatus and methods for adjusting performance characteristics of programmable logic devices
US7218155B1 (en) 2005-01-20 2007-05-15 Altera Corporation Techniques for controlling on-chip termination resistance using voltage range detection
US7221193B1 (en) 2005-01-20 2007-05-22 Altera Corporation On-chip termination with calibrated driver strength
US7193443B1 (en) 2005-05-23 2007-03-20 Altera Corporation Differential output buffer with super size
US7679397B1 (en) 2005-08-05 2010-03-16 Altera Corporation Techniques for precision biasing output driver for a calibrated on-chip termination circuit
US7439760B2 (en) 2005-12-19 2008-10-21 Rambus Inc. Configurable on-die termination
US7391229B1 (en) 2006-02-18 2008-06-24 Altera Corporation Techniques for serially transmitting on-chip termination control signals
US7936184B2 (en) * 2006-02-24 2011-05-03 Altera Corporation Apparatus and methods for adjusting performance of programmable logic devices
US7420386B2 (en) 2006-04-06 2008-09-02 Altera Corporation Techniques for providing flexible on-chip termination control on integrated circuits
US7855924B2 (en) * 2006-05-19 2010-12-21 Arm Limited Data processing memory circuit having pull-down circuit with on/off configuration
US7501851B2 (en) * 2006-05-26 2009-03-10 Pmc Sierra Inc. Configurable voltage mode transmitted architecture with common-mode adjustment and novel pre-emphasis
US7427878B2 (en) * 2006-06-01 2008-09-23 Fujitsu Limited Low-voltage differential signal driver for high-speed digital transmission
US8022723B1 (en) * 2006-07-19 2011-09-20 Altera Corporation Dynamic termination-impedance control for bidirectional I/O pins
US7417452B1 (en) 2006-08-05 2008-08-26 Altera Corporation Techniques for providing adjustable on-chip termination impedance
DE102006038870A1 (de) * 2006-08-18 2008-02-28 Texas Instruments Deutschland Gmbh Integrierter CMOS-Schaltkreis mit einem differenziellen Open-Drain-Ausgangstreiber
US7423450B2 (en) 2006-08-22 2008-09-09 Altera Corporation Techniques for providing calibrated on-chip termination impedance
US7953162B2 (en) * 2006-11-17 2011-05-31 Intersil Americas Inc. Use of differential pair as single-ended data paths to transport low speed data
US7979039B2 (en) * 2007-09-24 2011-07-12 Intel Corporation Pre-distorting a transmitted signal for offset cancellation
US8618842B2 (en) * 2011-09-30 2013-12-31 Qualcomm Incorporated Differential PVT/timing-skew-tolerant self-correcting circuits
TWI468710B (zh) * 2013-03-25 2015-01-11 Test Research Inc 用於電壓設定的測試機台
US9853642B1 (en) * 2016-08-11 2017-12-26 Xilinx, Inc. Data-dependent current compensation in a voltage-mode driver
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US5949253A (en) * 1997-04-18 1999-09-07 Adaptec, Inc. Low voltage differential driver with multiple drive strengths
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Also Published As

Publication number Publication date
WO2002021684A3 (en) 2003-02-27
EP1316146B1 (de) 2013-01-23
EP1316146A2 (de) 2003-06-04
JP5016176B2 (ja) 2012-09-05
US6366128B1 (en) 2002-04-02
JP2004508761A (ja) 2004-03-18
CA2419936C (en) 2012-10-16
US20020060602A1 (en) 2002-05-23
US6531892B2 (en) 2003-03-11
WO2002021684A2 (en) 2002-03-14
CA2419936A1 (en) 2002-03-14

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