DE19538994A1 - Dynamic interference-free address coding - Google Patents

Abstract

A synchronous SRAM device comprises a memory clock and a plurality of address lines which include a plurality of block address lines (404) and a plurality of row address lines (403). The SRAM device includes a row predecoder (406) for predecoding and synchronizing each of the row address lines (403) to the memory clock to yield a plurality of global row address signals (408) and a block predecoder (407) for predecoding and synchronizing each of the block address lines to the memory clock to yield a plurality of block address signals (409). The predecoder functions are implemented by using domino gates. The memory device also includes a plurality of blocks of memory, each block having an array of memory cells arranged in rows and columns. A block select decoder (411) selects a block of the memory responsive to the block address signals, and a global row decoder (410) selects a row of the array responsive to the global row address signals. The domino gates can be located close to the address line pins on the integrated circuit to minimize the capacitance on the memory clock line. <IMAGE>

Description

This invention relates to a method of deco dier of address lines for a memory device and in particular to a method and a device for Si Creation of a glitch-free address decode tion for the storage device.

A method of accelerating a static direct to handle memory (SRAM; SRAM = static random access memory) is a small single block of memory in small split up more memory blocks. An additional decoder stage (block decoder for each memory block) must the SRAM can be added to access individual blocks, each yet the behavior is by reducing the parasitic Capacitance and resistance that clot the memory block is assigned to a larger size, improved. The reduction of Capacity increases the speed of the circuits that drive the smaller blocks. A memory based on this The way it is organized is as a block architecture SRAM known.

The address lines to a block architecture SRAM can be in three different categories can be grouped. A first one Set of address lines specifies the particular memory accessed. A block decoder is used to build the special block based on the select the first set of address lines. The second and the third group designate a row and a column in the particular SRAM block being accessed. On Row decoder is used for row selection while a column decoder is used for column selection. Of the The term "word lines" generally refers to one Set of conductors who, when active, addressed the Select the row of memory cells of the selected block.  

The local word line (LWL; LWL = local word line) one special row of memory cells is activated when the corresponding line address and block address of the line from Memory cells is selected. This architecture will too referred to as a shared wordline approach. The Column address for this configuration of the SRAM has the Function of multiplexing the selected row of Spei cher cells to the SRAM input / output. If the number of Memory cells in each row of memory blocks 128 and the I / O lines (I / O = input / output = input / output) The column selection multiplexer chooses 16 bits wide for example the desired 16 memory cells from the 128 activated cells. With this SRAM architecture, the Column decoder not as critical as the row decoder or block decoder. The line decoder is signal-carrying approximately connected to a plurality of memory blocks. The local word line in a special block is through "ANDing" the global row decoder output with the block selection line selected. The row decoder gang is typically called the global word line. The logic required to run the column decoder Implementing function is much easier. Therefore are the timing restrictions on the column decoder a lot more relaxed than the timing restrictions on the glo header row decoder or the block selection decoder.

A common problem in address decoding a SRAM are interference on the local word line to step. Glitches can occur due to delays Delivery time offsets on the address lines and propagation delays caused by the address decoding logic blocks be det. Generally the signal is local SRAM wordline through both the global wordline and also controlled the block selection decoder. The address book delays and the combination logic to the global row decoder, as well as the address line delays and cross the combination logic to the block selection below different ways via the integrated circuit. The delays  Written two separate ways become different his. The local word line of a selected memory cell is the logical "AND" product of global wording device and the block selection corresponding to the special line of Corresponds to memory cells. Depending on the special SRAM circuit design can occur in a situation which the way the global line decoder has a greater delay less than the path of the block selection decoder. Faults can occur when two consecutive Accesses to a special block of memory exist that However, accesses rows of memory cells with under different global word lines take place.

Fig. 1 shows the generally accepted address line decoding used for a synchronous block architecture SRAM. The address lines are latched into the SRAM using a set of master / slave flip-flops 110 , 111 , 112 and 113 . A plurality of master / slave flip-flops 110 , 111 snap in the address lines which are assigned to the global word line, while a plurality of master / slave flip-flops 112 , 113 snap in the address lines which are assigned to the block selection are. The address line signals, after latching, propagate with a certain delay 114 , 115 to a global line decoder 116 and a block selection decoder 117 . The block selection decoder 117 is clocked using a clock (CLK) because its output drives the precharge of the sense amplifier. The sense amplifiers amplify the output signals of the memory cells (bit lines) before the output signals reach the output pin on the integrated SRAM circuit. In order to work correctly, the sense amplifiers must be precharged before the memory cell is accessed. The block selection decoder 117 accesses the desired memory block and generates the pre-charge signal of the sense amplifier. The timing constraints on the precharge of the sense amplifiers prior to memory access require that the block selection decoder be clocked. The global line decoder 116 cannot be clocked as this would require the clock line to be routed to all global line decoders. This would consume an excessive amount of clock resources and add undesirable capacity to the clock line. The outputs of decoders 116 , 117 propagate with a certain delay 118 , 119 to "AND" gate 120 , which generates the local word line signal.

The local word line activates a row of memory cells in a special memory block to be accessed. Each row of a memory block has a local word line that can select the row. If there are any disturbances in the local word lines, this means that two lines of memory in a block of memory can be accessed simultaneously. The desired local word line accesses the desired row of memory cells, while the disturbance that occurs in an undesirable local word line accesses an undesired row of memory cells. This is an undesirable situation and incorrect operation of the SRAM can occur. The SRAM address decoder architecture shown in Fig. 1 can produce noise in the local word line if the delays in decoding the global word line and the delays in block selection decoding are not well controlled. Controlling the delays includes checking and simulating all local word lines that access all memory rows in all memory blocks in the SRAM chip.

Fig. 2 shows the waveform of the global word line (GWL) and the block selection waveform (BS), which generates a fault 221 in the local word line (LWL). The fault 221 will occur when two memory accesses access the same block of memory but different rows in the particular block. From the waveforms in Fig. 2 it can be seen that the fault 221 occurs because the global word line (GWL) does not turn off before the next block selection (BS) occurs.

In the past, the solution for a local word line (LWL) that has a fault 221 was to ensure that the global word line (GWL) always switches off before the next block selection (BS) occurs. This was accomplished by varying the gate width ratios of the NMOS / PMOS transistors in the SRAM logic gates that generated the global word line signal. The gates have been modified in such a way that the global wordline switches off earlier than before. If the global word line (GWL) switches off earlier, there are no faults in the local word line. One result of this modification is that the global word line (GWL) tends to turn on later than before. Fig. 3 shows what the waveforms look like with this modification. The original waveforms are shown by dashed lines. Fig. 3 shows that a signal on the local word line (LWL) was slightly delayed in time. The result of this delay is that memory accesses take longer than they originally did. Another undesirable aspect is that the SRAM circuit designer must monitor the block select and global word lines each time he designs a new circuit to ensure that there is no interference in the local word line. The block selection (BS) and the global word line (GWL) have to be adapted over the entire SRAM chip in order to ensure that none of the local word lines has faults. This includes extensive simulations, in which many variables must be thoroughly tested to be sure that the SRAM is working as specified. The simulation process must be repeated each time the SRAM design or the chip layout is modified. Of course, this is not a satisfactory solution to the problem.

It is the object of the present invention to provide a device  device and a method for dynamic, trouble-free ad reßdecoding to create the memory access time do not increase.

This task is accomplished by a storage device according to Pa claim 1 and a method according to claim 6 solved.

The present invention provides a synchronous SRAM ad address decoding scheme that guarantees that in the local Word line no glitches occur, and that memory access time does not increase like previous solutions. Interference in the local word line is undesirable because if the fault occurs, on two separate lines from Memory cells in a memory block accessed simultaneously will.

The invention can be implemented in a storage device with a Memory clock and a plurality of address lines imple be mented. The address lines have a plurality of Block address lines and a plurality of row address lines towards. The storage device has a row predeco predecode and synchronize each of the times lenadreßlinien on the memory clock to a plurality of global line address signals, and a block Predecoder to predecode and synchronize everyone the block address lines to the memory clock to a more number of block address signals. The memory direction also has a plurality of memory blocks, wherein each block has an array of memory cells that is arranged in rows and columns. The storage device device also has a block selection decoder for selection a block of memory that is responsive to the block address signals speaks, and a global line decoder to select ner line of the array which is directed to the global line address signals appeals to.

The row predecoder and the block predecoder in the  Storage device can use domino gates to all prevent unwanted interference. A domino gate be sits an input, an output and a control signal entrance. The domino gate works by outputting one high logic level when its control signal is low, and outputting a level equivalent to a function of the signal at the input of the domino gate is when Control signal is high. Any address line that is decoded the logical level of the block selection or to determine the global word line through a do mino gate directed. This is the tax for this invention signal to the domino gate the synchronous SRAM clock. If the SRAM clock is low, are the outputs of the domino gate at a high logic level or in a pre-charge Mode. If the SRAM clock is high, the outputs of the Domino gate a function of the address lines on the SRAM Entrance.

Preferred embodiments of the present invention are referred to below with reference to the attached drawing nations explained in more detail. Show it:

Fig. 1 is a functional diagram of the known SRAM address de coder;

Figure 2 shows the waveforms of a known SRAM address de coder, which has a disturbance in the local word line device.

FIG. 3 shows the waveforms tung a known solution, the SRAM Adreßdecodiererstörung in the local wordline;

Figure 4 is a general functional block diagram of this invention;

Figure 5 shows the functional diagram of the SRAM address decoder for this invention; and

Figure 6 shows the waveforms of the SRAM address decoder of this invention.

A general block diagram representation of this invention is shown in FIG . Address lines are first latched by address latches 401 and 402 . The address lines latched in the first latch 401 drive the row address lines 403 . The address lines latched in the second latch 402 drive the block address lines 404 . The row address lines 403 are predecoded by a row predecoder 406 and synchronized to the synchronous SRAM clock 405 . Row predecoder 406 drives row address signals 408 high when clock input 405 is low. When clock 405 is high, row pre-decoder 406 still drives row address signals 408 , but as a function of row address lines 403 at the input of row pre-decoder 406 . The block address lines 404 are predecoded by a block predecoder 407 and synchronized to the synchronous SRAM clock 405 . Block predecoder 407 drives block address signals 409 high when clock input 405 is low. When clock 405 is high, block predecoder 407 still drives block address signals 409 , but as a function of block address lines 404 at the input of block predecoder 407 . In this novel predecoding and synchronization scheme, the global row decoder 410 and the block selection decoder 411 output signals that are timed in such a way that there is never a disturbance in the local word line 413 .

Figure 5 shows the address line decoding configuration of this invention. The known master-slave flip-flop configuration shown in FIG. 1 has been replaced by input latch sections 501 , 502 . The predecoders of Figure 4 have been replaced by domino gates 503 , 504 . The input latch sections 501 , 502 have inverters at their output. This inversion is necessary because dominoes 503 , 504 are in the subsequent stage. The domino gates 503 , 504 themselves have no signal inversion. The original slave latches 111 , 113 of FIG. 1 had one. The inversion is corrected by including an inversion in the input latches 501 , 502 . The block selection decoder 508 need not be clocked in this configuration. As with the known configuration, the global line decoder 507 is also not clocked. Global line decoder 507 and block selection decoder 508 decode the address line inputs to select the desired block and line of SRAM. Fig. 5 also shows the signal path delays 505 , 506 , 509 , 510 , which are assigned to the path lengths of the electrical connections between all address selection functions.

Domino gates 503 , 504 of Fig. 5 output a high logic level when their control signal is low and output a level equivalent to a function of the signal at their inputs when their control signal is high. Each address line to be decoded is passed through a domino gate to determine the logical level of the block select or global word line. For this invention, the control signal to the domino gate is the synchronous SRAM clock (CLK). The result is that when the SRAM clock is low, the outputs of the do mino gates are at a high logic level or in a pre-charge mode. If the SRAM clock is high, the outputs of the domino gates will be a function of the address lines on the SRAM input. The domino gates have been used in dynamic circuit design, but no one has previously used them to resolve the local word line interference that occurs with SRAM address line decoding. The domino gates 503 , 504 are placed on the integrated SRAM circuit near the Adreßan circuit surfaces. This is advantageous because the clock line is not routed around or over the SRAM chip, as was previously the case. A lower signal routing of the clock means that the clock line will have a smaller capacitance from it. Therefore, a lower cycle time offset is observed and the chip will derive less power.

The waveforms of the decoded SRAM address lines using domino gates are shown in FIG. 6. There are several significant features that can be observed with respect to these waveforms. The global word line (GWL) switches off well before the second block selection (BS). The local word line is only delayed by the amount of time it takes to decode the address lines. The fact that the global word line (GWL) of FIG. 6 turns off quickly ensures that there is no interference in the local word line (LWL) will occur. The local word line (FO) can be accelerated due to the fact that the domino gates guarantee that there will be no interference in the local word line (FO). This can be achieved by varying the gate width ratios of the NMOS / PMOS transistors in the logic gates of the SRAM that generate the signal on the local word line (FO). The dashed lines in Fig. 6 show the original waveforms in which the disturbance existed.

The general concept behind the operation of the SRAM decode tion of this invention can be described as follows. To first the desired memory address is increased Edge of the clock locked. Next, decode the Global wordline and block select decoders the address lines and select the correct line of memory the next rising edge of the system clock. If the address is decoded, the local word line of the desired row of memory cells of the selected memory cherblocks activated. This sets the criterion that the De encode the address lines within half a clock cycle must take place. However, it also ensures that there will be no interference in the local word line.  

This configuration frees the developer of the SRAM scarf tion furthermore, all local word lines of the whole Examine SRAM design for interference every time the chip layout changes with a new circuit design different.

Claims (7)

1. Storage device with the following features:
a memory clock ( 405 );
a plurality of address lines, the address lines including a plurality of block address lines ( 404 ) and a plurality of row address lines ( 403 );
a row predecoder ( 406 ) for predecoding and synchronizing each of the row address lines to the memory clock ( 405 ) to obtain a plurality of global row address signals ( 408 );
a block predecoder ( 407 ) for predecoding and synchronizing each of the block address lines to the memory clock to obtain a plurality of block address signals;
a plurality of memory blocks, each block having an array of memory cells arranged in rows and columns;
a block selection decoder ( 411 ) for selecting a block of memory responsive to the block address signals; and
a global line decoder ( 410 ) for selecting a line of the array responsive to the global line address signals. 2. The apparatus of claim 1, wherein the row pre-decoder ( 406 ) has a plurality of domino gates ( 503 ), and wherein the block pre-decoder ( 407 ) has a plurality of domino gates ( 504 ). 3. Apparatus according to claim 2, wherein the Speicherervor device is an integrated circuit having Adreßlei line pads, the domino gates ( 503 , 504 ) are physically positioned near the location where the address line pads are positioned, thereby minimizing the clock line capacity. 4. The device according to claim 1, 2 or 3, wherein the Storage device is an SRAM. 5. The device according to claim 4, wherein the SRAM with egg nem clock is synchronized, the SRAM a Zu grip time that is less than the duration of a Clock cycle is. 6. A method of selecting a row of memory cells in a memory device, the memory device comprising row address lines, block address lines and a memory clock, the row of memory cells being in a memory block, the memory block having an array of memory cells arranged in rows and Columns are arranged, the method comprising the following steps:

• (a) predecoding and synchronizing each of the block address lines to the memory clock to obtain a plurality of block address signals;
• (b) predecoding and synchronizing each of the row address lines to the memory clock to yield a plurality of global row address signals;
• (c) decoding the block address signals and selecting a memory block; and
• (d) Decode the global line address signals and select a line of memory in the memory block.

7. Method of selecting a row of memory cells in a memory device according to claim 6, wherein the pre-decoding and synchronization steps (a) and (b) take place substantially simultaneously.