DE19823583B4 - Combined semiconductor memory and logic device and memory test control circuit and memory test method therefor - Google Patents

Abstract

Semiconductor component with a memory-logic combination, comprising the following elements: a plurality of memories (17, 19), a contact point (8) receiving memory control signals (PC) for controlling the plurality of memories, a further contact point (7), applied to the memory data signals (DQI) received or generated by the plurality of memories, - a logic circuit (15) for controlling the plurality of memories, and - a memory test control circuit (13) connected to the further pad, the logic circuit and the plurality of memories ) for transmitting the memory control signals and the memory data signals to the plurality of memories when the plurality of memories are tested, in response to a test control signal (TESTMD0, TESTMD1) and for transferring the memory control signals and the memory data signals to the logic circuit during a normal operation.

Description

The invention relates to a combined semiconductor memory and logic device as well as to a memory test control circuit and a memory test method therefor.

In a combined semiconductor memory and logic device, a memory such. For example, a dynamic or a static random access memory (DRAM) or SRAM, and a logic circuit for controlling the memory in a semiconductor device combined to realize a system of small dimension and low weight, which has a high performance with low power consumption ,

In order to test the memory contained in a semiconductor memory device, a test setup is connected to pads of the semiconductor memory. However, with this, the memory included in a combined semiconductor memory and logic device can not be easily tested because the memory is connected to the pads via a logic circuit provided in the combined semiautomatic memory and logic device. Accordingly, additional pads are needed to test the memory incorporated in a combined semiconductor memory and logic device, see e.g. B. the patent US 5,535,165 A , However, as the number of pads increases, the size of the combined semiconductor memory and logic device increases, increasing its manufacturing cost.

Patent 5,568,437 A discloses an integrated circuit having a random access memory and built-in self-test structure for this memory.

The invention is based on the technical problem of providing a combined semiconductor memory and logic device, the memory of which can be tested as simply as possible, as well as a memory test control circuit and a memory test method, which are suitable for such a memory test in the combined semiconductor memory and logic device.

The invention solves this problem by providing a combined semiconductor memory and logic device having the features of claim 1 or 4, a memory test control circuit having the features of claim 9 and a memory test method having the features of claim 35.

Advantageous developments of the invention are specified in the subclaims.

Advantageous embodiments of the invention are illustrated in the drawings and will be described below. Hereby show:

1 a block diagram of a first combined semiconductor memory and logic device,

2 a block diagram of a first implementation of a memory test control circuit of 1 .

3 a block diagram of a memory control signal control unit of 2 .

4 a block diagram of a memory data control unit of 2 .

5 a block diagram of another implementation of the memory test control circuit of 1 .

6 a block diagram of a memory control signal control unit of 5 .

7 a block diagram of a first memory data control unit of 5 .

8th a block diagram of a second memory data control unit of 5 .

9 a block diagram of a second combined semiconductor memory and logic device,

10 FIG. 4 is a block diagram of a third combined semiconductor memory and logic device; FIG.

11 a block diagram of a fourth combined semiconductor memory and logic device,

12 a timing diagram of signals in the circuit diagrams of 9 to 11 and

13 a flowchart for illustrating a memory test method for the combined semiconductor memory and logic device.

1 shows in block diagram a first combined semiconductor memory and logic device 5 , the contact points 7 . 8th . 9 and 10 , a memory test control circuit 13 , a logic circuit 15 as well as first and second memories 17 . 19 contains.

The memory test control circuit 13 is at the contact points 7 to 10 connected, and the logic circuit 15 as well as the first and second memory 17 . 19 , z. DRAM banks are connected to the memory test control circuit 13 connected.

To the contact point 8th becomes a memory control signal PC for controlling the first and second memories 17 . 19 created, and to the contact points 9 and 10 Test control signals TESTMD0 and TESTMD1 are used to control the memory test control circuit 13 created. It also goes to the contact point 7 a memory data signal DQi applied to the first and second memories 17 . 19 supplied or discharged from them. The contact points 7 and 8th provide existing contact points to use the first and second memory 17 . 19 while the contact points 9 and 10 externally applied pads are to the memory test control circuit 13 to control. A memory test unit, not shown, is connected to the contact points 7 to 10 connected to functions of the first and second memory 17 . 19 of the combined semiconductor memory and logic device 5 to test. The memory test unit (not shown) gives information about the contact points 7 and 8th the memory control signal PC and the memory data signal DQi into the memory test control circuit 13 one. In addition, the memory test control circuit 13 controlled by a combination of the test control signals TESTMD0 and TESTMD1. Accordingly, the memory test control circuit is applied 13 when testing the first and second memory 17 . 19 the same with the memory control signal PC and the memory data signal DQi. The first and the second memory 17 . 19 operate under the action of the memory control signal PC and the memory data signal DQi, and the result thereof becomes the memory test control circuit 13 Posted. The memory test control circuit 13 transmits the signals of the first and second memory 17 . 19 to the storage test unit not shown on the contact points 7 and 8th , Accordingly, the memory test unit (not shown) analyzes via the pads 7 and 8th transmitted signals to the functions of the first and second memory 17 . 19 to determine.

In the case that the semiconductor memory device with memory-logic combination 5 works normally, ie without testing the first and second memory 17 . 19 , is the memory test control circuit 13 by the combination of the test control signals TESTMD0 and TESTMD1 not partially in operation. When the memory control signal PC and the memory data signals DQi are externally applied to the combined semiconductor memory and logic device 5 to operate normally, the signals supplied to the logic circuit 15 entered via the memory test control circuit 13 the first and second memories 17 . 19 controls.

While in this example the combined semiconductor memory and logic device has two memories, the invention may alternatively be used for a combined semiconductor memory and logic device with any other number of memories. As indicated above, in the combined semiconductor memory and logic device 5 the first and second memories 17 . 19 using the conventional contact points 7 . 8th be tested.

2 shows a block diagram of a first implementation of the memory test control circuit 13 from 1 , According to 2 includes the memory test control circuit 13 a main control signal generator 23 a memory control signal control unit 25 and a memory data control unit 27 ,

In the main control signal generator 23 For example, the test control signals TESTMD0 and TESTMD1 are applied to an input terminal while an output terminal is connected to the memory control signal control unit 25 and the memory data control unit 27 connected is. The main control signal generator 23 generates main control signals MEMTEST1, MEMTEST2 and NORMAL in response to the test control signals TESTMD0 and TESTMD1. Table 1 shows an exemplary truth table for the main control signal generator 23 , Table 1: function TESTMD0 TESTMD1 Main control signal Test 1. Memory "L" "L" MEMTEST1 Test 2. Memory "H" "L" MEMTEST2 normal operation "L" "H" NORMAL "H" "H" PRESENT. Keep state

As shown in Table 1, when the test control signals TESTMD0 and TESTMD1 are at logic low level "L", the main control signal MEMTEST1 is activated to the first memory 17 from 1 to test, and when the test control signal TESTMD0 is activated to high logic level "H" and the test control signal TESTMD1 is at logic low level "L", the main control signal MEMTEST2 is active to the memory 19 from 1 to test. Likewise, when the test control signal TESTMD0 is low logic level "L" and the test control signal TESTMD1 is high logic level "H", the signal NORMAL is active to the logic circuit 15 from 1 to operate normally. When the test control signals TESTMD0 and TESTMD1 are at logic low level "L", the previous state is maintained. The memory control signal control unit 25 receives this via the contact point 8th supplied memory control signal PC and is controlled by the main control signals MEMTEST1, MEMTEST2 and NORMAL to the memory control signal PC to the first and second memory 17 . 19 and to the logic circuit 15 from 1 transferred to. The memory control signal PC includes a row address strobe signal RASB, a column address strobe signal CASB, a write enable signal WEB, an output enable signal OEB, and an address signal Ai.

The memory data control unit 27 receives this via the contact point 7 supplied memory data signal DQi and is controlled by the main control signals MEMTEST1, MEMTEST2 and NORMAL to the externally input memory data signal DQi to the first or second memory 17 . 19 from 1 or to the logic circuit 15 from 1 as well as from the first and second memory 17 . 19 from 1 or the logic circuit 15 from 1 generated memory data signal DQi to the contact point 7 forward.

As explained above, in this first embodiment, the memory test control circuit 13 the first and second memories 17 . 19 from 1 using the normal contact points 7 and 8th from 1 without the logic circuit 15 testing.

3 shows a block diagram of a realization of the memory control signal control unit 25 from 2 , The memory control signal control unit 25 from 3 includes a buffer 31 , a logic gate 33 and a memory controller 35 , The buffer 31 receives the memory control signal PC and supplies the output signal to the logic gate 33 to. The buffer 31 changes the voltage level of the memory control signal PC. For example, the voltage level of a transistor-transistor logic (TTL) is converted into a voltage level of a complementary MOS technique (CMOS). The logic gate 33 receives the output signal of the buffer 31 and gives its output signals to the memory controller 35 from. The logic gate 33 includes first, second and third AND gates 33a . 33b and 33c ,

The first AND gate 33a receives the output signal of the buffer 31 and the main control signal MEMTEST1. If the output signal of the buffer 31 or the main control signal MEMTEST1 is at logic low level, generates the first AND gate 33a a low logic level signal while generating a high logic level signal when the output of the buffer 31 and the main control signal MEMTEST1 are at a high logic level.

The second AND gate 33b receives the output signal of the buffer 31 and the main control signal NORMAL and outputs its output signal to the logic circuit 15 from 1 from. If the output signal of the buffer 31 or the main control signal NORMAL is at logic low level, generates the second AND gate 33b a low logic level signal while generating a high logic level signal when the output of the buffer 31 and the main control signal NORMAL are at a high logic level.

The third AND gate 33c receives the output signal of the buffer 31 and the main control signal MEMTEST2. If the output signal of the buffer 31 or the main control signal MEMTEST2 is at logic low level, generates the third AND gate 33b a low logic level signal while generating a high level signal when the output of the buffer 31 and the main control signal MEMTEST2 are at a low logic level.

The memory controller 35 has a first and second multiplexer 35a . 35b on. As the first multiplexer 35a a multiplexer with two inputs and one output is used. The first multiplexer 35a receives the output of the first AND gate 33a and the output signal of the logic circuit 15 from 1 and is controlled by the main control signals NORMAL and MEMTEST1 to the output signal of the first AND gate 33a and the output signal of the logic circuit 15 from 1 to the first memory 17 from 1 forward. The first multiplexer transmits 35a when the main control signal NORMAL is active, from the logic circuit 15 of the 1 generated signals to the first memory 17 from 1 while coming from the first AND gate 33a generated signals to the first memory 17 from 1 transmits when the main control signal MEMTEST1 is active.

As a second multiplexer 35b one with two inputs and one output is used. The second multiplexer 35b receives the output of the third AND gate 33c and the output signal of the logic circuit 15 from 1 and is controlled by the main control signals NORMAL and MEMTEST2 to control the output of the third AND gate 33c and the output of the logic circuit 15 from 1 to the second memory 19 from 1 forward. In the process, the second multiplexer transmits 35b from the logic circuit 15 of the 1 generated signals to the second memory 19 from 1 when the main control signal NORMAL is active while being from the third AND gate 33c generated signals to the second memory 19 from 1 transmits when the main control signal MEMTEST2 is active.

4 shows in the block diagram a realization of the memory data control unit 27 from 2 , This storage data control unit 27 includes an input / output buffer 41 , a logic gate 43 , a memory controller 45 , an output control 47 and an output buffer controller 49 , The input / output buffer 41 includes an input buffer 41a and an output buffer 41b ,

The input buffer 41a receives the memory data signal DQi and transmits the output signal to the logic gate 43 , The input buffer 41a changes the voltage level of the memory data signal DQi. For example, a TTL voltage level is converted to a CMOS voltage level. The output buffer 41b is through the output buffer control 49 controlled to the output signal of the output control 47 to lead to the outside. In doing so, the output buffer becomes 41b for transmitting the output signal of the output controller 47 enabled to the outside when the output of the output buffer control 49 is active while the output buffer 41b when the output of the output buffer control 49 is inactive, remains inactive to transmit the output signal of the output controller 47 to prevent the outside.

The logic gate 43 receives the output of the input buffer 41a and the main control signals MEMTEST1, NORMAL and MEMTEST2, and passes the output of the memory controller 45 to. The logic gate has first, second and third AND gates 43a . 43b . 43c on.

The first AND gate 43a receives the output of the input buffer 41a and the main control signal MEMTEST1 and transmits the output to the memory controller 45 , If the output of the input buffer 41a or the main control signal MEMTEST1 is at logic low level, generates the first AND gate 43a a low logic level signal while generating a high logic level signal when the output buffer of the input buffer 41a and the main control signal MEMTEST1 are at a high logic level.

The second AND gate 43b receives the output of the input buffer 41a and the main control signal NORMAL, and transmits the output signal to the logic circuit 15 from 1 , If the output of the input buffer 41a or the main control signal NORMAL is at logic low level, generates the second AND gate 43b a low logic level signal while generating a high logic level signal when the output buffer of the input buffer 41a and the main control signal NORMAL are at a high logic level.

The third AND gate 43c receives the output signal of the input buffer 41a and the main control signal MEMTEST2 and transmits the output to the memory controller 45 , If the output of the input buffer 41a or the main control signal MEMTEST2 is at logic low level, generates the third AND gate 43c a low logic level signal while generating a high logic level signal when the output buffer of the input buffer 41a and the main control signal MEMTEST2 are at a high logic level.

The memory controller 45 includes a first and second multiplexer 45a . 45b , As the first multiplexer 45a one with two inputs and one output is used. The first multiplexer 45a receives the output of the first AND gate 43a and the output signal of the first logic circuit 15 from 1 and is controlled by the main control signals NORMAL and MEMTEST1 to the output signal of the first AND gate 43a and the output signal of the logic circuit 15 from 1 to the first memory 17 from 1 transferred to. The first multiplexer 45a transfers from the logic circuit 15 of the 1 generated signals to the first memory 17 from 1 when the main control signal NORMAL is active while being output from the first AND gate 43a generated signals to the first memory 17 from 1 transmits when the main control signal MEMTEST1 is active.

For the second multiplexer 45b one with two inputs and one output is used. The second multiplexer 45b receives the output of the third AND gate 43c and the output signal of the logic circuit 15 from 1 and is controlled by the main control signals NORMAL and MEMTEST2 to control the output of the third AND gate 43c and the output signal of the logic circuit 15 from 1 to the second memory 19 from 1 transferred to. The second multiplexer 45b transfers from the logic circuit 15 of the 1 generated signals to the second memory 19 from 1 when the main control signal NORMAL is active while being from the third AND gate 43c generated signals to the second memory 19 from 1 transmits when the main control signal MEMTEST2 is active.

The output control 47 receives from the logic circuit 15 of the 1 as well as from the first and second memory 17 . 19 from 1 generated signals and passes the output signal to the output buffer 41b further. For the output control 47 a multiplexer with three inputs and one output is used. The output control 47 is controlled by the main control signals NORMAL, MEMTEST1 and MEMTEST2. Here transfers the output control 47 from the logic circuit 15 of the 1 generated signals to the output buffer 41b when the main control signal NORMAL is active while from the first memory 17 of the 1 generated signals to the output buffer 41b transmits when the main control signal MEMTEST1 is active. When the main control signal MEMTEST2 is active, the output controller transmits 47 from the second memory 19 of the 1 generated signals to the output buffer 41b ,

The output buffer control 49 includes a first, second and third logic gate 49a . 49b . 49d , an AND gate 49c as well as a NAND gate 49e ,

The first logic gate 49a receives the main control signals MEMTEST1 and MEMTEST2. When one of the main control signals MEMTEST1 and MEMTEST2 is at a high logic level, the first logic gate generates 49a a signal at a high level while generating a signal at a low level when both the main control signal MEMTEST1 and the main control signal MEMTEST2 are at a low logic level.

The second logic gate 49b receives one from the first memory 17 of the 1 generated, first output buffer enable signal TRST1 and one from the second memory 19 of the 1 generated second output buffer enable signal TRST2. When the first or second output buffer enable signal TRST1, TRST2 is at a high logic level, the second logic gate generates 49b a high logic level signal while generating a low logic level signal when both the first and second output buffer enable signals TRST1, TRST2 are at a low logic level.

The fourth AND gate 49c receives the output signal of the first logic gate 49a and the output of the second logic gate 49b , When the output signal of the first logic gate 49a or the output signal of the second logic gate 49b is at a low logic level, the fourth AND gate generates a low logic level signal while generating a high logic level signal when both the output of the first logic gate 49a as well as the output signal of the second logic gate 49b are at a high logic level.

The third logic gate 49d receives the output of the fourth AND gate 49c and the main control signal NORMAL. When the output signal of the fourth AND gate 49c or the main control signal is at a high logic level, generates the third logic gate 49d a high logic level signal while producing a low logic level signal when both the output of the fourth AND gate 49c as well as the main control signal NORMAL are at low logic level.

The NAND gate 49e receives the output signal of the third logic gate 49d and a supply voltage VCC, and transmits the output signal to a control terminal of the output buffer 41b , The NAND gate 49e transmits the output signal of the third logic gate 49d in a modified form corresponding to the control terminal of the output buffer 41b , Here, the NAND gate generates 49e a low logic level signal when the output of the third logic gate 49d is at a high logic level, while generating a high logic level signal when the output of the third logic gate 49d is at a low logic level. When the output signal of the NAND gate 49e is at low logic level, ie is active, becomes the output buffer 41b is activated while it is deactivated when the output signal of the NAND gate 49e is at a high logic level, ie is inactive.

5 shows in block diagram a second embodiment of the memory test control circuit of 1 , The memory test control circuit 213 from 5 includes a main control signal generator 51 a memory control signal control unit 53 , a first storage data control unit 55 and a second storage data control unit 57 ,

The main control signal generator 51 receives a via the contact point 9 supplied test control signal TESTMD0 and transmits the output signal to the memory control signal control unit 53 to the first memory data control unit 55 and the second memory data control unit 57 , The main control signal generator 51 generates main control signals, ie, a main memory control signal MEMTEST and a main logic control signal NORMAL in response to the test control signal TESTMD0. An exemplary truth table for the main control signal generator 51 is shown in Table 2. Table 2: function TESTMD0 Main control signal 1st and 2nd memory test "L" MEMTEST normal operation "H" NORMAL

As can be seen from Table 2, the memory main control signal MEMTEST is active when the test control signal TESTMD0 is at logic low level, around the first and second memories 17 . 19 from 1 while the logic master control signal NORMAL is active when the test control signal TESTMD0 is high logic level, to test the logic circuit 15 from 1 to operate normally. The memory control signal control unit 53 receives via the contact point 8th the memory control signal PC and is controlled by the main control signals MEMTEST and NORMAL to the memory control signal PC to the first and second memory 17 . 19 from 1 or to the logic circuit 15 from 1 transferred to. The memory control signal PC includes a row address strobe signal RASB, a column address strobe signal CASB, a write enable signal WEB, an output enable signal OEB, and an address signal Ai.

The first memory data controller receives via the pad 7 supplied memory data signals DQ1i and is controlled by the main control signals MEMTEST and NORMAL to the memory data signals DQ1i to the first memory 17 from 1 or to the logic circuit 15 from 1 as well as from the first memory 17 from 1 or the logic circuit 15 from 1 generated memory data signals DQ1i via the contact point 7 to transfer to the outside.

The second storage data control unit 57 receives a via the contact point 7 supplied memory data signal DQ2i and is controlled by the main control signals MEMTEST and NORMAL to the memory data signal DQ2i to the second memory 19 from 1 or to the logic circuit 15 from 1 as well as the second memory 19 or the logic circuit 15 from 1 generated memory data signals DQ2i to the contact point 7 ' transferred to.

The second embodiment of the memory test control circuit 213 Thus, as explained above, the first and second memories 17 . 19 from 1 using common contact points 7 . 8th and 7 ' without the logic circuit 15 from 1 testing.

6 shows a block diagram of a realization of the memory control signal control unit 53 from 5 , This memory control signal control unit 53 includes a buffer 61 , a logic gate 63 and a memory controller 65 , The buffer 61 receives the memory control signal PC and transmits the output signal to the logic gate 63 , The buffer 61 changes the voltage level of the memory control signal PC. For example, a TTL voltage level is converted to a CMOS voltage level. The logic gate 63 receives the output signal of the buffer 61 and transmits the output signal to the memory controller 65 , The logic gate 63 has a first, second and third AND gate 63a . 63b . 63c on.

The first AND gate 63a receives the output signal of the buffer 61 and the main memory control signal MEMTEST. If the output signal of the buffer 61 or the main memory control signal MEMTEST is at low logic level, generates the first AND gate 63a a low logic level signal while generating a high logic level signal when the output of the buffer 61 and the memory main control signal MEMTEST are at a high logic level.

The second AND gate 63b receives the output signal of the buffer 61 and the main logic control signal NORMAL, and transmits the output signal to the logic circuit 15 from 1 , If the output signal of the buffer 61 or the logic main control signal NORMAL is at logic low level, generates the second AND gate 63b a low logic level signal while generating a high logic level signal when the output of the buffer 61 and the logic main control signal NORMAL are high logic level.

The third AND gate 63c receives the output signal of the buffer 61 and the main memory control signal MEMTEST. If the output signal of the buffer 61 or the memory main control signal MEMTEST is at a high logic level, generates the third AND gate 63c a signal at high logic level.

The memory controller 65 includes a first and a second multiplexer 65a . 65b , As the first multiplexer 65a one with two inputs and one output is used. The first multiplexer 65a receives the output of the first AND gate 63a and the output signal of the logic circuit 15 from 1 and is controlled by the main control signals NORMAL and MEMTEST to the output signal of the first AND gate 63a and the output signal of the logic circuit 15 from 1 to the first memory 17 from 1 transferred to. Here, the first multiplexer transmits 65a when the logic master control signal NORMAL is active, that of the logic circuit 15 from 1 generated signal to the first memory 17 from 1 while he's the one from the first AND gate 63a generated signal to the first memory 17 from 1 transmits when the memory main control signal MEMTEST is active.

As the second multiplexer 65b one with two inputs and one output is used. The second multiplexer 65b receives the output of the third AND gate 63c and the output signal of the logic circuit 15 from 1 and is controlled by the main control signals NORMAL and MEMTEST to the output of the third AND gate 63c and the output signal of the logic circuit 15 from 1 to the second memory 19 from 1 transferred to. In the process, the second multiplexer transmits 65b a signal generated by the logic to the second memory 19 from 1 when the logic master control signal NORMAL is active while receiving the signal from the third AND gate 63c generated signal to the second memory 19 from 1 transmits when the memory main control signal MEMTEST is active.

7 shows a block diagram of a realization of the first memory data control unit 55 from 5 , This first storage data control unit 55 includes a first input / output buffer 71 , a first logic gate 73 , a first memory controller 75 , a first output control 77 and a first output buffer controller 79 , The first input / output buffer 71 includes a first input buffer 71a and a first output buffer 71b ,

The first input buffer 71a receives the memory data signal DQ1i and transmits the output signal to the first logic gate 73 , The first input buffer 71a changes the voltage level of the memory data signal DQ1i. For example, it converts a TTL voltage level to a CMOS voltage level.

The first output buffer 71b is determined by the first output buffer control 79 controlled to the output signal of the first output control 77 forward to the outside. This becomes the first output buffer 71b when the output of the first output buffer control 79 is active, to activate, the output signal of the first output control 77 to forward to the outside while the first output buffer 71b the output of the first output controller 77 does not conduct to the outside when the output of the first output buffer control 79 is inactive.

The first logic gate 73 receives the output of the first input buffer 71a and transmits the output signal to the first memory controller 75 , The first logic gate 73 includes a first and second AND gate 73a . 73c ,

The first AND gate 73a receives the output of the first input buffer 71a and the main memory control signal MEMTEST. If the output of the first input buffer 71a or the memory main control signal MEMTEST is at logic low level, generates the first AND gate 73a a low logic level signal while generating a high logic level signal when the output of the first input buffer 71a and the memory main control signal MEMTEST are at a high logic level.

The second AND gate 73c receives the output of the first input buffer 71a and the main control signal NORMAL and transmits the output signal to the logic circuit 15 from 1 , If the output of the first input buffer 71a or the main control signal NORMAL is at logic low level, generates the second AND gate 73c a low logic level signal while generating a high logic level signal when the output of the first input buffer 71a and the main control signal NORMAL are at a high logic level.

The first memory controller 75 includes a multiplexer with two inputs and one output. The first memory controller 75 receives the output of the first AND gate 73a and the output signal of the logic circuit 15 from 1 and is controlled by the main control signals NORMAL and MEMTEST to the output signal of the first AND gate 73a and the output signal of the logic circuit 15 from 1 to the first memory 17 from 1 transferred to. In this case, the first memory controller transmits 75 when the logic main control signal NORMAL is active, from the logic circuit 15 of the 1 generated signals to the first memory 17 from 1 while coming from the first AND gate 73a generated signals to the first memory 17 of the 1 transmits when the memory main control signal MEMTEST is active.

The first output control 77 includes a multiplexer with two inputs and one output. The first output control 77 receives from the logic circuit 15 of the 1 and the first memory 17 from 1 generated signals and transmits the output signal to the first output buffer 71b , The first output control 77 is controlled by the main control signals NORMAL and MEMTEST. Here, the first output control transfers 77 from the logic circuit 15 of the 1 generated signals to the first output buffer 71b when the logic main control signal NORMAL is active while from the first memory 17 of the 1 generated signals to the first output buffer 71b transmits when the memory main control signal MEMTEST is active.

The first output buffer control 79 includes a third AND gate 79a , a first logic gate 79c and a first NAND gate 79d , The third AND gate 79a receives the main memory control signal MEMTEST and the first output buffer enable signal TRST1. When the memory main control signal MEMTEST or the first output buffer enable signal TRST1 is at logic low level, the third AND gate generates 79a a low logic level signal while generating a high logic level signal when both the memory master control signal MEMTEST and the first output buffer enable signal TAST1 are high logic level.

The first logic gate 79c receives the output of the third AND gate 79a and the main control signal NORMAL. When the output signal of the third AND gate 79a or the logic main control signal NORMAL is at a high logic level, generates the first logic gate 79c a high logic level signal while generating a low logic level signal when the output of the third AND gate 79a and the main control signal NORMAL are at a low logic level.

The first NAND gate 79d receives the output signal of the first logic gate 79a and the supply voltage VCC, and transmits the output signal to a control terminal of the first output buffer 71b , The first NAND gate 79d thus serves to transmit the output signal of the first logic gate to the control terminal of the first output buffer 71b , In this case, the first NAND gate generates 79d High logic level signals when the output of the first logic gate 79c is at a low logic level while generating low logic level signals when the output of the first logic gate 79c is at a high logic level. When the output of the first NAND gate 79d is at low logic level, ie is active, is the first output buffer 71d is activated while it is disabled when the output signal of the NAND gate 79d is at a high logic level, ie is inactive.

8th shows in block diagram an implementation of the second memory data control unit 57 from 5 , This second memory data controller 57 includes a second input / output buffer 81 , a second logic gate 83 , a second memory controller 85 , a second output control 87 and a second output buffer controller 89 , The second input / output buffer 81 has a second input buffer 81a and a second output buffer 81b on.

The second input buffer 81a receives the memory data signal DQ2i and transmits the output signal to the second logic gate 83 , The second input buffer 81a changes the voltage level of the memory data signal DQ1i. For example, it converts a TTL voltage level to a CMOS voltage level.

The second output buffer 81b is through the second buffer control 89 controls and transmits the output of the second output control 87 outward. In this case, the second output buffer transmits 81b the output of the second output controller 87 to the outside when the output of the second output buffer control 89 is active while it is inactive when the output of the second output buffer control 89 is inactive so that it then outputs the output of the second output controller 87 does not forward to the outside.

The second logic gate 83 receives the output of the second input buffer 81a and transmits the output signal to the second memory controller 85 , The second logic gate 83 has a fourth and fifth AND gate 83a . 83c on.

The fourth AND gate 83a receives the output of the second input buffer 81a and the main memory control signal MEMTEST. If the output of the second input buffer 81a or the memory main control signal MEMTEST is at logic low level, generates the fourth AND gate 83a a low logic level signal while generating a high logic level signal when the output of the second input buffer 81a and the memory main control signal MEMTEST are at a high logic level.

The fifth AND gate 83c receives the output of the second input buffer 81a and the main control signal NORMAL and transmits the output signal to the logic circuit 15 from 1 , If the output of the second input buffer 81a or the main control signal is at a low logic level, generates the fifth AND gate 83c a low logic level signal while generating a high logic level signal when the output of the second input buffer 81a and the main control signal NORMAL are at a high logic level.

The second memory controller 85 contains a multiplexer with two inputs and one output. The second memory controller 85 receives the output of the fourth AND gate 83a and the output of the logic circuit 15 from 1 and is controlled by the main control signals NORMAL and MEMTEST to the output signal of the fourth AND gate 83a or the output signal of the logic circuit 15 from 1 to the second memory 19 from 1 transferred to. In this case, the second memory controller transmits 85 from the logic circuit 15 of the 1 generated signals to the second memory 19 of the 1 when the logic skin control signal NORMAL is active while from the fourth AND gate 83a generated signals to the second memory 19 of the 1 transmits when the memory main control signal MEMTEST is active.

The second output control 87 contains a multiplexer with two inputs and one output. The second output control 87 receives from the logic circuit 15 of the 1 and from the second memory 19 of the 1 generated signals and transmits the output signal to the second output buffer 81b , The second output control 87 is controlled by the main control signals NORMAL and MEMTEST. Here transmits the second output control 87 from the logic circuit 15 of the 1 generated signals to the second output buffer 81b when the logic main control signal NORMAL is active while being from the second memory 19 of the 1 generated signals to the second output buffer 81b transmits when the memory main control signal MEMTEST is active.

The second output buffer control 89 includes a sixth AND gate 89a , a second logic gate 89c and a second NAND gate 89d ,

The sixth AND gate 89a receives the memory main control signal MEMTEST and that of the second memory 19 of the 1 generated output buffer enable signal TRST2. When the main control signal MEMTEST or the output buffer enable signal TRST2 is at logic low level, the sixth AND gate generates 89a a low logic level signal while generating a high logic level signal when both the master control signal MEMTEST and the output buffer enable signal TRST2 are high logic level.

The second logic gate 89c receives the output of the sixth AND gate 89a and the main control signal NORMAL. When the output of the sixth AND gate 89a or the main control signal NORMAL is at a high logic level, generates the second logic gate 89c a high logic level signal while producing a low logic level signal when both the output of the sixth AND gate 89a and the main control signal NORMAL are at low level.

The second NAND gate 89d receives the output signal of the second logic gate 89c and the supply voltage VCC, and transmits the output signal to a control terminal of the second output buffer 81b , The second NAND gate 89d thus serves to transmit the output signal of the second Logic gate to the control terminal of the second output buffer 81b , In this case, the second NAND gate generates 89d a high logic level signal when the output of the second logic gate 89c is at a low logic level while generating a low logic level signal when the output of the second logic gate 89c is at a high logic level. When the output signal of the second NAND gate 89d is at low logic level, ie active, becomes the second output buffer 81b is activated while it is deactivated when the output signal of the NAND gate 89d is at a high logic level, ie is inactive.

9 illustrates in block diagram a second embodiment of a semiconductor device with memory-logic combination. This semiconductor device 107 with memory-logic combination includes a first to sixth contact point 111 to 116 , a first built-in self-testing unit 121 , a second built-in self-testing unit 123 , a first store 125 , a second memory 127 and a logic circuit 129 , External signals are in the semiconductor device 107 with memory-logic combination via the first to fourth contact point 111 to 114 and the memory-logic combination semiconductor device outputs signals to the outside via the fifth and sixth pads 115 . 116 from.

Specifically, in this case, an external first and second clock signal Clock_A and Clock_B via the first and second contact point 111 . 112 in the semiconductor device 107 entered with memory-logic combination, and via the third and fourth contact point 113 . 114 become an external first and second test enable signal Enable_A and Enable_B in the semiconductor device 107 entered with memory-logic combination. Furthermore, about the fifth and sixth contact point 115 . 116 a first and second test result signal Error_A and Error_B from the semiconductor device 107 delivered with memory-logic combination to the outside.

The first built-in self-test unit 121 receives the first clock signal Clock_A and the first enable signal Enable_A and generates first control signals 131 that is, a row address strobe signal RASB, a column address strobe signal CASB, an address signal Addr, a write enable signal WEB, and an input data signal Data_in to supply to the first memory 125 supply. From the first store 125 a first output data signal Dataout_A is received to deliver the first test result signal Error_A to the fifth pad 115 leave.

The second built-in self-test unit 123 receives the second clock signal Clock_B and the second test enable signal Enable_B and generates second control signals 133 to give it to the second store 127 namely, a row address strobe signal RASB1, a column address strobe signal CASB, an address signal Addr, a write enable signal WEB, and an input data signal Data_in. A second output data signal Dataout_B is from the second memory 127 receive the second test result signal Error_B to the sixth pad 116 leave.

The first and second memory 125 . 127 for data storage includes input ports connected to the first and second built-in self-testing unit, respectively 121 . 123 are connected, as well as with the first and second self-testing unit 121 . 123 connected output terminals. The first store 125 generates the first output data signals Dataout_A in response to the first control signals 131 , and the second memory 127 generates the second output data signals Dataout_B in response to the second control signal 133 , The logic circuit 129 controls the first and second memories 125 . 127 ,

12 shows a timing diagram of signals for testing a semiconductor device with memory-logic combination according to the second to fourth embodiments of the invention. How out 12 to detect the first clock signal Clock_A or the second clock signal Clock_B and the first test enable signal Enable_A or the second test enable signal Enable_B are generated, after which the first and second control signals 131 . 133 be generated. After a predetermined time period T1, the first or the second output data signal Dataout_A, Dataout_B is then generated. Then, after a predetermined period of time T2, the first or second test result signal Error_A and Error_B are generated.

With reference to 12 below is the operation of the semiconductor device 107 with memory-logic combination according to 9 explained. The mode of operation for testing the first memory 125 over the first built-in self-testing unit 121 is equivalent to testing the second memory 127 via the second built-in self-test unit 123 , Accordingly, the explanation may be that of the operation for testing the first memory 125 over the first built-in self-testing unit 121 be limited.

When the first test enable signal Enable_A is asserted, ie high logic level, the first built-in self-test unit is 121 activated. In this state, when the first clock signal Clock_A is activated at a high logic level, the first built-in self-test unit is used 121 the first control signal 131 generated to the first memory 125 supply. Then the first memory is generated 125 after a predetermined time T1, as in 12 shown, the first output data signal Dataout_A in response to the first control signal 131 to make it the first built-in self-testing unit 121 supply. In the 12 The predetermined time T1 shown represents a period for activating and operating the first memory 125 as soon as the first control signals 131 and output the result as the first output data signal Dataout_A. The first built-in self-test unit 121 analyzes the first output data signal Dataout_A and generates the result as the first test result signal Error_A, to the fifth pad 115 be forwarded. The first built-in self-test unit 121 needed, as in 12 a period of time T2 to analyze the first output data signal Dataout_A and to output the first test result signal Error_A. The first test result signal Error_A determines if the function of the first memory 125 normal or not.

When the number of memories in the semiconductor device 107 of the 9 As the number of built-in self-test units, clock signals, and test-enable signals increases to be equal to the number of memories, it increases. When the first and second test enable signals Enable_A and Enable_B are activated simultaneously, the first and second memories become 125 . 127 tested simultaneously. Accordingly, the period of time for testing the first and second memories 125 . 127 the same size as the one for testing a memory. In addition, conventional contact points become common without the first to sixth contact points 111 to 116 used, which reduces the number of contact points and thus the production cost.

10 shows a third embodiment of a combined semiconductor memory and logic device according to the invention 207 , The semiconductor device 207 with memory-logic combination includes a first to fifth contact point 211 . 213 . 214 . 215 . 216 , a first and second, built-in self-testing unit 221 . 223 , a first and second memory 225 . 227 and a logic circuit 229 ,

External signals are injected into the semiconductor device 207 with memory-logic combination via the first to third contact point 211 . 213 . 214 input, and signals of the semiconductor device 207 with memory logic combination are via the fourth and fifth contact point 215 . 216 delivered to the outside.

More specifically, about the first contact point 211 an external clock signal Clock_A in the semiconductor device 207 entered with memory-logic combination, and via the second and third contact point 213 . 214 become an external first and second test enable signal Enable_A and Enable_B in the semiconductor device 207 equipped with memory logic combinatin. Furthermore, the semiconductor device 207 with memory-logic combination the first and second test result signal Error_A and Error_B via the fourth and fifth contact point 215 . 216 delivered to the outside.

The first built-in self-test unit 221 receives the clock signal Clock_A and the first test enable signal Enable_A and generates first control signals 231 to give it to the first store 225 namely, a row address strobe signal RASB, a column address strobe signal CASB, an address signal Addr, a write enable signal WEB, and an input data signal Data_in. Furthermore, from the first memory 225 Receive the first output data signal Dataout_A to the first test result signal Error_A to the fourth contact point 215 leave.

The second built-in self-test unit 223 receives the clock signal Clock_A and the second test enable signal Enable_B and generates second control signals 233 to give it to the second store 227 namely, a row address strobe signal RASB, a column address strobe signal CASB, an address signal Addr, a write enable signal WEB, and an ice dispensing data signal Data_in. The second output data signal Dataout_B is from the second memory 227 receive the second test result signal Error_B to the fifth pad 216 leave.

The first and second memory 225 . 227 for data storage includes with the first and the second built-in self-testing unit 221 . 223 connected input terminals and with the first and the second built-in self-testing unit 221 . 223 connected output terminals. The first store 225 generates the first output data signal Dataout_A in response to the first control signals 231 while the second memory 227 the second output data signal Dataout_B in response to the second control signals 233 generated. The logic circuit 229 controls the first and second memories 225 . 227 ,

The operation of the semiconductor device 207 with memory-logic combination according to 10 is referred to below with reference to 12 explained. In the semiconductor device 207 with memory logic combination of 10 is the operation for testing the first memory 225 over the first built-in self-testing unit 221 equivalent to testing the second memory 227 via the second built-in self-test unit 223 , Therefore, in the present case, the explanation of the operation in testing the first memory suffices 225 over the first built-in self-testing unit 221 ,

When the first test enable signal Enable_A is asserted, ie high logic level, the first built-in self-test unit is 221 activated. In this state, when the clock signal Clock_A is activated at high logic level, the first control signals 231 from the first built-in self-test unit 221 generated to the first memory 225 supply. The first memory then generates 225 after a predetermined period T1 according to 12 the first output data signal Dataout_A in response to the first control signals 231 to make it the first built-in self-testing unit 221 supply. The predetermined period T1 of 12 provides a period of time to activate and operate the first memory 225 as soon as the first control signals 231 and outputting the result as the first output data signal Dataout_A. The first built-in self-test unit 221 analyzes the first output data signal Dataout_A and generates the result as the first test result signal Error_A to make it the fourth contact point 215 supply. The time period for generating the first test result signal Error_A after generation of the output data signal Dataout_A is the time duration T2 of 12 , The first test result signal Error_A determines if the function of the first memory 225 normal or not.

When the number of memories in the semiconductor device 207 from 10 As the number increases, the number of built-in self-test units and test-enable signals increases to be the same size as that of the memories. However, a common clock signal is used.

When the first and second test enable signals Enable_A and Enable_B are activated simultaneously, the first and second memories become 225 . 227 tested simultaneously. Accordingly, in the case that the first and second test enable signals Enable_A and Enable_B are activated simultaneously, the time period for testing the first and second memories is 225 . 227 the same size as testing a memory, which reduces the test duration. In addition, conventional pads are shared without addition of the first to fifth pads 211 . 213 . 214 . 215 . 216 , which reduces the number of contact points and the production cost.

11 shows a fourth inventive semiconductor device 307 with memory-logic combination. This combined semiconductor memory and logic device 307 includes a first to fifth contact point 311 . 313 . 314 . 315 . 316 , a built-in self-testing unit 321 , a first and second memory 325 . 327 and a logic circuit 329 ,

External signals are in the semiconductor device 307 with memory-logic combination via the first to third contact point 311 . 313 . 314 input, and signals from the semiconductor device 307 with memory logic combination are via the fourth and fifth contact point 315 . 316 delivered to the outside.

More specifically, in the semiconductor device 307 with memory-logic combination an external clock signal Clock_A via the first contact point 311 and an external first and second test enable signal Enable_A and Enable_B are input to the semiconductor device 307 with memory-logic combination via the second and third contact point 313 . 314 entered. In addition, the first and second test result signals Error_A and Error_B of the semiconductor device 307 with memory-logic combination via the fifth and sixth contact point 315 . 316 delivered to the outside.

The built-in self-test unit 321 receives the clock signal Clock_A as well as the first and second test enable signals Enable_A and Enable_B, and generates first and second control signals 331 . 333 to the first or second memory 325 . 327 namely, a row address strobe signal RASB, a column address strobe signal CASB, an address signal Addr, a write enable signal WEB, and an input data signal Data_in. The first and second output data signal Dataout_A and Dataout_B are from the first and second memory, respectively 325 . 327 received to the first and second test result signal Error_A and Error_B to the fourth and fifth contact point 315 . 316 leave. The second control signals 333 If necessary, the first control signals 331 share.

The first and second memory 325 . 327 for data storage together include the built-in self-testing unit 321 connected input ports and shared with the built-in Self-test unit 321 connected output ports. The first store 325 generates the first output data signal Dataout_A in response to the control signals 331 , and the second memory 327 generates the second output data Dataout_B in response to the second control signals 333 , The logic circuit 329 controls the first and second memories 325 . 327 ,

The operation of this fourth combined semiconductor memory and logic device 307 according to 11 is referred to below with reference to 12 explained.

When the first test enable signal Enable_A is asserted, ie high logic level, the built-in self-test unit is 321 activated. In this state, when the clock signal Clock_A is activated at high logic level, the built-in self-test unit 321 the first control signals 331 generated and the first memory 325 fed. The first store 325 then generates after a predetermined period T1 according to 12 the first output data signal Dataout_A in response to the first control signals 331 and leads it to the built-in self-testing unit 321 to. The predetermined period T1 of 12 is a period of time for activating and operating the first memory 325 as soon as the first control signals 331 and outputting the result as the first output data signal Dataout_A. The built-in self-test unit 321 analyzes the first output data signal Dataout_A and as a result generates the first test result signal Error_A to the fourth contact point 315 to lead. The time period T2 of 12 is needed to generate the first test result signal Error_A after generation of the output data signal Dataout_A. The first test result signal Error_A determines if the function of the first memory 325 normal or not.

The operation for testing the function of the second memory 327 is equivalent to testing the first memory 325 , In the process, the clock signal Clock_A and the built-in self-test unit become 321 for the operation for testing the function of the second memory 327 used together. Accordingly, when the first and second test enable signals Enable_A and Enable_B are asserted together, the first and second memories become 325 . 327 tested together. Therefore, the period of time for testing the first and second memories 325 . 327 similar to testing a memory, which reduces the test duration. In addition, conventional pads are shared without adding the first to fifth pads 311 . 313 . 314 . 315 and 316 , which reduces the number of contact points and the production cost.

When the number of memories in the semiconductor device of 11 As the number of test enable signals increases, the number of test enable signals increases to equal the number of memories. However, a built-in self-test unit and a clock signal are shared.

13 FIG. 10 shows a flowchart of a test method for the combined semiconductor memory and logic device according to the invention. According to 13 For example, the test method for a memory of the semiconductor device with memory-logic combination includes a step 401 to activate a first memory, a step 411 to activate a second memory, one step 421 to read data from the first memory, a step 431 for reading data from the second memory, a step 441 to write data to the first memory, a step 451 to write data to the second memory, one step 461 to reread data from the first memory, a step 471 to reread data from the second memory, a step 481 for preloading the first memory and a step 491 for precharging the second memory.

In step 401 to activate the first memory becomes the built-in self-test unit 321 activated by external signals, and the built-in self-test unit 321 activates the first memory 325 , In step 411 to activate the second memory activates the built-in self-test unit 321 the second memory 327 , In step 421 The built-in self-test unit reads to read data from the first memory 321 Data stored in the first memory 325 are stored. In step 431 for reading data from the second memory, the built-in self-test unit reads 321 Data stored in the second memory 327 are stored. In step 441 to write data to the first memory writes the built-in self-test unit 321 "1" or "0" data in the first memory 325 , In step 451 to write data to the second memory writes the built-in self-test unit 321 "1" or "0" data in the second memory 327 ,

In step 461 to read data from the first memory again, the built-in self-test unit reads 321 Data in the first memory 325 were written. During normal operation of the first memory 325 Reference data in the built-in self-test unit 321 saved. Accordingly, in the built-in self-test unit 321 those from the first store 325 read data with is compared with the reference data, and when the measured data is different from the reference data, an error signal is generated and sent out. In step 471 to read data from the second memory again, the built-in self-test unit reads 321 Data stored in the second memory 327 were written. The second memory 327 read data are in the built-in self-test unit 321 is compared with the reference data, and when the read data is different from the reference data, an error signal is generated and sent out.

In step 481 for precharging the first memory, which is a pre-stage for writing data to the first memory 325 or to read from in the first memory 325 stored data becomes the first memory 325 summoned. In step 491 for precharging the second memory 327 , which is a preliminary stage for writing data to the second memory 327 or to read from in the second memory 327 stored data becomes the second memory 327 summoned.

By the test method according to the invention, the first and second memory 325 . 327 tested after a nesting process. If the first and second memory 325 . 327 16M synchronous memories, a test cycle can be run for the first and second memories 325 . 327 using a 14N-Y-March algorithm by Equation 1 below assuming that a data bus transfers 64 bits. Test Cycle = Data Format x Stage x 128K = 2 x 6 x 128K = 1,572,864 (Cycle Time) Equation 1

It will be to simultaneously carry out each stage with respect to the first and second memory 325 . 327 according to an interleaving method 11 Cycles as shown in Table 3 below. Table 3 1 2 3 4 5 6 7 8th 9 10 11 1 memory block active ready ready ready read ready write ready read again subpoena ready 2nd memory block ready ready active ready ready read ready read ready read subpoena input data 1.Dateneingabe 2.Dateneingabe output data 1.Dateneingabe 2.Dateneingabe

Accordingly, the total test time for the first and second memories can be made 425 . 427 by expressing Equation 2 below. Test duration = 1,572,864 x 11 = 325,301,504 (cycle time). Equation 2

The test duration according to the invention according to equation 2 is thus only about 55% of the conventional test duration. This means that according to the invention the memory test duration is reduced by about 45% compared to the conventional memory test duration. The interleaving method according to the invention can also be applied to a combined semiconductor memory and logic device having three or more memories, thereby considerably reducing the memory test duration.

According to the invention, an internal memory can be tested using conventional pads without adding pads, which avoids an increase in manufacturing overhead. In addition, the memory testing time is significantly reduced, regardless of the number of memories.

Claims (41)

Semiconductor device with memory-logic combination, comprising: - a plurality of memories ( 17 . 19 ), - a contact point ( 8th ) receiving memory control signals (PC) for controlling the plurality of memories, - another contact point ( 7 ) to which memory data signals (DQI) received or generated by the plurality of memories are applied, - a logic circuit ( 15 ) for controlling the plurality of memories and - a memory test control circuit connected to the further contact point, the logic circuit and the plurality of memories ( 13 ) for transmitting the memory control signals and the memory data signals to the plurality of memories when the plurality of memories are tested, in response to a test control signal (TESTMD0, TESTMD1) and for transferring the memory control signals and the memory data signals to the logic circuit during a normal operation. The semiconductor device of claim 1, wherein the plurality of memories consists of a first and a second memory. The semiconductor device according to claim 2, wherein the memory test control circuit includes: a memory control signal control unit 25 ) for transferring the memory control signals to the first and second memories and to the logic circuit, - a memory data controller ( 27 ) for transmitting the memory data signals to the first and second memories and the logic circuit or for transmitting the memory data signals generated by the first and second memory and the logic circuit to the further contact point and a main control signal generator connected to the memory control signal control unit and the memory data controller ( 23 ) for controlling the transfer of the memory control signals to the first and second memories and logic circuitry in response to the test control signal, transmitting the memory data signals to the first and second memories and the logic circuitry, and transmitting the memory data signals generated by the first and second memories and the logic circuitry to the further pad. Semiconductor device having a memory-logic combination, comprising the following elements: - a plurality of contact points ( 111 to 114 ) to which one or more external clock signals and test enable signals are applied, - a plurality of further contact points ( 115 . 116 ), - at least two memories in which data are stored, and - one or more built-in self-testing units ( 121 . 123 ) for testing the functions of the memories in response to the clock signals and the test enable signals and for sending the results to the plurality of other pads. A semiconductor device according to claim 4, comprising: - first and second contact points ( 111 . 112 ), to which a first or second external clock signal (Clock_A, Clock_B) are applied, - a third and fourth contact point ( 113 . 114 ) to which a first and a second external test enable signal (Enable_A, Enable_B) are applied, - a fifth and sixth contact point ( 115 . 116 ), - a first and second memory ( 125 . 127 ) in which data is stored, A first built-in self-testing unit ( 121 ) connected to the first memory and the first and third pads to test functions of the first memory in response to the first clock signal and the first test enable signal and send the results to the fifth pad, and a second built-in self-test unit ( 123 ) coupled to the second memory, second and fourth pads for testing functions of the second memory in response to the second clock signal and the second test enable signal and transmitting the results to the sixth pad. Semiconductor component according to claim 4, comprising: - a first contact point ( 211 ), to which an external clock signal (Clock_A) is applied, - a second and third contact point ( 213 . 214 ) to which a first and second external test enable signal (Enable_A, Enable_B) are applied, - a fourth and fifth contact point ( 215 . 216 ), - a first and second memory ( 225 . 227 ), in which data are stored, - a first built-in self-testing unit ( 221 ) connected to the first memory and the first and second pads for testing functions of the first memory in response to the clock signal and the first test enable signal and sending the results to the fourth pad, and a second built-in self-testing unit ( 223 ) coupled to the second memory and the first and third pads for testing functions of the second memory in response to the clock signal and the second test enable signal and transmitting the results to the fifth pad. Semiconductor component according to claim 4, comprising: - a first contact point ( 311 ), to which an external clock signal (Clock_A) is applied, - a second and third contact point ( 313 . 314 ), to which a first or second test enable signal (Enable_A, Enable_B) are applied, - a fourth and fifth contact point ( 315 . 316 ), - a first and second memory ( 325 . 327 ), in which data is stored, and - a built-in self-testing unit ( 321 ) connected to the first memory, the second memory, and the first to third pads for testing functions of the first and second memories in response to the clock signal and the first and second test enable signals and transmitting the results to the fourth and fifth pads, respectively , A semiconductor device according to any one of claims 1 to 7, wherein the memories are formed by DRAM banks. A memory test control circuit for a semiconductor device according to any one of claims 1 to 8, wherein the memory test control circuit is connected to a pad, another pad, a logic circuit, and first and second memories to transfer memory control signals and memory data signals to the first and second memories. when the first and second memories are tested, and to transfer memory control signals and memory data signals to the logic circuit during normal operation, and comprising: a memory control signal controller (10); 25 ) for the transmission of the memory control signals to the first and second memory and to the logic circuit, - a memory data control unit ( 27 ) for transmitting the memory data signals to the first and second memories and the logic circuit or for transmitting the memory data signals generated by the first and second memory and the logic circuit to the further contact point and - a main control signal generator ( 23 ) connected to the memory control signal control unit and the memory data control unit for transmitting the memory control signals to the first and second memories and the logic circuit in response to the test control signal and the memory data signals of the first and second memories and the logic circuit to the further pad. The memory test control circuit according to claim 9, wherein the main control signal generator is one in which the output of the memory control signal control unit and that of the memory data control unit are transmitted to the first memory when the first and second test control signals are inactive, the output of the memory control signal control unit and that of Memory data control unit are transmitted to the second memory when the first test control signal is active and the second test control signal is inactive, and the output of the memory control signal control unit and that of the memory data control unit are not transmitted to the logic circuit, when the first test control signal inactive and the second test control signal is active. A memory test control circuit according to claim 9 or 10, wherein the memory control signal control unit comprises: - a buffer ( 31 ) for receiving the memory control signals, - a logic gate ( 33 ) for receiving the output signal of the buffer and for receiving the main control signals and for transmitting one of the output signals to the logic circuit, and - a memory controller ( 35 ) for receiving the output signal of the logic gate and the output signal of the logic circuit and for transmitting the output signal of the logic gate and the output signal of the logic circuit to the first and second memory in response to the main control signals. The memory test control circuit of claim 11, wherein the logic gate includes: a first AND gate ( 33a ) for receiving the output signal of the buffer and a first main control signal from the main control signal generator, for transmitting the output signal of the buffer for Memory control when the first main control signal is at a high logic level and for blocking the output signal of the buffer when the first main control signal is at a low logic level, - a second AND gate ( 33b ) for receiving the output signal of the buffer and a second main control signal from the main control signal generator, for transmitting the output signal of the buffer to the logic circuit when the second main control signal is at a high logic level, and for blocking the output signal of the buffer when the second main control signal is at low level, and - a third AND gate ( 33c ) for receiving the output of the buffer and a third main control signal from the main control signal generator, for transmitting the output of the buffer for memory control when the third main control signal is at a high logic level, and for disabling the output of the buffer when the third main control signal is at a low logic level. Memory test control circuit according to claim 11 or 12, wherein the memory control comprises the following elements: - a first multiplexer ( 35a ) for receiving the output signal of the logic circuit and the output signal of the logic gate and for transmitting the output signal of the logic circuit or the output signal of the logic gate to the first memory in response to the main control signals and - a second multiplexer ( 35b ) for receiving the output signal of the logic circuit and the output signal of the logic gate and for transmitting the output signal of the logic circuit and the output signal of the logic gate to the second memory in response to the main control signals. The memory test control circuit of any one of claims 9 to 13, wherein the memory data control unit includes: - an input / output buffer ( 41 ) to which the memory data signals are applied, - a logic gate ( 43 ) for receiving the output signal of the input / output buffer and the main control signals and for transmitting one of the output signals to the logic circuit, - a memory controller ( 45 ) for receiving the output signal of the logic gate and the output signal of the logic circuit and for transmitting the output signal of the logic gate or the output signal of the logic circuit to the first and second memory in response to the main control signals, - an output control ( 47 ) for receiving memory data signals generated by the first and second memories and the output signal of the logic circuit and for transferring the memory data signals generated by the first and second memories or the output signal of the logic circuit to the input / output buffer in response to the main control signals and - an output buffer control ( 49 ) for receiving the main control signals and the memory data signals generated by the first and second memories, for transmitting the output signal to the input / output buffer and for passing the output signal of the output control via the input / output buffer when the output signal is active, and for not forwarding the Output signal of the output controller via the input / output buffer when the output signal is inactive. The memory test control circuit of claim 14, wherein the input / output buffer includes: - an input buffer (14); 41a ) for transferring the memory data signals to the logic gate and - an output buffer ( 41b ) for transmitting the output signal of the output controller to the outside in response to the output buffer control. The memory test control circuit of claim 14 or 15, wherein the logic gate includes: a fourth AND gate ( 43a ) for receiving the output of the input / output buffer and a first main control signal, for transmitting the output of the buffer for memory control when the first main control signal is at a high logic level, and for disabling the output of the buffer when the first main control signal is at a low logic level , - a fifth AND gate ( 43b ) for receiving the output of the buffer and a second main control signal, for transmitting the output of the buffer to the logic circuit when the second main control signal is at a high logic level, and for inhibiting the output of the buffer when the second main control signal is at a low logic level, and - on sixth AND gate ( 43c ) for receiving the output of the buffer and a third main control signal, for transmitting the output of the buffer for memory control when the third main control signal is at a high logic level, and for disabling the output of the buffer when the third main control signal is at a low logic level. The memory test control circuit of any one of claims 13 to 16, wherein the memory controller includes: - a third multiplexer ( 45a ) for receiving the output signal of the logic circuit and the output signal of the logic gate and for transmitting the output signal of the logic circuit and the output signal of the logic gate to the first memory in response to the main control signals and - a fourth multiplexer ( 45b ) for receiving the output signal of the logic circuit and the output signal of the logic gate and for transmitting the output signal of the logic circuit and the output signal of the logic gate to the second memory in response to the main control signals. A memory test control circuit according to any one of claims 14 to 17, wherein the output controller is a multiplexer which receives the memory data signals and the output signal of the logic circuit generated by the first and second memories and the memory data signals generated by the first and second memories and the output signal of the logic circuit from the main control signals. The memory test control circuit of any one of claims 14 to 18, wherein the output buffer control comprises: a first logic gate ( 49a ) for receiving the main control signals for the control of the first and second memory, - a second logic gate ( 49b ) for receiving the memory data signals generated by the first and second memories, - a seventh AND gate ( 49c ) for receiving the output signals of the first and second logic gates, - a third logic gate ( 49d ) for receiving the output signal of the seventh AND gate and the main control signals for controlling the logic circuit, and - a NAND gate ( 49e ) for receiving the output signal of the third logic gate and a supply voltage and for transmitting the output signal to the input / output buffer. The memory test control circuit of claim 9, wherein the main control signal generator activates a memory main control signal when the test control signals are active and a main logic control signal when the test control signals are inactive. The memory test control circuit according to any one of claims 9 to 20, wherein as a main control signal, a first main control signal in the form of a main memory control signal and a second main control signal in the form of a logic main control signal are provided. The memory test control circuit of claim 21, wherein the memory controller includes: - A first multiplexer for receiving the output signal of the logic circuit and the output signal of the logic gate and for transmitting the output signal of the logic circuit and the output signal of the logic gate to the first memory in response to the main memory control signal and the main logic control signal and - A second multiplexer for receiving the output signal of the logic circuit and the output signal of the logic gate and for transmitting the output signal of the logic circuit and the output signal of the logic gate to the second memory in response to the main memory control signal and the main logic control signal. A memory test control circuit according to claim 21 or 22, comprising a memory data controller ( 55 ) comprising the following elements: a first input / output buffer ( 71 ) to which the memory data signals are applied, - a first logic gate ( 73 ) for receiving the output of the first input / output buffer, the main memory control signal and the main logic control signal, and for transmitting one of the output signals to the logic circuit, a first memory controller (10) 75 ) for receiving the output signal of the first logic gate and the output signal of the logic circuit and for transmitting the output signal of the first logic gate or the output signal of the logic circuit to the first memory in response to the memory main control signal and the logic main control signal, - a first output control ( 77 ) for receiving the memory data signals generated by the first memory and the output signal of the logic circuit and for transmitting the memory data generated by the first memory or the output signal of the logic circuit to the first input / output buffer in response to the main memory control signal and the main logic control signal and A first output buffer control ( 79 ) for receiving the main memory control signal, the main logic control signal and the memory data signals generated by the first memory, and transmitting the output of the first input / output buffer, the output of the first output controller being forwarded through the first input / output buffer when the output of the first Output buffer control is active, while the output signal of the first output control is not forwarded by the first input / output buffer when the output signal of the first output buffer control is inactive. The memory test control circuit of claim 23, wherein the first input / output buffer includes: a first input buffer (14); 71a ) for transmitting the memory data signal to the first logic gate, and - a first output buffer ( 71b ) for transmitting the output signal of the first output controller outward in response to the first output buffer control. The memory test control circuit of claim 23 or 24, wherein the first logic gate includes: - a first AND gate ( 73a ) for receiving the output of the first input / output buffer and the memory main control signal, for transmitting the output of the first input / output buffer to the first memory controller when the memory main control signal is at a high logic level, and for disabling the output of the first input / output Buffer when the memory main control signal is at logic low level, and - a second AND gate ( 73c ) for receiving the output of the first input / output buffer and the logic main control signal, for transmitting the output of the first input / output buffer to the logic circuit when the logic main control signal is at a high logic level, and for inhibiting the output of the first input / output buffer when the logic main control signal is at a low logic level. The memory test control circuit according to any one of claims 23 to 25, wherein the first memory controller is constituted by a multiplexer receiving the output signal of the logic circuit and the output signal of the first logic gate and the output signal of the logic circuit and the output signal of the first logic gate in response from the main memory control signal and the main logic control signal to the first memory. A memory test control circuit according to any one of claims 23 to 26, wherein the first output controller is constituted by a multiplexer receiving the memory data signals and the output signal of the logic circuit generated by the first memory and the memory data signals generated by the first memory or the output signal of the logic circuit in response to the main memory control signal and from the main logic control signal to the first input / output buffer. The memory test control circuit of any one of claims 23 to 27, wherein the first output buffer control includes: a third AND gate ( 79a ) for receiving the memory main control signal and the memory data signals generated by the first memory, - a first logic gate ( 79c ) for receiving the output signal of the third AND gate and the main control signal, and - a first NAND gate ( 79d ) for receiving the output signal of the first logic gate and a supply voltage. A memory test control circuit as claimed in any one of claims 23 to 28, wherein a second memory data controller is provided with: - a second input / output buffer ( 81 ) to which memory data signals are applied, - a second logic gate ( 83 ) for receiving the output signal of the second input / output buffer, the main memory control signal and the main logic control signal, and for transmitting one of the output signals to the logic circuit, - a second memory controller ( 85 ) for receiving the output signal of the second logic gate and the output signal of the logic circuit and for transmitting the output signal of the second logic gate or the output signal of the logic circuit to the second memory in response to the memory main control signal and the logic master control signal, - a second output control ( 87 ) for receiving memory data signals generated by the second memory and the output signal of the logic circuit and for transmitting the second of the memory Memory generated memory data signals or the output signal of the logic circuit to the second input / output buffer in response to the memory main control signal and the main logic control signal and - a second output buffer control ( 89 ) for receiving the main memory control signal, the main logic control signal and the memory data signals generated from the second memory to the second input / output buffer, the output of the second output controller being forwarded via the second input / output buffer when the output of the second output buffer control is active, while the output signal of the second output controller is not forwarded through the second input / output buffer when the output of the second output buffer controller is inactive. The memory test control circuit of claim 29, wherein the second input / output buffer includes: a second input buffer (14); 81a ) for transferring the memory data signal to the second logic gate, and - a second output buffer ( 81b ) for transmitting the output signal of the second output controller to the outside in response to the second output buffer controller. The memory test control circuit of claim 29 or 30, wherein the second logic gate includes: a fourth AND gate ( 83a ) for receiving the output of the second input / output buffer and the memory main control signal, for transmitting the output of the second input / output buffer to the second memory controller when the memory main control signal is at a high logic level, and for disabling the output of the second input / output Buffer when the memory main control signal is at a low logic level, and - a fifth AND gate ( 83c ) for receiving the output of the second input / output buffer and the main control signal, for transmitting the output of the second input / output buffer to the logic circuit when the main control signal is at a high logic level, and for inhibiting the output of the second input / output buffer when the main control signal is at a low logic level. A memory test control circuit according to any one of claims 29 to 31, wherein the second memory controller consists of a multiplexer receiving the output of the logic circuit and the output of the second logic gate and the output of the logic circuit and the output of the second logic gate in response to Main memory control signal and from the main logic control signal to the second memory transmits. A memory test control circuit according to any one of claims 29 to 32, wherein the second output controller is a multiplexer which receives the memory data signals and the output signal of the logic circuit generated by the second memory and the memory data signals generated by the second memory or the output signal of the logic circuit in response to the main memory control signal and from the main logic control signal to the second input / output buffer. A memory test control circuit according to any of claims 29 to 33, wherein said second output buffer control includes: - a sixth AND gate ( 89a ) for receiving the memory main control signal and the memory data signals generated by the second memory, - a second logic gate ( 89c ) for receiving the output signal of the sixth AND gate and the main control signal, and - a second NAND gate ( 89d ) for receiving the output signal of the second logic gate and a supply voltage. A memory test method for a combined semiconductor memory and logic device having a built-in self-test unit connected to an external terminal and a plurality of memories, characterized by the steps of: a) writing data in the built-in self-test unit and the multiple memory and b) reading data stored in the plurality of memories by the built-in self-test unit. The memory test method of claim 35, wherein said step a of writing data includes the substeps of: a1) activating the multiple memories, a2) read the data stored in the plurality of memories by the built-in self-test unit and a3) Write the data into the multiple memories by the built-in self-test unit. The memory test method according to claim 36, wherein in step a1 for activating the plurality of memories, the built-in self-test unit is activated to activate the plurality of memories. The memory test method according to any one of claims 35 to 37, wherein the step b of reading data includes the substeps of: b1) read the data stored in the memory by the built-in self-test unit and b2) preloading the memory. The memory test method according to any one of claims 35 to 38, wherein in the step a of writing data, the built-in self-test unit sequentially writes data into the plurality of memories. The memory test method according to any one of claims 35 to 39, wherein in the step b of reading data, the built-in self-test unit sequentially reads data from the plurality of memories. The memory test method of any one of claims 35 to 40, further characterized in that the memories are formed by DRAM banks.

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