DE19923979C2 - Ferroelectric memory with split word line structure and without plate lines - Google Patents

Description

The present invention relates to a non-volatile ferroelectric memory and in particular to a ferroelectric memory with SWL (split word line) structure without plate lines.

SWL (split word line) structures are already from classic DRAM Storage arrangements known. An example of this is in US 5,148,401 described. Here, first and second memory cell arrays are replaced by a plurality of Word lines, all of which are divided into two sections, over the first and second Memory cell arrays extend, addressed, the word line drivers in three blocks are divided.

Ferroelectric memories as non-volatile memories are e.g. B. from US 5,373,463 known. This document describes a ferroelectric non-volatile memory Above the driver line segments are arranged parallel to the word lines, with a Driver line segment to a predetermined number of memory cells in a row can be coupled.  

Furthermore, a ferroelectric static memory is known from US Pat. No. 5,680,344 Test purposes can be operated as dynamic memory. This memory has a pair of Bit lines that can be coupled to the ferroelectric capacitors via access transistors.

Ferroelectric random access memories (FRAM's) are considered to be the next ones Generation because their access speed is just as fast as that of one conventional DRAMs, but they are also able to hold data, even if their Power supply is switched off. Similar to a DRAM also come with a FRAM Capacitors are used as memory cells, however, with a FRAM they contain the capacitors a ferroelectric substance that has a high residual polarization. As a result of this property the ferroelectric substance, data is not erased even if that is applied to the capacitor electric field disappears.  

Fig. 1a shows the conventional hysteresis loop of a ferroelectric substance, while Fig. 1b shows a ferroelectric capacitor of a conventional ferroelectric memory.

According to FIG. 1a, when an electric field is switched off, the polarization induced by the electric field does not disappear, but remains at the value "d" or "a", due to the spontaneous polarization. These values "d" and "a" can be interpreted as states for the logical values "1" and "0". This creates the basis for the construction of a memory cell. In other words, if a positive voltage is present at node 1 according to FIG. 1b, state "c" shown in FIG. 1a is assumed. If, on the other hand, the voltage at node 1 in FIG. 1b is switched off, ie if the electric field E goes to the value 0, state d is assumed in FIG . On the other hand, if a negative voltage is applied to node 1 of FIG. 1b, state "f" shown in FIG. 1a is reached. If this negative voltage is returned to the value 0, the system assumes state "a" shown in FIG. 1a. Is then subsequently again a positive voltage to the bone th 1 in Fig. 1b applied, so 1 to the stand is transferred to state "b" in Fig. Occupied in turn "c" in Fig. 1, etc. Also, If there is no voltage at both ends of the capacitor, the states "a" and "d" are assumed in it. Along the hysteresis loop, the states "c" - "d" correspond to the logical value "1", while the states "a" - "f" correspond to the logical value "0".

To be able to read a data from the capacitor, the "d" state fixed to read data stored in the capacitor. traditionally, a sense amplifier is used to read a datum which is one of one Reference voltage generator generated reference voltage with one in one Main cell array compares generated voltage. In a ferroelectric ref Reference cell are two modes for generating a reference voltage on one Reference bit line used, namely a "1" polarity and a "0" polarity. As a result, the sense amplifier compares a bit line voltage of a main cell with a reference bit line voltage of a reference cell in order to Main cell to read stored information. Is the read in the same cycle  If the date is re-registered, the deleted date can be renewed.

A conventional FRAM is described below with reference to the drawing. There are so-called 1T / 1C FRAMs with one transistor and one capacitor per unit cell and so-called 2T / 2C FRAMs with two transistors and two capacitors. Figure 2 shows a conventional 1T / 1C FRAM cell array.

According to the Fig. 2 includes the conventional 1T / 1C FRAM cell array, a plurality of word lines W / L extending in one direction and are arranged parallel to one another lying at fixed intervals. Several plate lines P / L are between the word lines and parallel to them. A plurality of bit lines B1,. , ., Bn runs in a direction perpendicular to the word lines W / L and the plate lines P / L, the bit lines also being arranged parallel to one another at a fixed distance. Each transistor in a unit cell has a gate electrode connected to one of the word lines W / L, a source electrode connected to an adjacent bit line B / L, and a drain electrode connected to a first electrode of the capacitor. The second electrode of the capacitor is connected to a neighboring plate line P / L.

A driver circuit and the operation of the aforementioned conventional 1T / 1C FRAM are described below. Here, FIGS. 3a and 3b together men, the driving circuit for the conventional 1T / 1C FRAM, while Fig. 4a illustrates the timing of signals, the FRAM cell are created when writing data in a conventional 1T / 1C. In contrast, FIG. 4b shows the timing of signals which are applied when reading from a conventional 1T / 1C FRAM cell.

A circuit for driving the conventional 1T / 1C FRAM has a reference voltage generator 1 for generating a reference voltage; a reference voltage stabilizing part 2 with a plurality of transistors Q1-Q4 and a capacitor C1 for stabilizing a reference voltage on two adjacent bit lines B1 and B2, since the reference voltage cannot be supplied directly from the reference voltage generating part 1 to a sense amplifier; a first reference voltage storage part 3 with a plurality of transistors Q6-Q7 and capacitors C2-C3 for storing a logic value "1" and a logic value "0" on adjacent bit lines; a first equalization part 4 with a transistor Q5 for equalizing adjacent bit lines (in terms of voltage); a first main cell array part 5 with a plurality of transistors Q8, Q9,. , , and ferroelectric capacitors C5, C6,. , . connected to word lines W / L and plate lines P / L for storing data; a first sense amplifier 6 having a plurality of transistors Q10-Q15 and P sense amplifiers PSA for reading data in a cell selected from a plurality of cells of the main cell array part 5 by a word line; a second main cell array part 7 with a plurality of transistors Q26, Q27,. , , and capacitors C7, C8,. , . connected to different word lines and plate lines for storing data; a second reference voltage storage part 8 with a plurality of transistors Q28-Q29 and capacitors C9-C10 for storing a logic value "1" and a logic value "0" on adjacent bit lines; and a second sense amplifier part 9 with a plurality of transistors Q16-Q25 and N sense amplifiers NSA for reading data in the second main cell array part 7 .

The following is the operation of the aforementioned conventional 1T / 1C FRAM are explained. A write mode and a read mode are presented.

According to FIG. 4a, a CSBpad signal, which is a chip enable signal, is set externally from "high" to "low" when writing. The expression "high" here denotes a high logic level, while the expression "low" denotes a low logic level. A write mode enable signal WEBpad also goes from "high" to "low" so that the write mode can begin. Now address decoding starts to set a selected line from "low" to "high" in order to select a cell in this way. While the word line is kept at "high", an associated plate line P / L is set to "high" in one interval and to "low" in another interval, in that order. To write a logic "1" or "0" into a selected cell, a "high" or "low" signal is applied to the corresponding bit line, in sync with the write enable signal. If there is a "high" signal on the bit line in order to be able to write the logic value "1", the logic value "1" is written into the ferroelectric capacitor within an interval in which the word line is at "high" and that Disk signal is pulled to "low" conditions. If, on the other hand, a logic "0" is to be written, the logic value "0" is written into the ferroelectric capacitor when a signal "low" is applied to the bit line when the plate line signal is at "high". In this way, either the logical value "1" or the logical value "0" can be written or saved.

The reading operation is explained below.

As shown in FIG. 4b, the signal CSBpad, so the chip Enablesignal (chip Release Certificates besignal) externally of "high" set to "low", then all the bit lines before selection of a entspre sponding word line voltage moderately balanced, namely the fact that they pulled to "low", which he follows by a compensation signal. Thus, in FIG. 3, if a "high" signal is applied to the compensation part 4 and a "high" signal is also applied to the transistors Q19 and Q20, the bit lines are grounded by the transistors Q19 and Q20, that is to say evenly to " pulled low. The transistors Q5, Q19 and Q20 are switched off in order to switch off the corresponding bit lines. An address is decoded in order to pull the corresponding word line from "low" to "high" in order to be able to select the corresponding cell in this way. A "high" signal is then applied to the plate line of the selected cells in order to delete a data which corresponds to the logic value "1" and is stored in the FRAM. If a date corresponding to the logical value "0" is saved in the FRAM, this date is not deleted. A cell with a deleted date and a cell in which a date has not been deleted provide different signals from each other in accordance with the hysteresis loop principle mentioned above. A data supplied via the bit line is read by the sense amplifier, which therefore detects either the logical value "1" or "0". Corresponding to FIG. 1, the case of a deleted date relates to the case in which the state changes from "d" to "f". On the other hand, the case of an undeleted date concerns the case where the state changes from "a" to "f". If the sense amplifier is activated after a predetermined time, the date is amplified in the case of the deleted date in order to obtain a logic value "1". On the other hand, in the case of the undeleted date, the date is amplified to obtain a logical value "0". After the sense amplifier has amplified and outputted the signal, since the cell is to be renewed with an original date while "high" lies on the corresponding bit line, the plate line is pulled from "high" to "low" in order to become inactive.

With the conventional 1T / 1C FRAM, however, the reference cell is very often used ger used as the main memory cell, so that the state of the reference cell deteriorated quickly. This leads to an unstable reference signal or egg ner unstable reference voltage. In addition, the regulation of the refe not using the voltage regulation circuit stable enough because this circuit due to external voltage fluctuations and Noise can be influenced. To overcome these problems, has been proposed beaten, instead of the conventional 1T / 1C FRAM's already briefly above featured 2T / 2C FRAM. It indicates improved properties obviously the electrode materials, the packing density, the stability of the fer roelectric thin films and operational reliability.

Fig. 5 shows an array of conventional 2T / 2C FRAM cells, while Fig. 6a shows the timing of various signals used in writing in the conventional 2T / 2C FRAM. In contrast, FIG. 6b shows the temporal course of various signals to explain the reading mode in the conventional 2T / 2C FRAM cell.

According to the Fig. 5 is an array of conventional 2T / 2C FRAM cells from a plurality of word lines W / L, which are arranged in a direction in parallel to each other vorbestimm th intervals. A plurality of plate lines P / L each run between adjacent word lines W / L, these plate lines P / L also being parallel to one another and parallel to the word lines. A plurality of bit lines and additional bit lines B1, BB1, B2, BB2,. , , are parallel in this order and extend in a direction perpendicular to the direction of the word lines W / L and the plate lines P / L. The bit lines or additional bit lines are also at a fixed distance from one another. The gate electrodes of two transistors of a unit memory cell are connected together to an adjacent word line W / L, while the source electrodes of these transistors are each connected to an adjacent bit line B and an adjacent additional bit line BB. Each of the drain electrodes of the two transistors is connected to a first electrode of one of two capacitors of the unit cell, while the second electrodes of these capacitors are connected to an adjacent plate line P / L.

A driver circuit and its operation for controlling the Ar rays of the conventional 2T / 2C FRAM cells are described in more detail.

Different from the array of conventional 1T / 1C FRAM cells in the Ar ray of conventional 2T / 2C FRAM cells is that in the latter case the cells write and read a logical value "1" or "0". If, in accordance with FIG. 6a, a signal CSBpad, that is to say a chip enable signal, is set externally from “high” to “low”, the array is activated and at the same time a write mode enable signal WEBpad goes from “high” to “low” "to apply" high "and" low "or" low "and" high "signals to the bit line and the additional bit line, in accordance with a logical value to be written in. Address decoding then begins to set a word line for selecting a cell from "low" to "high" to select the cell. Within an interval in which the word line is kept "high", an assigned plate line P / L is set to "high" for a fixed interval and to "low" for a fixed interval, in this order. To write the logical value "1", a signal "high" is applied to a bit line Bn and a signal "low" to an adjacent additional bit line BB-n. In contrast, for writing a logic value "0", a signal "low" is applied to a bit line Bn and a signal "high" to an adjacent additional bit line BB-n. This means that either a logical value "1" or a logical value "0" can be written.

Reading data is described in more detail below.

If, according to FIG. 6b, a CSBpad signal, ie a chip enable signal, is set externally from "high" to "low", a read mode is started. Simultaneously with the change of this signal, a write mode enable signal WEBpad goes from "low" to "high", which leads to the end of the write mode and to the start of the reading mode.

Before a desired word line is selected, all bit lines are equalized and set to "low", specifically by means of a compensation signal identical to the operation with the 1T / 1C FRAM according to FIG. 3b. After the equalization to "low" has been completed, address decoding takes place to change the signal of the desired word line from "low" to "high", so that the desired cell is selected in this way. A "high" signal is also applied to a plate line of the selected cell to clear the data on the bit line and the auxiliary bit line. If the logical value "1" is written, a date in a capacitor connected to the bit line is deleted. If, on the other hand, the logical value "0" is written, a data item in a capacitor connected to the additional bit line is deleted. Depending on the data deleted on the bit line or the additional bit line, values that are different from one another are thus obtained, namely in accordance with the course of the hysteresis loop. If the data supplied via the bit line or the additional bit line is read by the sense amplifier, the data value will be either logic "1" or logic "0". After the sense amplifier has amplified and outputted the data, since the data in the cell are to be renewed, and that while the associated word line is at "high", the plate line is pulled from "high" to "low", ie disabled or deactivated.

However, the conventional FRAMs and circuits for their control have some drawbacks. Regardless of the benefit of data retention when switched off the supply voltage, separate cell plate cables are required in the FRAM derlich, which leads to a complicated layout and manufacturing process. This is unfavorable for mass production. On the other hand, the reception of the Control signals of the word lines and the plate lines to different Way when reading and writing data due to the use of separate Plate lines, which is due to the efficiency of the storage device different signal paths reduced. The reference cell is also compared read to the main memory much more often, so that their state ver deteriorated relatively quickly. This leads to the generation of an unstable Reference voltage and deteriorated operating behavior of the memory chers. The generation of a reference voltage by a voltage regulator circuit is another disadvantage because of this reference voltage due to the influence of external voltage characteristics and due to the on flow can be disturbed by noise. Last but not least, a quick to resorted to a ferroelectric memory does not take place when it is activated only a CSBpad signal (chip selection signal) is used.

The invention is therefore based on the object the ferroelectric memory with split wording tion structure so that cell plate lines are no longer required.

The solution to this problem is specified in claim 1. Advantageous embodiments of the Invention can be found in the subclaims.

In accordance with the invention, a ferroelectric memory with a split word line structure (SWL structure or partial word line structure) contains the following:
a cell array with a plurality of sub-word lines (SWL or split word lines) and a plurality of bit lines for storing data; a SWL driver (sub-word line driver) for driving each of the sub-word lines in the cell array; a plurality of sense amplifier blocks for detecting data on each of the bit lines in the cell array; an input / output bus controller as an interface between the sense amplifier blocks and data buses for outputting the data contained in each of the sense amplifier blocks and for inputting data to be written, each of the cells in the cell array having a pair of first and second partial word lines and a pair of is connected to the first and second bit lines and each of the cells in the cell array has a first transistor, the gate electrode of which is connected to a first partial word line and the source electrode of which is connected to a first bit line, a second transistor, the gate electrode of which is connected to a second partial word line and the source electrode is connected to a second bit line, a first capacitor, the first terminal of which is connected to the drain electrode of the first transistor and the second terminal of which is connected to the second partial word line, a second capacitor of which first terminal is connected to the drain Nelectrode of the second transistor is connected and the second terminal is connected to the first partial word line.

Embodiments of the invention are described below with reference to the drawing in individual explained. Show it:

FIG. 1a is a hysteresis loop of a ferroelectric substance;

1b shows the structure of a unit capacitor in the conventional ferroelectric memory.

Figure 2 shows a conventional 1T / 1C FRAM cell array;

Figures 3a and 3b together are a driving circuit for the conventional 1T / 1C FRAM.

FIG. 4a is a signal diagram for explaining the Einschreibbetriebs in a conventional 1T / 1C FRAM cell;

FIG. 4b is a signal diagram for explaining the reading operation in a conventional forth 1T / 1C FRAM cell;

Figure 5 shows an array of conventional 2T / 2C FRAM cells;

FIG. 6a is a waveform diagram for explaining the Einschreibbetriebs forth in conventional 2T / 2C FRAM cells;

Fig. 6b is a signal diagram for explaining the reading operation in conventional 2T / 2C FRAM cells;

Fig. 7 is a system block diagram of an array of cells of a ferroelectric memory rule SWL in accordance with a preferred imple mentation of the present invention;

Fig. 8 is a circuit system of an array of cells of a ferroelectric memory SWL in accordance with a first Ausführungsbei game of the present invention;

Fig. 9 is a circuit system of an array of cells of a ferroelectric memory SWL in accordance with a second Ausführungsbei game of the present invention;

FIG. 10 is a system block diagram dung a driver circuit for a ferroelectric memory rule SWL in accordance with the present OF INVENTION;

FIG. 11 is a system block diagram of a global control pulse generator in match with the first embodiment of the present invention;

FIG. 12 is a system block diagram of a global control pulse generator in match with the second embodiment of the present invention;

FIG. 13 is an operation timing chart of the first embodiment of the global control pulse generator according to the present invention;

FIG. 14 is an operation timing chart in accordance with the second exporting approximately example of the global control pulse generator according to the present invention;

Figure 15 is an operation timing chart of a third embodiment of the globa len control pulse generator according to the present invention.

FIG. 16 is an operation timing chart of a fourth embodiment of the globa len control pulse generator according to the present invention;

Fig. 17 is a circuit system of a local control pulse generator in accordance with the first embodiment of the present inven tion shown in FIG. 8;

Fig. 18 shows a circuit system of column control in accordance with the first embodiment of the present invention shown in Fig. 8;

Fig. 19 is a circuit system of a first embodiment of a Lesever stärkers and an input / output controller in accordance with the present invention shown in Fig. 8;

Fig. 20 shows a circuit system of a second embodiment of a sense amplifier and an input / output controller in accordance with the present invention shown in Fig. 8;

Fig. 21 shows a circuit system of a third embodiment of a sense amplifier and an input / output controller in accordance with the present invention of Fig. 8;

Fig. 22 shows a circuit system of a fourth embodiment of its sense amplifier and an input / output controller in accordance with the present invention of Fig. 8;

Fig. 23 is a timing chart of the local control pulse generator in a write mode in the event that a Y address is changed in Fig. 8;

Fig. 24 is a timing chart of the local control pulse generator in a read mode in case a Y address is changed in Fig. 8;

Fig. 25 is a timing chart of the local control pulse generator in a write mode when X, Z addresses are changed in Fig. 8;

Fig. 26 is a timing chart of the local control pulse generator in a read mode in case X, Z addresses are changed in Fig. 8;

Fig. 27 shows a circuit system of the local control pulse generator in accordance with the second embodiment of the present invention shown in Fig. 9;

Fig. 28 shows a circuit system of a first embodiment of a sense amplifier and an input / output controller in accordance with the present invention of Fig. 9;

Fig. 29 is a circuit system of a second embodiment of a sense amplifier and an input / output controller in accordance with the present invention of Fig. 9;

Fig. 30 is a timing chart of the local control pulse generator in a write mode when a Y address is changed in Fig. 27;

Fig. 31 is a timing chart of the local control pulse generator in a read mode when a Y address is changed in Fig. 27;

Fig. 32 is a timing chart of the local control pulse generator in a write mode in case X, Z addresses in Fig. 27 are changed;

Fig. 33 is a timing chart of the local control pulse generator in a read mode when X, Z addresses are changed in Fig. 27;

FIG. 34 is a system block diagram of an input / output array a Ferroe lektrischen SWL memory in accordance with the preferred embodiment of the present invention;

FIG. 35 is a system block diagram of a first embodiment of a Le sever stärkers in a ferroelectric memory SWL, in conformity with the invention;

FIG. 36 is a system block diagram of a second embodiment of a Le sever stärkers in a ferroelectric memory SWL, in conformity with the present invention;

FIG. 37 is a system block diagram of a third embodiment of a Le sever stärkers in a ferroelectric memory SWL, in conformity with the present invention;

FIG. 38 is a system block diagram of a fourth embodiment of a Le sever stärkers in a ferroelectric memory SWL, in conformity with the present invention;

FIG. 39 is a circuit system of a first embodiment of an input / output bus controller in a SWL ferroelectric memory in accordance with the present invention;

Fig. 40 is a circuit system of a second embodiment of a entranc be / output bus controller in a SWL ferroelectric memory in accordance with the present invention;

FIG. 41 is a circuit system of a third embodiment of a entranc be / output bus controller in a SWL ferroelectric memory in accordance with the present invention;

Fig. 42 is a circuit system of a fourth embodiment of a entranc be / output bus controller in a SWL ferroelectric memory in accordance with the present invention;

FIG. 43 is a circuit system of a fifth embodiment of a entranc be / output bus controller in a SWL ferroelectric memory in accordance with the present invention;

Fig. 44 is a circuit system of a sixth embodiment of a entranc be / output bus controller in a SWL ferroelectric memory in accordance with the present invention;

FIG. 45 is a system of a first embodiment of a data bus in accordance with the present invention;

Fig. 46 is a system of a second embodiment of a data bus in accordance with the present invention;

FIG. 47 is a system of a third embodiment of a data bus in accordance with the present invention;

FIG. 48 is a system of a fourth embodiment of a data bus in accordance with the present invention;

FIG. 49 is an operation timing chart of the input / output bus controller in keeping with a first preferred embodiment of the present invention;

Fig. 50 is an operation timing chart of the input / output bus controller in conformity with a second embodiment of the present invention; and

Fig. 51 is an operation timing diagram of the input / output bus controller in keeping with a third embodiment of the present invention.

The preferred embodiment of the present invention will be explained in more detail with reference to the drawing. The Fig. 7 shows a block diagram of an overall system of a ferroelectric memory into SpeI accordance with a preferred embodiment of the present invention in a schematic way.

According to Fig. 7, the ferroelectric memory chip of the present contains He invention in an enlarged representation SWL driver 300 (split or sub-wordline tung driver) for driving split or sub-word lines, cell array 400 for storing data and so-called cores 500 , each having a read amplifier block for reading data and an input / output bus control as an interface between an external data line and a sense amplifier block. The cell arrays 400 are located on the left and right sides of a SWL driver 300 , so that the SWL driver 300 is located in the center between two cell arrays 400 . In contrast, one of the nuclei 500 mentioned is located above and below a respective cell array 400 . A cellar ray 400 is therefore seen between two of these cores 500 in the vertical direction.

The SWL memory is explained in more detail below with reference to FIG. 8. This Fig. 8 shows a circuit of a sub-block arrays of cells of a fer roelektrischen SWL memory in accordance with a first exporting approximately example of the present invention.

According to the Fig. 8 includes a cell array of a ferroelectric memory SWL in accordance with the first embodiment of the invention vorlie constricting n-SWL1 a plurality of partial or split word lines, SWL2-n. , ., SWL2-n + 3, which extend in one direction and are arranged at fixed distances from each other in parallel. Furthermore, a plurality of bit lines are bit-n, bit-n + 1. , ., RBit-n, RBit-n + 1 are present, which extend in a direction that is vertical to the direction of the SWLs, and which are also arranged parallel to each other at a distance. A unit cell is each formed by a pair of adjacent SWLs and two adjacent bit lines. In other words, a unit cell includes a first transistor whose gate electrode is connected to a first SWL of a pair of SWLs and whose source electrode is connected to a first bit line of a pair of bit lines, a second transistor whose gate is connected to a second SWL of the one Pair of SWLs is connected, and the source electrode is connected to a second bit line of the one pair of bit lines, a first capacitor, the first electrode is connected to a drain electrode of the first transistor, the second electrode is connected to the second SWL, and one second capacitor, the first electrode of which is connected to the drain electrode of the second transistor, and the second electrode of which is connected to the most SWL. The cell array actually contains a main cell area 401 for writing data and a reference cell area 402 for storing reference values when reading data. A plurality of bit lines for main cells therefore form a main cell sub-block, while a pair of reference cell bit lines RBit-n, Rbit-n + 1 form a reference cell sub-block for each main cell sub-block. A plurality of main cell sub-blocks and a plurality of reference cell sub-blocks are present in order to build up a cell array or cell array. These blocks alternate with each other. As can be seen, the main cell sub-blocks can comprise four column units and the reference cell sub-blocks can comprise two column units. In deviation from this, the main cell sub-blocks can also comprise 2n column units (n is a natural number greater than 2), while the reference cell sub-blocks each have two column units. Last but not least, a so-called core 500 has a main cell bit line control block 501 and a reference cell bit line control block 502 . The main cell bit line control block 501 includes a sense amplifier block for reading data of the main memory cells and a write control circuit. The main cell bit line control blocks 501 and the reference cell bit line control blocks 502 at the bottom of the cell array each control odd columns B_n, B_n + 2, RB_n of the cell array. In contrast, the main cell bit line control blocks 501 and the reference cell bit line control blocks 502 located at the top of the cell array control even numbered columns B_n + 1, B_n + 3, RB_n + 1 of the cell array.

Fig. 9 shows a cell array of a ferroelectric SWL memory in accordance with the second embodiment of the present invention.

According to the Fig. 9 includes a cell array of a ferroelectric memory SWL in accordance with the second embodiment of the invention vorlie constricting n-SWL1 a plurality of split or sub-word lines, SWL2-n. , ., SWL2-n + 3, hereinafter referred to as "SWLs". They extend in one direction and are parallel to each other at fixed distances. Furthermore, there are a plurality of bit lines Bn, Bn + 1 and additional bit lines BB-n, BB-n + 1, which are alternately arranged in a direction at fixed intervals parallel to one another and extend in the direction vertical to the respective SWLs. A unit cell is formed by a pair of adjacent SWLs and a pair of adjacent bit lines B and bit lines BB, respectively. The unit cell includes a first transistor whose gate electrode is connected to a first SWL of a pair of SWLs and whose source electrode is connected to bit line B, a second transistor whose gate electrode is connected to a second SWL of the one pair of SWLs and whose source electrode is connected to the additional bit line BB is connected to a first capacitor, the first electrode of which is connected to a drain electrode of the first transistor, the second electrode of the capacitor being connected to the second SWL, and a second capacitor, the first electrode of which the drain electrode of the second transistor is connected and the second electrode is connected to the first SWL. The cell array of the ferroelectric SWL memory in accordance with the second embodiment of the present invention is constructed similarly to the cell array of the ferroelectric SWL memory according to the first embodiment of the present invention, but differs in that now the even bit lines B at first embodiment are replaced by the set bit lines BB and that all reference cell sub-blocks in the first embodiment are replaced by main cells.

A circuit for driving a ferroelectric memory according to the inven tion is described in more detail below with reference to FIG. 10. This circuit is designed so that it can control both the ferroelectric memory according to the first embodiment and the second embodiment of the present invention.

. According to the Figure 10 includes the driver circuit comprises: a X buffer 11 for buffering an X address of X, Y and Z addresses; an X predecoder 12 for predecoding a signal from the X buffer 11 ; a Z buffer 13 for puffing a Z address from X, Y and Z addresses; a Z predecoder 14 for predecoding a signal from the Z buffer 13 ; an X, Z ATD generator 15 for detecting address transition points of the X address and Z address signals from the X buffer 11 and the Z buffer 13 ; a global control pulse generator 16 for receiving a signal from the X, Z-ATD generator 15 and for receiving an external CSBpad signal, which generates a power increase sensor signal for itself and supplies a base pulse for memory control, in accordance with that X, Z-ATD signal, the CSBpad signal and the power increase sensor signal; a Y buffer 17 for buffering a Y address from X, Y and Z addresses received from the outside; a Y predecoder 18 for predecoding a signal from the Y buffer 17 ; a Y-ATD generator 19 for detecting an address transition point of the Y address signal from the Y buffer 17 ; a local control pulse generator 20 for connecting a signal from the global control pulse generator 16 to a Z predecode signal from the Z predecoder 14 and a signal from the Y-ATD generator 19 to a pulse required in each memory block; an X post-decoder 21 for connecting the X pre-decode signal to the Z pre-decode signal from the X pre-decoder 12 and the Z pre-decoder 14, respectively, for the selection of a cell block; a SWL driver 22 for connecting signals from the X post-decoder 21 and from the local control pulse generator 20 for driving split word lines of each of the SWL cell blocks 23 ; a column controller 24 for connecting signals from the Y predecoder 18 and from the local control pulse generator 20 to select a bit line (or an additional bit line); a sense amplifier and input / output controller 25 for connecting a signal from the local control pulse generator 20 to a signal from the column controller 24 for controlling the operation of the sense amplifier and the input / output; and an input / output bus controller 26 for forming an interface between an external data bus on the one hand and the sense amplifier and input / output controller 25 .

The global control pulse generator is described in more detail below with reference to FIG. 11. The Fig. 11 shows a block diagram of globa len control pulse generator according to the first embodiment of the present invention.

Referring to FIG. 11, the global control pulse generator 16 contains, after the first imple mentation of the invention comprises: a receiving buffer 31 to the Emp catch a signal that at least one CSBpad signal, the X, Z-ATD signal from the X, Z-ATD Generator 15 and the power increase detector signal, wherein the reception buffer outputs a first synchronization signal and a second synchronization signal; 32 to an operation to prevent a circuit to prevent operation at low voltage as well as for preventing noise, the circuit 32 outputs a low-voltage detection signal when never Driger voltage, and outputs a noise cancellation signal, to filter noise in the first synchronization signal, and wherein circuit 32 further outputs a preactivation pulse for precharging the bit lines and the like in response to the first synchronization signal from the reception buffer 31 and receives a feedback signal (fourth control signal from the second controller); a first controller 33, which in the event that a normal supply voltage is supplied from the circuit 32, a signal with no rough rule of the circuit 32 receives, and a first control signal for controlling the activation timing of the sense amplifier, a second control signal for controlling the Spaltenselektions- Activation time and the bit line pull-up process of a reference cell and a third control signal to provide a signal for the SWL driver and other control signals; a second controller 34 for receiving the third control signal from the first controller 33 , the second controller 34 generating a signal S1 for the SWL1 and a basic waveform generation signal S2 for the SWL2 in a pair of SWLs for the SWL driver, a fourth Control signal outputs that a basic pulse signal for controlling the activation period of the signals S1 and S2 and for controlling a pulse signal P2, which has an improved driver capability due to the fourth control signal, and the fourth control signal as a feedback signal to the circuit 32 and the pulse signal P2 outputs to the local control pulse generator 20 ; a third controller 35 for receiving the first and second synchronization signals from the reception buffer 31 and for receiving the fourth control signal from the second controller 34 , for supplying a fifth control signal in synchronization with the SCBpad signal if all signals except the signal S1 for the SWL1 and the signal S2 for SWL2 are disabled, and to provide a sixth control signal to interrupt the deactivated state of the CSBpad signal when the CSBpad signal is disabled under the condition that the basic waveform generation signal S1 are enabled for the SWL1 and the basic waveform generation signal S2 for the SWL2 and maintain the activated state until the normal operation of the basic waveform activation signal S1 for the SWL1 and the activation signal S2 for SWL2 has ended; and a fourth controller 36 for receiving the fifth and sixth control signals from the third controller 35 , the first, second and third control signals from the first controller 33, and for receiving the pre-activation pulse from the low voltage and noise preventing circuit 32 , wherein the fourth controller outputs an enable signal SAN for an n-MOS device and an enable signal SAP for a p-MOS device in the sense amplifier, and also supplies the following control signals: a control signal C1 for connecting one Bit line of a main cell block with a first input / output node of the sense amplifier, a control signal C2 for connecting a bit line of a reference cell block with a second input / output node of the sense amplifier, a control signal C3 for controlling a low-voltage precharge of a bit line of a main cell, a bit line a reference number Elle and a node of the sense amplifier, and a fourth control signal C4 for controlling the enable or activation time of a column selection and a bit line pull-up process of a reference cell.

If the externally applied signals (the CSBpad signal, the A, Z-ATD signal and the power rise detector signal) to the global control pulse generator are stable in the first embodiment, the low voltage operation preventing circuit and the noise preventing circuit can be used be omitted. This is explained below with reference to a second embodiment of the invention. Fig. 12 shows a block diagram of a global control pulse generator according to this second embodiment of the invention.

Fig. 12 shows the schematic structure of the global control pulse generator according to the second preferred embodiment of the present invention. This global control pulse generator contains the following: a receive buffer 31 for receiving a signal which comprises at least one CSBpad signal, the X, Z-ATD signal from the X, Z-ATD generator 15 and a power increase detector signal, and for outputting one first and a second synchronization signal; a first controller 33 for receiving the first synchronization signal from the reception buffer 31 and for outputting a first control signal for controlling an activation time of the sense amplifier, a second control signal for controlling a column selection switch-on time and a bit line pull-up process of a reference cell, and for outputting a third control signal for Providing a signal for the SWL driver and other control signals; a second controller 34 for receiving the third control signal from the first controller 33 , which generates a generator signal S1 for the SWL1 and a generator signal S2 for the SWL2 in a pair of SWLs for the SWL driver, outputs a fourth control signal that provides a basic pulse signal Is control of the turn-on periods of the signals S1 and S2, and which further outputs a pulse signal P2 which, as a result of the fourth control signal, has an improved driver capability, the pulse signal P2 being supplied by the second controller 34 to the local control pulse generator 20 ; a third controller 35 for receiving the first and second synchronization signals from the reception buffer 31 and for receiving the fourth control signal from the second controller 34 , the third controller 35 outputting a fifth control signal in synchronism with the SCBpad signal when all signals except the Generator signal S1 for the SWL1 and the generator signal S2 for the SWL2 are disabled and switched off, and which also outputs a sixth control signal to interrupt the switched-off state of the CSBpad signal when the CSBpad signal is switched off or dis abled under the condition that the generator signal S1 for the SWL1 and the generator signal S2 for the SWL2 are enabled or switched on, the sixth control signal holding the switched on until the normal operation of the generator signal S1 for the SWL1 and the generator signal S2 for the SWL2 has ended; and a fourth controller 36 for receiving the fifth and sixth control signals from the third controller 35 , the first, second and third control signals from the first controller 33 and the first synchronization signal from the receive buffer 31 , the fifth controller 36 an activation signal SAN outputs for an n-MOS device and an activation signal SAP for a p-MOS device in the sense amplifier, and also outputs further signals: a control signal C1 for connecting a bit line on a main cell block to a first input / output node of the sense amplifier second control signal C2 for connecting a bit line on a reference cell block to a second input / output node of the sense amplifier, a third control signal C3 for controlling a low-voltage precharge of a bit line of a main cell, a bit line of a reference cell and a node of the sense amplifier, and a fourth control signal C4 for controlling the switch-on or activation time of a column selection and a bit line pull-up process of a reference cell.

Although not shown, the circuit may prevent operation low voltage and to prevent noise in global control pulse generator of the first embodiment replaced by a circuit be either only operating at low voltage or just the harsh prevented.

A method for operating the aforementioned global control pulse generator in the ferroelectric SWL memory is described in more detail below. Fig. 13 shows an operation flowchart of the first embodiment of the global control pulse generator in accordance with the present invention, while Fig. 14 shows an operation flowchart of the second embodiment of the global control pulse generator in accordance with the present invention. FIG. 15 shows an operational flowchart of a third embodiment of the global control pulse generator in accordance with the invention, while FIG. 16 shows an operational flowchart of a fourth embodiment of the global control pulse generator according to the invention.

The operation of the global control pulse generator according to the present invention depends on the cell array system, on the X, Z address switching or on the Y address switching. The operation of the global control pulse generator of the first embodiment will be described below with reference to FIG. 13. Here, a cell array system according to FIG. 8 is used, the Y address being switched over. Since the chip is switched on (enabled) when the chip activation signal CSBpad is pulled externally to "low", the chip is brought into the switched-on state when the CSBpad signal changes from "high" to "low". A switch-off interval to "high" is therefore always required in order to carry out a new read or write operation. Referring to FIG. 13 reaches a complete cycle of operation from time t1 to time t15. First of all, it is assumed that the CSBpad signal is activated, that is to say changes to "low", specifically from the start point of the t1 interval to the end point of the t14 interval. The CSBpad signal is deactivated by changing to "high", namely at the starting point of the t15 interval. It is assumed that there is no transition in the X and Z addresses and that the Y address changes at the start point of interval t7 and at the start point of interval t11, respectively, while the CSBpad signal is in the on state. A Y-ATD detects a change in a Y address and generates a high pulse in the intervals t7 and t8 on the one hand and in the intervals t11 and t12 on the other hand. S1 and S2 are pulses for use in forming the base waveforms for word lines SWL1 and SWL2 of a SWL cell. First, the CSBpad signal changes from "high" to "low" at the beginning of the interval t1 in order to activate the chip. The X, Y and Z addresses are kept in the state they were in before t1. The Y-ATD signal changes to "high" from the interval t7 to the interval t8 when the Y address changes at the start time of the interval t7. If the Y address changes again at the start time of the interval t11, the Y-ATD signal changes again to "high" from the start time of the interval t11 to the end of the interval t12. The signal S1 goes to "low" in the interval t1, to "high" from the interval t2 up to and including the interval t3, to "low" in the interval t4, to "high" in the interval t5 and to "low" from the beginning of the interval t6 hold until the beginning of the interval t15, and beyond. In contrast, the signal S2 is kept "high", specifically from the beginning of the interval t2 to the end of the interval t4. Otherwise it remains at "low". The signal C1, which is a basic signal for controlling the signal flow between a main cell bit line and an input / output terminal on the sense amplifier, is only kept "low" from the beginning of the interval t3 to the end of this interval t3 and is otherwise on "high". This signal interrupts the signal flow between the main cell bit line and the input / output terminal of the sense amplifier only in the interval t3. The signal C2 is a base signal for controlling a signal flow between a reference cell bit line and the other input / output terminal of the sense amplifier and supplies a pulse which is kept "low" from the interval t3 to the interval t14 inclusive, to the signal flow between one Interrupt reference cell bit line and the other input / output terminal of the sense amplifier, from the beginning of the interval t3 to the end of the interval t14. The signal C4 controls a signal transmission between a main cell bit line and an external data bus and also controls a pull-up process of a reference cell bit line. It is held at "high" from interval t4 to interval t14 and changes back to "low" at a time at which the CSBpad signal is disabled or switched off (end time of interval t14) in order to control signal transmission between to enable a main cell bit line and the external data bus and control of the pull-up process on a reference cell bit line, and only from the beginning of the interval t4 to the end of the interval t14. The signal P2 is kept "high", namely from the beginning of the interval t2 to the end of the interval t5, in which time the signals S1 and S2 are also kept "high" to counter the signals S1 and S2 To protect external influences, with the signal P2 changing to "low" at the beginning of the interval t6. The signal C3 is used for precharging the main cell bit line and the reference cell bit line to a low voltage before switching on the signals S1 and S2 and for this purpose is kept "high" until the end of the interval t1. Then the signal C3 changes to "low" at the beginning of the interval t2 and is kept at "low" until the end of the interval t14 in order to switch off the precharging. At the beginning of the interval t15, the signal C3 changes back to "high", that is, when the CSBpad signal is switched off. The signal SAN (a prior signal for generating a SAN_C signal, which is a signal for controlling NMOS transistors for operating the sense amplifier in the sense amplifier and input / output control) is initially kept at "low" and changed to "high" at the beginning of the interval t3 and again to "low" when the CSBpad signal is switched off. The SAP signal (a preliminary signal for generating a SAP_P signal that controls PMOS transistors for operating the sense amplifier in the sense amplifier and input / output control) behaves in the opposite way to the SAN signal. The SAP signal is kept "high" until the end of the interval t2 and then changes to "low" at the beginning of the interval t3. It changes to "high" again when the CSBpad signal is switched off. If the CSBpad signal is switched off, the Y address changes and the signal Y-ATD appears, a logical "0" is written into the relevant cell in write mode, in the intervals in which both S1 and S2 are at "high"" lie. Logical "0" is written from interval t2 to interval t3. In contrast, a logical "1" is written into the cell if only one of the signals S1 and S2 is at "high", ie here from the beginning of the interval t4 to the end of the interval t5.

The operation of the global control pulse generator according to the second embodiment of the present invention will be described with reference to FIG. 14. A cell array system according to FIG. 8 is used here, the X, Z addresses being switched over. A complete operating cycle is divided into intervals t1 to t21, with both addresses X, Z changing at the beginning of intervals t7 and t14. Since the operation of the global control pulse generator in the case of the X, Z address switchover is similar to the operation of the global control pulse generator in the case of the Y address switchover, only processes which differ from the first exemplary embodiment are described. Alternately while the Y-ATD signal of FIG. 13 at a Y address switches to "high", it is assumed that during the second execution of the invention, X, Z, for example addresses at the beginning of the intervals t7 and t14 clauses wech. The X, Z-ATD signals are thus kept "high" in the intervals t7 and t14 and are otherwise "low" in all other intervals. If the X, Z addresses change, the global control pulse generator connects the X, Z ATD signals with the CSBpad signal. In other words, if the X, Z ATD signals are high (t7 and t14), the global control pulse generator determines that the CSBpad signal is switched on again in the interval. The global control pulse generator thus again delivers all signals to enable normal access to the X, Z addresses. Both signals S1 and S2 start after a predetermined interval (t1) after the signal CSBpad has changed to "low" and start after a predetermined interval (t8 and t15) after the signals X, Z-ATD at "low" have changed. This means that the signal S1 is kept "high", namely in the intervals t2-t3, in the interval t5, in the intervals t9-t10, in the interval t12, in the intervals t16-t17 and in the interval t19. In contrast, the signal S1 is kept "low" in the rest of the intervals. The signal S2 is kept "high" in the intervals t2-t4, in the intervals t9-t11 and in the intervals t16-t18. Otherwise it remains at "low". The signal C1 changes and is kept "low" in the intervals t3, t10 and t17, in which both the signal S1 and the signal S2 are "high" (t1-t3, t9-t10 and t16-t17) , and then changes back to "high". The signal C2 changes from "high" to "low" at the time when the signal C1 changes to "low" and goes from "low" to "high" at the time when the X, Z-ATD signal changes to "high". The signal C4 changes from "low" to "high" at the time when the signal C1 changes to "high" and changes from "high" to "low" at the time when the signal X, Z-ATD changes to "high". The signal P2 changes from "low" to "high" at the point in time at which both signals S1 and S2 change to "high", and changes from "high" to "low" at the point in time at which the second pulse occurs changes from S1 to "low". The signal C3 changes from "high" to "low" at the time at which both signals S1 and S2 change to "high", and changes from "low" to "high" at the time at which the signal X, Z -ATD changes to "high". The signals SAN and SAP run opposite to each other, the signal SAN changing from "low" to "high" at the time the signal C1 changes to "low" and changing from "high" to "low" to that Time at which the signal X, Z-ATD changes to "high". This means that a logical "0" is written into a relevant cell when both signals S1 and S2 are "high", ie in the intervals of t1-t3, t9-t10 and t16-t17. In contrast, a logical "1" is written into a relevant cell at intervals in which only one of the signals S1 and S2 is at "high", that is to say in the intervals t4-t5, t11-t12 and t18-t19.

The operation of the global control pulse generator will be described in the event that a cell array as shown in FIG. 9 is constructed and a Y address is switched. The description is given with reference to FIG. 15. A complete operating cycle is again subdivided into intervals t1 to t15. The cell array of FIG. 9 does not require the C1 and C2 signals because the stem Zellenarraysy bit lines and bit lines having additional, but not Referenzzel len. It is assumed that the CSBpad signal is from the beginning of the interval t1 to the end of the interval t14 at "low" when it is switched on and otherwise at "high" when it is switched off. While the CSBpad signal is on, the X, Z addresses are not changed, while the Y address is switched at the beginning of the intervals t7 and t11. When a Y address changeover is detected, the Y-ATD signal is output and set to "high", specifically from the beginning of the interval t7 to the end of the interval t8 and from the beginning of the interval t11 to the end of the interval t12. The signals S1 and S2 are signals for forming the basic waveforms for the SWL1 and the SWL2 partial word lines of the SWL memory cell. The signal S1 forms a pulse and is "high" in the intervals t2-t3 and in the interval t5, while the signal S2 also forms a pulse and is "high" in the intervals t2-t4. Otherwise the signals S1 and S2 are "low". The signal C4 is a signal for controlling a signal transmission between a main cell bit line and an external data bus and for controlling a pull-up operation for the main cell bit line and the additional bit line. The signal C4 changes from "low" to "high" at the beginning of the interval t4, and changes from "high" to "low" at the point in time at which the CSBpad signal is switched off (at the beginning of the interval t15). Since a signal transmission between a main cell bit line and egg ner data line is possible. The signal P2 is kept "high" in the intervals t2-t5, in which both signals S1 and S2 form the normal pulses (on "high"). Signal P2 latches signals S1 and S2 to prevent other signals from interfering with them. Thus, if P2 is held high in the intervals t2 to t5 in which the signals S1 and S2 form normal pulses, P2 protects the signals S1 and S2 against interference from external signals in these intervals. C3 is a signal to turn off precharge in intervals t2-t4 and turn on precharge in the remaining intervals. C3 is thus kept at "high" until the end of the interval t1, and then changes to "low" at the beginning of the interval t2. It changes from "low" to "high" again at the time when the CSBpad signal is switched off. The signal SAN, which is a preliminary signal for generating a SAN_C signal, which is used to control NMOS transistors for operating the sense amplifier in the sense amplifier and input / output control, is kept at "low", namely until at the end of the interval t2, and rises to "high" at the beginning of the interval t3. It changes back to "low" when the CSBpad signal is switched off. The SAP signal, which is a preliminary signal for generating a SAP_P signal, which is used to control PMOS transistors for operating the sense amplifier in the sense amplifier and input / output control, behaves in the opposite way to the SAN signal. In other words, the SAP signal is kept "high" until the end of the interval t2 and then changes to "low" at the beginning of the interval t3. It changes back to "high" when the CSBpad signal is switched off. In other words, a logical "0" is now written into a relevant cell, in intervals in which both the signal S1 and the signal S2 are "high", ie in the intervals t2-t3. On the other hand, a logical "1" is written into a relevant cell, in intervals in which only one of the signals S1 and S2 is "high", that is in the intervals t4-t5.

The operation of the global control pulse generator will be described in the event that a cell array system shown in FIG. 9 is used and the X, Z addresses are switched. The description is based on FIG. 16, which relates to a fourth exemplary embodiment of the present invention. Since the operation of the global control pulse generator when switching the X, Z addresses is similar to the operation of the global control pulse generator when switching the Y addresses, only steps that are different are described.

In Fig. 15, the signal A-ATD changed to "high" at the time when the Y address was changed. In the present case, on the other hand, the signal X, Z-ATD goes "high" when the X, Z addresses change. The global control pulse generator connects the X, Z-ATD signals with the CSBpad signal in the event of the transition of the X, Z addresses. If the X, Z-ATD signals are "high" (t7 and t14), the global control pulse generator detects that the CSBpad signal has been switched on again in the interval. As a result, the global control pulse generator delivers all signals again to enable normal access to the X, Z addresses. Both the signal S1 and the signal S2 start after the expiration of a predetermined interval (t1) after the transition of the CSBpad signal to "low" and after the expiration of a predetermined interval (t8 and t15) after the transition of the X, Z-ATD Signals at "low". The signal C4 changes from "low" to "high" at the time when the signal S1 changes to "low" and the signal S2 remains at "high", and changes from "high" to "low" at the time to which the X, Z-ATD signals change to "high". Signal P2 changes from "low" to "high" at the point in time at which both signals S1 and S2 change to "high" and changes from "high" to "low" at the point in time when both signals S1 and S2 go up fell low. The signal C3 changes from "high" to "low" at the point in time at which both signals S1 and S2 change to "high", and changes from "low" to "high" at the point in time at which the X, Z Change ATD signals to "high". The signals SAN and SAP change after a predetermined delay from the time at which both signals S1 and S2 have switched to "high" and change to opposite states at the time when the X, Z-ATD signals are at "high" switch. In other words, a logical "0" is written into a relevant cell, namely in intervals in which both signals S1 and S2 are "high", ie in the intervals t2-t3, t9-t10 and t16 -t17. In contrast, a logic "1" is written into a relevant cell in an interval in which only one of the signals S1 and S2 is "high", namely in the intervals t4-t5, t11-t12 and t18-t19.

Having previously described the structure and mode of operation of the global control pulse generator, the structure and mode of operation of the local control pulse generator 20 , which operates as a function of signals from the global control pulse generator, will now be described. Furthermore, the column controller 24 and the sense amplifier and input / output controller 25 are described in more detail ben and their operation. Since the system and mode of operation depend on whether the cell array of the ferroelectric SWL memory is designed according to FIG. 8 or FIG. 9, the explanation is made separately in each case.

Fig. 17 shows a circuit system of the local control pulse generator in accordance with the first embodiment of the present invention shown in Fig. 8. Fig. 18 shows a circuit system of column control in accordance with the first embodiment of the present invention shown in Fig. 8. Die Fig. 19 shows a circuit system of a first embodiment of a sense amplifier and input / output control in accordance with the present invention shown in Fig. 8. Fig. 20 shows a circuit system of a second embodiment of a sense amplifier and input / output control 8 in accordance with the present invention . FIG. 21 shows a circuit system of a third embodiment of a sense amplifier and input / output controller in accordance with the present invention shown in FIG. 8, and FIG. 22 shows one Circuit system of a fourth embodiment e iner sense amplifier and input / output control in accordance with the present invention of FIG. 8.

The signals S1, S2, P2, C1, C3, C4, SAN and SAP to the local control pulse generator are signals from the global control pulse generator. In addition, an address transition detection signal (address switching detection signal) is generated when a Y address is switched. The Y-ATD signal (pulse signal), which is at a high level, then appears as the address switching detector signal. A WEBpad signal serves as a write-in signal, which signal is then at a low logic level and is switched on when a write mode (write mode) is executed. The signals Z_Add1, Z_Add2, Z_Add3 and Z_Add4 are signals from the Z_ predecoder 14 . The local control pulse generator of the present invention shown in FIG. 17 is an example of providing a signal for controlling an upper block in FIG. 8. In an identical manner, an operation control pulse is provided for a lower block. The local control pulse generator 20 includes at least a first control pulse generator 200 for generating a signal that is transmitted to the sense amplifier and input / output controller 25 , a second control pulse generator 201 for generating a signal that is transmitted to the column controller 24 , and a third control pulse generator 202 for generating a signal that is transmitted to the SWL driver 22 . The first control pulse generator 200 contains a first logical operator 203 for receiving the signals SAP, SAN, Z_Add3, Z_Add4 and a third control signal for controlling an upper block and a lower block, and a second logical operator 204 for receiving first and second control signals C1, C2, Z_Add1 and Z_Add2 for the delivery of the control pulses C1P_T, C1N_T, C2P_T, C2N_T and C3N_T.

The local control pulse generator is explained in detail below.

The first logic operator 203 of the first control pulse generator 200 contains the following: a first NAND gate 203-1 for the logic combination of signals Z_Add3 and Z_Add4 for the delivery of a signal for the purpose of generating control signals which are to be delivered to a floor block; a second NAND gate 203-2 for logically combining a signal from the first NAND gate 203-1 with NAND-linked signals Z_Add1 and Z_Add2; a third NAND gate 203-3 for logically combining an external signal SAP with a signal from the second NAND gate 203-2 ; a first inverter 203-4 for inverting the signal from the third NAND gate 203-2 to provide a signal SAP_C; a fourth NAND gate 203-5 for logically combining a SAN signal with a signal from the second NAND gate 203-2 ; a second inverter 203-6 for inverting a signal from the fourth NAND gate 203-5 to generate a signal SAN_C; a third inverter 203-7 for inverting the third control signal C3; a fifth NAND gate 203-8 for logically combining the output signal of the third inverter 203-7 with a signal from the second NAND gate 203-2 ; a fourth inverter 203-9 for inverting the signal from the fifth NAND gate 203-8 to generate a signal C3P_C; and a fifth inverter 203-10 for inverting the signal from the fourth inverter 203-9 for supplying a signal C3N_C.

The second logic operator 204 in the first control pulse generator 200 contains the following: a first NAND gate 204-1 for the logic combination of signals Z_Add1 and Z_Add2 for outputting a signal to generate control signals for the upper block; a first inverter 204-2 for inverting the signal from the first NAND gate 204-1 ; a second NAND gate 204-3 for logically combining a signal from the first inverter 204-2 with a first control signal C1 to perform a NAND operation; second and third inverters 204-4 and 204-5 for amplifying a signal from the second NAND gate 204-3 into a C1P_T signal; a fourth inverter 204-6 for inverting a signal from the second NAND gate 204-3 to provide a signal C1N_T; a third NAND gate 204-7 for logically NANDing a signal from the first inverter 204-2 with a second control signal C2; fifth and sixth inverters 204-8 and 204-9 for amplifying a signal from the third NAND gate 204-7 into a C2P_T signal; a seventh inverter 204-10 for inverting a signal from the third NAND gate 204-7 into a signal C2N_T; a fourth NAND gate 204-11 for logically NANDing a signal from the first inverter 204-2 with a third control signal C3; and ninth and tenth inverters 204-12 and 204-13 for amplifying a signal from the fourth NAND gate 204-11 into a C3N_T signal.

Furthermore, the second control pulse generator 201 contains the following: a first inverter 201-1 for inverting a WEBpad signal; a second inverter 201-2 for inverting a signal from the first inverter 201-1 ; a third inverter 201-3 for inverting a fourth control signal C4; a NAND gate 201-4 for logically NANDing signals from the second and third inverters 201-2 and 201-3 ; a fourth inverter 201-5 for inverting a signal from the NAND gate 201-4 ; a NOR gate 201-6 for the logical NOR combination of a third control signal C3, a signal from the fourth inverter 201-5 and a signal from the first NAND gate 204-1 , the latter being located in the second logic operator of the first control pulse generator 200 ; a fifth inverter 201-7 for inverting a signal from NOR gate 201-6 into a C4P_T signal; and a sixth inverter 201-8 for inverting a signal from the fifth inverter 201-7 into a C4N_T signal.

The third control pulse generator 202 includes: a first inverter 202-1 for inverting a P2 signal; a first NAND gate 202-2 for logically NANDing a Y_ATD signal, a signal from the first inverter 202-1 , a fourth control signal C4 and the inverted WEBpad signal; a second inverter 202-3 for inverting a signal from the first NAND gate 202-2 , third, fourth, fifth and sixth inverters 202-4 , 202-5 , 202-6 and 202-7 for delaying a signal from the second inverter 202-3 ; a first NOR gate 202-8 for NOR operation of an S1 signal with a signal from the second inverter 202-3 ; a second NOR gate 202-9 for NOR-linking a signal from the first NOR gate 202-8 with a signal from the first NAND gate 204-1 , which is located in the second logic operator 204 ; a seventh inverter 202-10 for inverting a signal from the second NOR gate 202-9 into a PS1_T signal; a third NOR gate 202-11 for NOR operation of a second control signal S2 with a signal from the sixth inverter 202-7 ; a fourth NOR gate 202-12 for the logical NOR combination of a signal from the third NOR gate 202-11 with a signal from the first NAND gate 204-1 in the second logic operator 204 ; and a seventh inverter 202-13 for inverting a signal from the fourth NOR gate 202-12 into a PS2_T signal.

In the aforementioned local control pulse generator of the present invention, the first logic operator 203 in the first control pulse generator 200 is a block in which a control pulse for use for the upper block and the lower block is generated together, while the second logic operator 204 in the first control pulse generator 200 and the second and the third control pulse generator 201 and 202 are blocks that generate a pulse for controlling the upper block.

The generation of the control pulses in the local control pulse generator follows explained in more detail according to the present invention.

The write mode is first described. If the WEBpad signal is "low", a signal lying at "low" passes the first inverter 201-1 and the second inverter 201-2 in the second control pulse generator 201 , which leads to the first NAND gate 201-4 being switched off becomes. The first NAND gate 201-4 thus supplies a "high" signal at its output, which leads to the activation of the NOR operator 201-6 . If the NOR operator 201-6 is activated or switched on, the third control signal C3 generates a C4P_T signal via the fifth inverter 201-7 and likewise a C4N_T signal via the sixth inverter 201-8 . The third control signal C3 generates a state before the sub-word lines SWL1 and SWL2 are enabled or activated, that is, a state in which all column selection signals are deactivated, specifically in a precharge interval of a memory cell bit line and a reference cell bit line. The de-activated column selection signal blocks a signal flow between a data bus and a bit line and prevents a collision of data on a bit line with data on an input / output data bus when the bit line is precharged in write mode. If the WEBpad signal is "low" in write mode, then a signal from the first inverter 201-1 in the second control pulse generator 201 is "high", which leads to the activation of the NAND gate 202-2 in the third control pulse generator 202 . Accordingly, the NAND gate 202-2 in the third control pulse generator 202 is under the control of the Y-ATD signal, the P2 signal and the C4 signal. So if the signals S1 and S2 work under regular conditions when the signal P2 is "high", the NAND gate 202-2 in the third control pulse generator 202 is deactivated, to ensure the operation of the signals S1 and S2 in the case the regular conditions. If the signal P2 changes to "low" after the regular working conditions of the signals S1 and S2 have ended, an output of the first inverter 202-1 in the third control pulse generator 202 changes to "high", which in turn activates the NAND gate 202-2 third control pulse generator 202 leads. Under this condition, the NAND gate 202 in the third control pulse generator 202 operates depending on the state of the Y-ATD signal or the C4 signal. In this case, an output of the first inverter 202-1 in the second control pulse generator 201 changes to "high" and the signal C4 is also "high", the NAND gate 202-2 in the third control pulse generator 202 is activated, so that the Y-ATD signal is provided to the SWL driver block 70 . Specifically, the signals S1 and S2 activate the first and third NOR gates 202-8 and 202-11 in the third control pulse generator 202 at an interval in which the Y address changes. As a result, the Y-ATD signal passes through the NAND gate 202-2 and the second inverter 202-3 in the third control pulse generator 202 to the NOR gate 202-8 in the third control pulse generator 202 , while the output signal of the second inverter 202-3 is delayed via the third, fourth, fifth and sixth inverters 202-4 , 202-5 , 202-6 and 202-7 and finally reaches the third NOR gate 202-11 . The Y-ATD signal passes through the first and second NOR gates 202-8 and 202-9 as well as the seventh inverter 202-10 in the third control pulse generator 202 , at the output of which an inverted and "low" PS1_T signal is finally received becomes. The delayed Y-ATD signal at the output of the inverter 202-7 passes through the third and fourth NOR gates 202-11 and 202-12 and the seventh inverter 202-13 in the third control pulse generator 202 , at the output of which is finally an inverted and PS2_T signal present at "low". As a result, both the PS1_T signal and the PS2_T signal have a phase that is inverted with respect to the Y-ATD signal. The overlap period of the PS1_T signal with the PS2_T signal in the "low" state can be set by the sizes of the third, fourth, fifth and sixth inverters 202-4 , 202-5 , 202-6 and 202-7 , delaying a signal from the second inverter 202-3 in the third control pulse generator 202, entspre be selected accordingly. In read mode, the NAND gate 201-4 in the second control pulse generator 201 is activated in order to convert the signal C4 into the signal C4P_T via the third inverter 201-3 , since 99999 00070 552 001000280000000200012000285919988800040 0002019923979 00004 99880s NAND gate 201- 4 , the fourth inverter 201-5 , the NOR gate 201-6 and the fifth inverter 201-7 in the second control pulse generator 201 . A signal from the fifth inverter 201-7 is also converted into the C4N_T signal, specifically via the sixth inverter 201-8 . The signals C4P_T and C4N_T deliver signals which are amplified by the sense amplifier and finally reach the data bus. In the present reading mode, a "low" signal from the first inverter 201-1 in the second control pulse generator 201 deactivates the NAND gate 202-2 in the third control pulse generator 202 and thus blocks the transmission of the Y-ATD signal, the P2 signal and the signal C4. A signal from the second inverter 202-3 in the third control pulse generator 202 changes to "low" to activate the first NOR gate 202-8 in the third control pulse generator 202 . The previously explained operation of generating the control pulses results in the signal PS1_T and the signal PS2_T, which arrive at the SWL driver 22 , having waveforms which each have phases which are opposite to those of the signals S1 and S2.

Below is the column control of the ferroelectric SWL memory explained in more detail according to the present invention.

Fig. 18 shows an example of a block for control of an upper array of memory cells. The column controller receives address signals and control signals from the Y predecoder 18 and from the local control pulse generator 20 for the purpose of outputting a column selection signal to select any cell in data input / data output.

Specifically, the column controller 24 contains a plurality of NAND gates 230 , 231 , 232 and 233 , each of which an address Ypre_n, Ypre_n + 1, Ypre_n + 2 and Ypre_n + 3,. , ., receives. These addresses are predecoded in the Y predecoder 18 . Furthermore, each of the NAND gates 230 , 231 , 232 , 233 receives the C4N_T signal from the local control pulse generator 20 to perform the respective logical NAND functions. Inverters 234 , 235 , 236 and 237 are connected to the output of the NAND gates, the outputs of which are connected to respective output connections. In addition, the outputs of the NAND gates 230 , 231 , 232 and 233 each lead directly to separate output connections. The output signals of the NAND gates 230 , 231 , 232 and 233 , which are passed via the respective inverters, form the Y addresses Y_n_T, Y_n + 1_T, Y_n + 2_T and Y_n + 3_T,. , In contrast, the output signals of the NAND gates 230 , 231 , 232 and 233 , which are not routed to the output terminals via the respective inverters, form the reference / Y addresses YB_n_T, YB_n + 1_T, YB_n + 2_T and YB_n + 3_T ,. , .. In the case of further addresses or reference addresses, of course, there are several NAND gates or inverters. In the activation case there is only one of the Y addresses Y_n_T, Y_n + 1_T, Y_n + 2_T, Y_n + 3_T,. , , to "high" and only one of the reference / Y addresses YB_n_T, YB_n + 1_T, YB_n + 2_T and YB_n + 3_T,. , , to "low". These activated signals control the on / off switching state of the transistors connected to the data buses in the sense amplifier and input / output controller 25 , or the switching blocks with transmission gates.

A first exemplary embodiment of a sense amplifier and input / output control according to the present invention for a system according to FIG. 8 is described in more detail below.

Fig. 19 shows a first embodiment of a sense amplifier and entranc be / output control according to the invention. It contains a sense amplifier 210 with an arbitrary bit line BIT_T which is connected to an upper memory cell, an arbitrary bit line RBIT_T which is connected to an upper reference cell, an arbitrary bit line BIT_T which is connected to a lower memory cell and an arbitrary bit line RBIT_T connected to a lower reference cell. In other words, the first embodiment of the sense amplifier and input / output controller of the present invention for the system of FIG. 8 includes: the sense amplifier 210 for reading and amplifying data on corresponding bit lines in response to sense amplifier enable signals SAP_C and SAN_C from the local control pulse generator 20 ; an equalizer 211 for equalizing voltages on bit lines BIT_T and RBIT_T or BIT_B and RBIT_B in response to equalization signals C3N_C or C3P_C; first and second transfer gates 212 and 213 , each of which is switchable in response to upper cell array connection signals C1P_T and C1N_T or C2P_T and C2N_T from the local control pulse generator 20 for selectively connecting the bit lines BIT_T or RBIT_T connected to the upper main cell or the reference cell , with an input / output line of the sense amplifier 210 ; third and fourth transmission gates 214 and 215 , each of which is switchable in response to lower cell array connection signals C1P_B and C1N_B or C2P_B and C2N_B for selectively connecting the bit lines BIT_B or RBIT_B connected to the lower main cell or the reference cell with one Input / output line of sense amplifier 210 ; a fifth transmission gate 216 connected to a bit line BIT_T between the first transmission gate 212 and the upper memory cell for controlling the connection to a data bus terminal D_BUS in response to column selection signals Y_n_T and YB_n_T; a sixth transfer gate 217 connected to a bit line BIT_B between the third transfer gate 214 and the lower memory cell to control the connection to a data terminal D_ in response to column selection signals Y_n_B and YB_n_B; a first bit line level adjuster 218 , one electrode of which is connected to a bit line BIT_T between the first transmission gate 212 and fifth transmission gate 216 , and the other electrode of which is connected to a power supply terminal for adjusting a level of the bit line BIT_T in response to a pull-down control signal C3N_T, that is applied to the gate of level adjuster 218 ; and a second bit line level adjuster 219 whose one electrode is connected to a bit line BIT_B between the third transfer gate 214 and a lower memory cell array block and whose other electrode is connected to the power supply terminal for setting a level of the bit line BIT_B in response to a pull-down control signal C3N_B is applied to the gate of the bit line level adjuster 219 . The data connection D_ is used both for the operation in the reading mode and for the operation in the writing mode. This means that the data connection D_ is used as the transmission path of a signal from the reading amplifier in the reading mode and as the transmission path of data which are to be written into a memory cell.

A second embodiment of a sense amplifier and input / output controller according to the present invention for the system of Fig. 8 will be explained below.

Fig. 20 shows a second embodiment of a sense amplifier and input / output control according to the invention for the system of Fig. 8. This control includes: a sense amplifier 220 , which has bit lines BIT_T, RBIT_T, BIT_B and RBIT_B for detection and Amplifying data on respective lines in response to sense amplifier enable signals SAP_C and SAN_C from the local control pulse generator 20 ; an equalizer 221 for equalizing voltages on bit lines BIT_T and RBIT_T or on bit lines BIT_B and RBIT_B in response to equalization signals C3N_C or C3P_C; first and second NMOS transistors 222 and 223 , each switchable in response to upper cell array connection signals C1N_T or C2N_T from local control pulse generator 20 for selectively connecting bit lines BIT_T or RBIT_T, connected to the upper main cell or the reference cell, with an input / output line sense amplifier 220 ; third and fourth NMOS transistors 224 and 225 , each switchable in response to lower cell array connection signals C1N_B or C2N_B for selectively connecting the bit lines BIT_B or RBIT_B, connected to the lower main cell or the reference cell, with an input / output line of the sense amplifier 220 ; a fifth NMOS transistor 226 connected to a bit line BIT_T between the first NMOS transistor 222 and the upper memory cell for controlling the connection to a data bus connection D_ in response to column selection signals Y_n_T; a sixth NMOS transistor 227 connected to a bit line BIT_B between the third NMOS transistor 224 and the lower memory cell for controlling the connection to a data terminal D_BUS in response to a column selection signal Y_n_B; a first bit line level adjuster 228 having one electrode connected to a bit line BIT_T between the first NMOS transistor 222 and the fifth NMOS transistor 226 for adjusting a level of the bit line BIT_T in response to a pull-down control signal C3N_T applied to its gate becomes; and a second bit line level adjuster 229 , an electrode having a bit line BIT_B between the third NMOS transistor 224 and the lower memory cell array block for adjusting a level of the bit line BIT_B in response to a pull down control signal C3N_B connected to the gate thereof is created.

Below are various control signals for the sense amplifiers and on sabe / output control described in detail, together with the Be drove the blocks.

The SAN_C signal is applied to the gate of the NMOS transistor, one electrode of which is connected to the sense amplifier and the other electrode of which is connected to a ground connection Vss, on the one hand to enable the sense amplifier 210 to be "high" or on the other hand to "low""to disabel. Furthermore, the SAP_C signal is applied to the gate of the PMOS transistor, one electrode of which is connected to the sense amplifier and the other electrode of which is connected to a voltage supply connection Vcc in order to enable the sense amplifier 210 to be "low" or the sense amplifier 210 to " high "to disabel. The equalization signals C3N_C and C3P_C to the equalization device 211 serve to equalize voltages on the bit lines BIT_T, RBIT_T BIT_B and RBIT_B on the main and reference cells and the sense amplifier 210 before the partial word lines SWL1 and SWL2 are activated. The pulldown control signal C3N_T turns on the first bit line level adjuster 218 upon selection of the upper main cell column and the reference cell column to perform a pull down operation such that the bit lines BIT_T and RBIT_T connected to the upper main memory cell and the reference cell are low "are pulled (low logic level). On the other hand, the pull-down control signal C3N_B turns on the second bit line level adjuster 219 when selecting the lower main cell column and the reference cell column to enable a pull-down operation in which the bit lines BIT_T and RBIT_T connected to the lower main memory cell and the reference cell. be set to "low" (low logic level).

A third embodiment of a sense amplifier and input / output controller of the present invention for the system of FIG. 8 will be explained in detail below.

FIG. 21 shows the third embodiment of the sense amplifier and input / output control according to the present invention for a system according to FIG. 8. This control includes the following: a sense amplifier 260 connected to bit lines BIT_T, RBIT_T, BIT_B and RBIT_B for Detecting and amplifying data on corresponding lines in response to sense amplifier activation signals SAP_C and SAN_C from the local control pulse generator; an equalizer 261 for equalizing voltages on bit lines BIT_T and RBIT_T or BIT_B and RBIT_B in response to equalization signals C3N_C or C3P_C; first and second transmission gates 262 and 263 , each switchable in response to upper cell array connection signals C1P_T and C1N_T or C2P_T and C2N_T from the local control pulse generator for the purpose of selectively connecting the bit lines BIT_T or RBIT_T, connected to the upper main cell or the reference cell, with an input / output line of sense amplifier 260 ; fourth and fifth transmission gates 264 and 265 , each switchable in response to lower cell array connection signals C1P_B and C1N_B or C2P_B and C2N_B for selectively connecting the bit lines BIT_B or RBIT_B, connected to the lower main cell or the reference cell, with an input / output line of the sense amplifier 260 ; a fifth transmission gate 266 connected to the input / output terminal of sense amplifier 260 for controlling the connection to a data terminal D_ in response to column selection signals Y_n and YB_n; a sixth transmission gate 267 connected to the input / output terminal of the sense amplifier 260 for controlling the transmission to an inverted data terminal DB_ (Databar-Termi nal) in response to column selection signals Y_n and YB_n; a first bit line adjuster 268 connected to a bit line BIT_T between the first transfer gate 262 and the upper memory cell for adjusting a level of the bit line BIT_T in response to a pull-down control signal C3N_T applied to the gate of the level adjuster 268 ; and a second bit line level adjuster 269 having an electrode connected to a bit line BIT_B between the third transfer gate 264 and the lower memory cell array block for adjusting a level of the bit line BIT_B in response to a pull down control signal C3N_B applied to the gate of the second level adjuster 269 . The other electrodes of the level adjusters 268 and 269 are applied to Vss (earth potential).

The SAN_C signal is applied to the gate of the NMOS transistor, one electrode of which is connected to the sense amplifier and the other electrode of which is connected to ground potential Vss in order to switch the sense amplifier 260 to "high" or to enable the sense amplifier 260 to switch to "low" or to disabble. Furthermore, the SAP_C signal is applied to the gate of the PMOS transistor, one electrode of which is connected to the sense amplifier and the other electrode of which is connected to a supply voltage connection Vcc in order to set the sense amplifier 260 to "low", or to enable it to set or disable the sense amplifier 260 to "high". The compensation signals C3N_C and C3P_C for the compensation device 261 equalize voltages on the bit lines BIT_T, RBIT_T, BIT_B and RBIT_B on the main and reference cells and on the sense amplifier 260 before the partial word lines SWL1 and SWL2 are activated or enabled. The pulldown control signal C3N_T turns on the first bit line level adjuster 268 when selecting the upper main cell column and the reference cell column to perform a pull down operation and thereby pull the bit lines BIT_T and RBIT_T connected to the upper main memory cell and the reference cell to "low" (low logic level). The pull-down control signal C3N_B, on the other hand, turns on the second bit line adjuster 269 when selecting the lower main cell column and the reference cell column in order to carry out a pull-down operation and thereby thereby the bit lines BIT_T and RBIT_T, connected to the lower main memory cell and the reference cell, to "low" to pull (at low logic level).

A fourth embodiment of a sense amplifier and input / output control according to the present invention for the system of FIG. 8 is described in more detail below.

Fig. 22 shows the fourth embodiment of the sense amplifier and input / output controller according to the following invention for the system of Fig. 8. This controller includes the following: a sense amplifier 270 connected to bit lines BIT_T, RBIT_T, BIT_B and RBIT_B for Reading and amplifying data on corresponding lines in response to sense amplifier activation signals SAP_C and SAN_C from the local control pulse generator; a compensation device 271 in the form of an NMOS transistor for compensating voltages on bit lines BIT_T and RBIT_T or BIT_B and RBIT_B in response to compensation signals C3N_C or C3P_C; first and second NMOS transistors 272 and 273 , each switchable in response to upper cell array connection signals C1N_T or C2N_T from the local control pulse generator for selectively connecting the bit lines BIT_T or RBIT_T, connected to the upper main cell or the reference cell, with an input / output line of the sense amplifier 270 , third and fourth NMOS transistors 274 and 275 , each switchable in response to lower cell array connection signals C1N_B or C2N_B for selectively connecting the bit lines BIT_B or RBIT_B, connected to the lower main cell and the reference cell, with an input / output line of the sense amplifier 270 ; a fifth NMOS transistor 276 connected to the input / output terminal of the sense amplifier 270 for controlling the connection to a data terminal D_ in response to a column selection signal Y_n; a sixth NMOS transistor 277 connected to the input / output terminal of sense amplifier 270 for controlling the connection to an inverted data terminal DB_ (Databar terminal) in response to a column selection signal Y_n; a first bit line level adjuster 278 made of an NMOS transistor having a first electrode connected to a bit line BIT_T between the first NMOS transistor 272 and the memory cell block for adjusting a level of the bit line BIT_T in response to a pull-down control signal C3N_T applied to its gate ; and a second bit line level adjuster 279 in the form of an NMOS transistor having an electrode connected to a bit line BIT_B between the third NMOS transistor 274 and the lower memory cell array block for setting a level of the bit line BIT_B in response to a pull-down control signal C3N_B, the other Gate is created.

The data input / output to or from the aforementioned ferroelectric SWL memory according to the invention is explained in more detail below. FIG. 23 shows a timing chart for the local control pulse generator in a write mode when a Y address is changed in FIG. 17. Since the core block contains the sense amplifier and data input / output control circuit and these are used together by cell blocks adjacent to the core block above and below, the explanation below is intended to relate only to the use of the upper memory cell block. The time operation according to FIG. 23 is described in intervals which divide the period of the CSBpad signal. This signal is a chip enable signal (chip activation signal) which is activated in the "low" state and deactivated in the "high" state. The CSBpad signal comprises the time periods t1 to t14 and changes to "low" before t1 and to "high" at the beginning of the time period t15.

In the t1 interval, the CSBpad signal is activated and kept at "low", while the WEBpad signal is also activated and kept at "low". Both signals remain "low" until the end of period t14. The addresses X, Y and Z are initially kept unchanged, while the signals PS1_T, PS2_T, C1N_T, C2N_T, C4N_T, C3N_C, SAP_C and SAN_C also remain as they are from the local control pulse generator. The PS1_T signal is "high" in the interval t1, "low" in the intervals t2 and t3, "high" in the interval t4, "low" in the interval t5 and "high" in the interval t6. Then the PS1_T signal is kept at "low" at intervals t7, t8, at "high" at intervals t9, t10, at "low" at intervals t11 and t12, and then goes to the beginning of interval t13 to "high" and remains at this level. The signals SWL1 and SWL2 from the SWL driver 300 are "low" in the interval t1 and "high" in the interval t2. The SWL1 signal has a phase opposite to the PS1_T signal, but the same transition time behavior. In contrast, the SWL2 signal has an opposite phase to the signal PS2_T, but also has the same transition time behavior. The signal PS2_T is in the interval t1 to "high", in the intervals t2-t4 to "low", in the intervals t5-t7 to "high", in the intervals t8, t9 to "low", in the intervals t10 , t11 to "high", in the intervals t12, t13 to "low" and in the intervals len t14, t15 again to "high". The waveform changes of the signals C1N_T and C2N_T are described below. These are control signals for the electrical connection of the input / output line of the sense amplifier, a bit line in the memory cell block and a bit line in the reference cell block. The C1N_T signal is only "low" in the interval t3 and is otherwise "high". The interval t3 is a time period in which the signals SWL1 and SWL2 are kept "high" before the Y address signal is switched. The signal C2N_T is also subject to the changeover and changes from "high" to "low" at the beginning of the interval t3, at the same time as the signal C1N_T also changes to "low". Thereafter, the signal C2N_T remains at "low" and changes back to "high" at the same time at which the CSBpad signal also changes to "high", ie at the end of the period t14. The signal C4N_T changes from "low" to "high" at the beginning of the time period t2, that is to say at the same time that the signals SWL1 and SWL2 also change to "high". The signal C4N_T changes back to "low" at the same time that the CSBpad signal changes to "high" or is deactivated (disabled). The signal P2 is "high" during the time periods t2 to t5, ie it changes to "high" at the beginning of the period t2 at the same time as the signals SWL1 and SWL2 change to "high". P2 then changes back to "low" at the beginning of the time period t6 and then remains at this level. The signal C3N_C is "high" until the end of the interval t1 and then changes to "low" at the beginning of the interval t2 when the SWL1 and SWL2 signals also change to "high". The signal C3N_C changes from "low" to "high" only when the CSBpad signal changes to "high". In other words, the C3N_C signal has the same waveform as the C4N_T signal, but has the opposite phase to it. The SAN_C signal changes from "low" to "high" at the time the signals C1N_T and C2N_T change to "low", and is then held high until the CSBpad signal is deactivated or on "high" goes. The SAP_C signal has the same waveform as the SAN_C signal, but has the opposite phase to it. If a Y-ATD signal is generated in accordance with a change in a Y address in the ferroelectric SWL memory described above, the local control pulse generator generates the signals PS1_T and PS2_T in order to cause the SWL driver block 70 to generate the signals SWL1 and SWL2 to create. A logical "0" is written into an SWL memory cell at intervals of the two signals SWL1 and SWL2 when these signals are at "high", that is, at intervals t2-t3, t8 and t12. In contrast, a logical "1" is written into the SWL memory cell, in intervals in which only one of the two signals SWL1 and SWL2 is "high", ie in the intervals t4-t5, t7, t9, t11 and t13.

The operation of the non-volatile ferroelectric memory device according to the present invention is described below in connection with a reading mode. FIG. 24 shows waveforms of the local control pulse generator according to FIG. 17 in the read mode when a Y address is changed.

In reading mode, the WEBpad signal is kept at "high". As with the Write mode, the signal Y-ATD is only set to "high" if the Y- Address is changed. If the Y address changes at the beginning of the interval t7, see above the signal Y-ATD changes to "high" and turns up in the intervals t7 and t8 kept "high". It then changes back to "low" and again at the beginning of the In tervalls t11 is "high" and remains "high" during intervals t11 and t12. It then remains "low" in the remaining intervals. The PS1_T signal is present to "low" in the intervals t2, t3 and t5 and otherwise to "high". The signal PS2_T is kept "low" from the beginning of the interval t2 to the end of the interval t4 and otherwise "high". The SWL1 signal has the same transition times as the signal PS1_T, but a phase opposite to it. On the other hand, that shows SWL2 signal the same transition times as the signal PS2_T on, but to this an opposite phase. The signals C1N_T and C2N_T are control signals for the electrical connection of the input / output line of the reader amplifier, a bit line of a memory cell block and a bit line of a Reference cell block. The signal C1N_T is only "low" in the interval t3. So during a period in which the signals SWL1 and SWL2 before switching direction of the Y address signal are kept "high". The signal C1N_T is used for remain high for the rest of the intervals. The signal C2N_T changes from "high" to "low" at the same time as the signal C1N_T to "low" goes, and is then held at "low" and is then set to "high" again when  the WEBpad signal also goes "high". The signal C4N_T changes from "low" to "high" at the beginning of the interval t4, even if the signal C1N_T to "high" changes, and is only set to "low" again at the time when the CSBpad signal goes "high". The signal P2 is "high" during the time pe periods t2 to t5 and changes to "high" at the same time as the Signals SWL1 and SWL2 go "high", ie at the beginning of the interval t2. It changes back to "low" at the time when the signal SWL1 last changes to "low", ie immediately before the Y address signal is switched. The Signal C3N_C is held at "high" in interval t1 and changes to "low" Start of the interval t2 when the signals SWL1 and SWL2 also change to "high" seln, and is kept "low" until the CSBpad signal on again "high" goes. The signal SAN_C changes from "low" to "high" at the beginning of the inter valls t3, at the same time as the signals C1N_T and C2N_T on go "low" and is held high until the CSBpad signal is on again "high" goes. The signal SAP_C has a phase opposite to the signal SAN_C, however, the same transition times. So only the Y address changes to egg The state in which the CSBpad signal is at "low" shows the Output of the global control pulse generator makes no difference to its on gear. The signals PS1_T and PS2_T from the local control pulse generator change not in read mode, even if the signal Y-ATD changes to "high", namely due to the change of a Y address, so that the signals SWL1 and SWL2 in de activated state (disabled) remain. As a result, the column decode rer activated in accordance with the change of a Y address to read in to deliver amplifier-held data to the data bus. In the present case changes the Y address at the beginning of interval t7 for the first time. Therefore data arrive from the sense amplifier to the data bus to carry out the read operation. At the start of the interval t11, the Y address changes again, so that data from Sense amplifiers are transmitted to the data bus in order to carry out the read operation to lead. Data held in the sense amplifier can only pass on as a result Tet that the column gate selection ge when switching the Y address will change.

So far, the data input / output operation in the ferroelectric SWL memory in the write mode and in the read mode in the case of changing a Y address has been described. The operating waveforms when only X and Z addresses are changed in write and read modes are explained below. When the ferroelectric SWL memory is operated in write mode when the X and Z addresses are switched, it is divided into 21 intervals t1 to t21. Fig. 25 shows the respective operation waveforms in the write mode of the ferroelectric rule SWL memory according to the invention, in the switching of the X, Z addresses in Fig. 17.

First the CSBpad signal is activated by the fact that at the beginning of the Inter valls t1 changes from "high" to "low" and up to the beginning of the interval t21 "low" remains and is then deactivated by t21 at the beginning of the interval changes to "high". This changes at the same time as the CSBpad signal WEBpad signal, which can be regarded as a write activation signal, see above that the WEBpad signal at the beginning of the interval t1 from "high" to "low" changes and is thus activated, and again at the end of the interval t20 "high" changes and is deactivated. Both the CSBpad signal as well the WEBpad signal are external signals. The X and Z addresses change to Start of the intervals t7 and t14, so in the intervals t7 and t14 Signals X-ATD and Z-ATD, ie the signal X, Z-ATD kept at "high". In all at other intervals, these signals are "low". At the beginning of the interval t1 only the signals CSBpad and WEBpad activated or set to "low", while al The other signals initially remain as they are. Remain in the interval t2 the signals CSBpad and WEBpad as they are, while the signals PS1_T, Change PS2_T and C3N_C from "high" to "low". Switch at this time also the signals SWL1, SWL2, C4N_T and P2 from previously "low" to now "high". The signal C4N_T is now activated by going from "low" to "high" externally provided data on a bit line of a memory cell as well given to a bit line of a reference cell. In the interval t3, all are previously mentioned signals (CSBpad, WEBpad, PS1_T, PS2_T, SWL1, SWL2, C3N_C, C4N_T and P2) kept in the state in which they are also in the interval t2 had found. In contrast, the signal SAN_C changes at the beginning of the interval t3 from "low" to "high", while at this point the signal SAP_C from "high" changes to "low". The waveforms of the signals PS1_T and PS2_T then change repeated from "high" to "low" as follows. The PS1_T signal is set to "high" ten in the intervals t1, t4, t6, t7, t8, t11, t13, t14, t15, t18 and t20 and in the rest the intervals to "low". In contrast, the signal PS2_T is kept "high" in the Intervals t1, t5-t8, t12-t15 and t19-t21 and in the remaining intervals "Low". The SWL1 signal changes at the same times as the signal PS1_T,  but has the opposite phase to this. The SWL2 signal change selt at the same time as the signal PS2_T, but also opposite this is the opposite phase. The signal C1N_T is "low" in some In tervallen t3, t10 and t17, in which the signals SWL1 and SWL2 to the same Time is high. The signal C2N_T changes to "low" at the time at which the signal C1N_T changes to "low" and changes to "high" at the time point at which the X and Z ATD signals change to "high". The signal C4N_T changes to "high" at the same time as the signals SWL1 and SWL2 change to "high", and change to "low" again at the time to which the X and Z ATD signals change to "high". The P2 signal changes to "high" at the time when the signals SWL1 and SWL2 on at the same time change to "high" and change back to "low" at the time the Signals SWL1 and SWL2 both assume the "low" state at the same time. The Signal SAN_C has a phase opposite to signal C2N_T, while that Signal SAP_T has a phase that is identical to that of signal C2N_T.

The operating waveforms are explained interval by interval below.

In the interval t4, the signals PS2_T and C1N_T change to "high", and the signal SWL1 from "high" to "low". The signal PS1_T changes from its in the interval t5 previous high state to "low", so that the signal SWL1 from "low" to "high" changes. The signal PS2_T changes from "low" to "high" at the beginning of the In tervalls t5, so that the signal SWL2 changes from "high" to "low". The In begins tervall t6, the signal PS1_T changes from "low" to "high", so that the signal SWL1 changes from "high" to "low". Signal P2 also changes from the previous one State "high" then to "low". In the interval t7, the X and Z addresses change from "low" to "high". The signal C2N_T changes from "low" to "high", the signal C4N_T and the SAN_C signal from "high" to "low" as well as the C3N_C signal and that Signal SAP_C from "low" to "high". If the interval t8 begins, only those change X and Z ATD signals from their previous states "high" to "low" and all other signals remain as they were in the interval t7. The waveform edges The beginning of the interval t9 is the same as the waveform changes in the intervals t2 to t8. Finally, the interval t21 begins the signals CSBpad and WEBpad change to "high" and remain there, so that write mode is deactivated. The signal C4N_T changes from "high" to "low" while the SAN_C signal changes from "high" to "low" and the signal  SAP_C from "low" to "high". In the write mode of the ferroelectric SWL memory chers according to the present invention is thus when the X and of the Z addresses activates the signal C4N_T at a time when the signals SWL1 and SWL2 are also activated. Now data get to the bit line before the sense amplifier is activated.

Operating waveforms for the ferroelectric SWL memory in the read mode when X and Z addresses change are described below. The operating intervals or waveform intervals are the intervals t1 to t21. Fig. 26 shows the corresponding operating waveforms in the case of switching the X and Z addresses in the read mode of the ferroelectric SWL memory shown in Fig. 17. Waveforms in the read mode are compared with those in the write mode to make it clear that there is a difference is present at the transition point of the signal C4N_T. The WEBpad signal is deactivated in the "high" state in read mode. The signal C4N_T is kept at "low" in the intervals t1 to t3. At the beginning of the interval t4, the signal C4N_T is activated and switched from the "low" state to the "high" state. The result of this is that data amplified by the sense amplifier reach the bit line. The signal C4N_T which is set to "high" at the beginning of the interval t4 is kept "high" until the end of the interval t6 and then changes to the "low" state at the beginning of the interval t7 and is kept at "low" until the end of the interval t10, after which it goes back to "high" at the beginning of the interval t11. If the signal C4N_T changes from "low" to "high", data amplified by the sense amplifier are given for data input / output line. After the read amplifier has previously detected data in the read mode, the signal C4N_T is activated (ena bled) in order to be able to transmit the detected data to the data input / output line. The reading operation is carried out in this way.

In the following, the local control pulse generator, the column control and the sense amplifier and input / output control will be described for the case that the memory cell array has the structure shown in FIG. 9. FIG. 27 shows the local control pulse generator for the case of the system of FIG. 9. FIG. 28 illustrates a system of a first embodiment of a sense amplifier and input / output control in accordance with the present invention according to FIG. 9, while FIG. 29 shows a system of a second embodiment of a sense amplifier and input / output controller in accordance with the present invention of FIG. 9. FIG. 30 shows a timing chart for a write mode when a Y address is changed in FIG. 27, FIG. 31 shows a timing chart of a read mode when a Y address is changed in FIG. 27, and FIG. 32 shows a timing chart for a Write mode when X, Z addresses are changed in FIG. 27, and FIG. 33 shows a timing chart in a read mode when X, Z addresses are changed in FIG. 27.

According to the Fig. 27 receives the local control pulse generator in the case of the memory cell system according to FIG. 9, a signal from the global control pulse generator 16 and the Y-ATD signal and a signal from the Z-predecoder 74 for generating control signals for part-word line driver 22 to the sense amplifier and input / output control 25 and for column control 24 . In particular, the signals S1, S2, P2, C3, C4, SAN and SAP are supplied by the global control pulse generator 16 , as well as the Y-ATD signal, as previously described, and last but not least an address transition detector signal, which is generated when the Y address changes. A WEBpad signal, which is a write enable pad signal or write activation signal, defines the activated state in the write mode when it is in the "low" state. "Low" denotes a low logic level and "high" denotes a high logic level.

The local control pulse generator according to the invention and shown in FIG. 27 contains the following: a first logic circuit 100 for generating a signal which is supplied to the sense amplifier and input / output controller 25 , a second logic circuit 101 for generating a signal which is provided to column controller 24 , and a third logic circuit 102 for generating a signal which is provided to partial word line driver 22 . The first logic circuit 100 contains a first logic operator 100 a for the delivery of the signals BS_T, BSB_T, BS_B and BSB_B, a second logic operator 100 b for the delivery of the signals SAP_C and SAN_C and a third logic operator 100 c for the delivery of the signal C3_C. The third logic circuit 102 contains a fourth logic operator 102 a for supplying a signal PS2 and a fifth logic operator 102 b for supplying a signal PS1.

The local control pulse generator is explained in detail below.  

The first logic operator 100 a is used for processing the signals Z-Add1, Add2 Z, Z and Z Add3 Add4. The first logic operator 100 a contains a first NAND gate NAND1 for the logical processing of the signals Z-Add1 and Z-Add2, a second NAND gate NAND2 for the logical processing of the signals Z-Add3 and Z-Add4; a third NAND gate NAND3 for logically processing the signals from the first and second NAND gates NAND1 and NAND2; a first inverter INV1 for inverting a signal from the first NAND gate NAND1; a second inverter INV2 for inverting a signal from the first inverter INV1; a third inverter INV3 for inverting a signal from the second NAND gate NAND2; and a fourth inverter INV4 for inverting a signal from the third inverter INV3. In the present case, the signal from the first inverter INV1 is a signal BS_T for the sense amplifier and input / output controller 25 , while the signal from the second inverter INV2 is a signal BSB_T, specifically for the sense amplifier and input / output Control 25 . The signal BS_T and the signal BSB_T for the sense amplifier and input / output control 25 are control signals for controlling a transmission gate which selectively amplifies an input / output connection of the sense amplifier in the sense amplifier and input / output control 25 with a bit line and one connected in vertical bit line (bit bar line) of the upper main cell block. The signals from the third inverter INV3 and from the fourth inverter INV4 are also supplied to the sense amplifier and input / output controller 25 , specifically as signal BS_B and as signal BSB_B. The signals BS_B and BSB_B are control signals for controlling two transmission gates for connecting a bit line and an inverted bit line (bit bar line) of the lower main cell block with an input / output connection of the sense amplifier. The second logic operator 100 b, which processes the signal from the third NAND gate NAND3 and the signals SAP and SAN from the global control signal generator 76 to supply a signal to the sense amplifier and input / output controller 85 , contains a fourth NAND Gate NAND4 for the logical processing of the signal SAP with the signal from the third NAND gate NAND3; a fifth inverter INV5 for inverting the output signal from the fourth NAND gate NAND4; a fifth NAND gate NAND5 for logically processing the signal SAN with the signal from the third NAND gate NAND3; and a sixth inverter INV6 for inverting the output signal from the fifth NAND gate NAND5. The signal from the fifth inverter INV5 is a signal SAP_C, and the signal from the sixth inverter INV6 is a signal SAN_C. The third logic operator 100 c which combines the signal from the third NAND gate NAND3 to the signal C3 from the global control signal generator 76 to deliver a signal C3_C to the sense amplifier and input / output controller 25 includes a seventh inverter INV7 for inverting the Signals C3, a sixth NAND gate NAND6 for logically processing the signal from the third NAND gate NAND3 with the signal from the seventh inverter INV7; an eighth inverter INV8 for inverting the signal from the sixth NAND gate NAND6; and a new inverter INV9 for inverting the signal from the eighth inverter INV8. The signal C3_C is a control signal for the read amplifier and input / output controller 25 for pulling down the bit line and the inverted bit line (bit bar line) and for controlling the compensation device, not shown, which is used jointly for a plurality of bit lines and inverted bit lines becomes.

The second logic circuit 101 , which is used for the logical processing of the signal C4 from the global control pulse generator 16 , the signal WEBpad and the signal from the third NAND gate NAND3 in order to obtain a signal C4N for the column controller 24 , contains the following: a tenth inverter INV10 to invert the signal WEBpad; an eleventh inverter INV11 for inverting the signal from the tenth inverter INV10; a twelfth inverter INV12 for inverting the signal C4; a seventh NAND gate NAND7 for logically processing the signal from the eleventh inverter INV11 with the signal from the twelfth inverter INV12; a thirteenth inverter INV13 for inverting the signal from the seventh NAND gate NAND7; a fourteenth inverter INV14 for inverting a signal from the third NAND gate NAND3; a first NOR gate NOR1 for the logical processing of a signal from the fourteenth inverter INV14 with a signal from the thirteenth inverter INV13, the NOR gate NOR1 also receiving the signal C3 as an input signal; a fifteenth inverter INV15 for inverting a signal from the first NOR gate NOR1; and a sixteenth inverter INV16 for inverting a signal from the fifteenth inverter INV15. The signal C4N from the second logic circuit 101 is a signal for superimposing a plurality of predecoded Y address signals from the Y predecoder 78 .

The third logic circuit part 102 contains a fourth logic operator 102 a and a fifth logic operator 102 b. The fourth logic operator 102 a for generating the signal PS2 for the SWL driver 22 contains the following: a seventeenth inverter INV17 for inverting the signal P2 from the global control pulse generator 16 ; an eighth NAND gate NAND8 for logically processing the signal Y-ATD, the signal C4 and the signal from the tenth inverter INV10; an eighth tenth inverter INV18 for inverting a signal from the eighth NAND gate NAND8; a delay line D for delaying a signal from the eighth inverter INV18 for a predetermined period of time; a second NOR gate NOR2 for logic processing of the signal S2 with a signal from the delay line D; a third NOR gate NOR3 for logically processing a signal from the second NOR gate NOR2 with a signal from the fourteenth inverter INV14; and a nineteenth inverter INV19 for inverting a signal from the third NOR gate NOR3. The delay line D contains an even number of inverters. The fifth logic operator 102 b to generate the signal PS1 for the SWL driver 22, a fourth NOR gate NOR4 contains the logical processing of the signal S1 from the global control pulse generator 16 and a signal from the eighteenth inverter INV18; a fifth NOR gate NOR5 for logically processing a signal from the fourteenth inverter INV14 and a signal from the fourth NOR gate NOR4; and a twentieth inverter INV20 for inverting the signal from the fifth NOR gate NOR5. In the aforementioned local control pulse generator 20 , the signals S1, S2, P2, C4, C3, SAN and SAP come from the global control pulse generator 16 . The signals Z-Add1, Z-Add2, Z-Add3 and Z-Add4 are supplied by the Z predecoder 14 . The BS_T signal and the BSB_T signal for the sense amplifier and input / output controller 25 are signals for accessing bit lines and inverted bit lines in the upper main cell block. In contrast, the signals BS_B and BSB_B are those for accessing bit lines and inverted bit lines of the lower main cell block.

The following is the operation of the aforementioned local control signal generator tors described in more detail, with regard to the reading mode and Write mode.

First of all, it should be mentioned that in the write mode the WEBpad signal, which passes through the tenth inverter INV10 and the eleventh inverter INV11 and reaches the seventh NAND gate NAND7, is at "low", so that the seventh NAND gate NAND7 is deactivated. The seventh NAND gate NAND7 therefore provides a logic "high" signal at its output. This "high" output signal of the seventh NAND gate NAND7 activates the first NOR gate NOR1 and allows the signal C3 to pass through the fifteenth inverter INV15 and the sixteenth inverter INV16, after which it represents the signal C4N. The signal C3 acts that the signal C4N assumes the "low" state, namely at intervals in which the bit line and the inverted bit line are precharged before SWL1 and SWL2 are enabled or activated. Since all column selection signals are deactivated when the signal C4N is in the "low" state, the signal flow between the output data bus and the bit lines is interrupted, preventing a collision of data on the bit lines with the data on the output data bus when the bit lines are precharged in write mode is changed. Furthermore, since the signal from the tenth inverter INV10 is high in the write mode, the eighth NAND gate NAND8 is activated. As a result, the eighth NAND gate NAND8 is under the control of the Y-ATD signal, the P2 signal and the C4 signal. If the signals S1 and S2 are enabled to be active with the signal P2 in the "high" state under regular conditions, the eighth NAND gate NAND8 is deactivated in order to ensure the regular operation of the signals S1 and S2. After completion of the regular operation of the signals S1 and S2, the signal P2 changes to logic "low", so that the signal from the seventeenth inverter INV17 changes to "high" and activates the eighth NAND gate NAND8. The operation of the eighth NAND gate NAND8 depends on the state of the Y-ATD signal or on the state of the C4 signal. If the signal C4 also has the "high" state while the signal from the tenth inverter INV10 is "high", then the eighth NAND gate NAND8 is finally activated in order to pass the signal Y-ATD to the SWL driver 82 . In other words, if the signals S1 and S2 activate the second NOR gate NOR2 and the fourth NOR gate NOR4 in an interval in which the Y address changes, the Y-ATD signal becomes the fourth NOR gate NOR4 passed through the eighth NAND gate NAND8 and the eighth inverter INV18, while the output signal of the eighteenth inverter INV18 is simultaneously delayed through the delay path D to the second NOR gate NOR2. The Y-ATD signal then passes through the fourth NOR gate NOR4, the fifth NOR gate NOR5 and the twentieth inverter INV20 in order to finally form an inverted and low-lying PS1 signal. The delayed Y-ATD signal passes through the second NOR gate NOR2, the third NOR gate NOR3 and the nineteenth inverter INV19 and finally becomes the inverted and "low" signal PS2. As a result, each of the signals PS1 and PS2 has a phase that is inverted from the Y-ATD signal. The number and size of the inverters in the delay line D can be selected appropriately in order to set the duration of the overlap of the signals PS1 and PS2 when they are "low".

In read mode, the seventh NAND gate NAND7 is deactivated, so that the signal C4 the twelfth inverter INV12, the seventh NAND gate NAND7, the thirteenth Inverter INV13, the first NOR gate NOR1, the fifteenth inverter INV15 and passes through the sixteenth inverter INV16 in order to signal C4N form. The signal C4N thus serves to supply one through the sense amplifier amplified signal to the data bus. Since in this reading mode the signal from tenth inverter INV10 in the "low" state deactivates the eighth NAND gate NAND8 Fourth, a transmission of the signals Y-ATD, P2 and C4 is cut off, which there results in the signal changing from the eighteenth inverter INV18 to "low". because the fourth NOR gate NOR4 is always activated by. This leads to the fact that Signal PS1 and signal PS2 are waveforms opposite to each other Have signals S1 and S2.

The column control has a system according to FIG. 18, even if the local control pulse generator is constructed according to FIG. 27.

A first exemplary embodiment of a sense amplifier and input / output control for the case of a local control pulse generator according to FIG. 27 is described in more detail below with reference to FIG. 28.

Fig. 28 shows a first embodiment of a sense amplifier and input / output control for the case of a local control pulse generator according to Fig. 27. It contains a bit line BIT_T and an inverted bit line BITB_T (bit bar line), each with the upper main cell block are connected, and a bit line BIT_B and an inverted bit line BITB_B (bit bar line), which are each connected to the lower main cell block. Although not shown, there are a plurality of bit lines and bit bar lines (or inverted bit lines) that run in the column direction.

The first embodiment of a sense amplifier and input / output control contains the following: a sense amplifier 85 a for detecting and amplifying data on the bit line and the inverted bit line and for supplying the data to a data line and to an inverted data line (data bar line) ; a pull-down and equalizer 85 b for voltage pull-down and for balancing voltages on the bit line and the inverted bit line; first and second transmission gates 131 a and 131 b for the selective connection of the bit line and the inverted bit line of the upper main cell to the input / output connections of the sense amplifier; third and fourth transmission gates 131 c and 131 d for the selective connection of the bit line and the inverted bit line of the lower main cell to the input / output connections of the sense amplifier; and fifth and sixth transmission gates 131 e and 131 f for selectively connecting the data line and the inverted data line to the input / output terminals of the sense amplifier. The sense amplifier 85 a may further include a PMOS transistor PM10 and an NMOS transistor NM10 for activation and deactivation control. The signal SAP_C and the signal SAN_C for controlling the PMOS transistor PM10 and the NMOS transistor NM10 come from the local control pulse generator 20 and are used jointly for a plurality of bit lines and in vertical bit lines. If in the aforementioned sense amplifier and input / output control 25 of the sense amplifier 85 a to detect data of the upper main cell, the first and second transmission gates 131 a and 131 b are switched on, while the third and fourth transmission gates 131 c and 131 d can be switched off. In contrast, if the sense amplifier 85 a is to detect data from the lower main cell, then the first and second transmission gates 131 a and 131 b are switched off and the third and fourth transmission gates 131 c and 131 d are switched on. Each of the transmission gates 131 a, 131 b, 131 c and 131 d contains the PMOS transistor PM and the NMOS transistor NM lying parallel to one another, the signals BS_T and BSB_T each for switching the first and second transmission gates 131 a on and off and 131 b are used and come from the local control signal generator 20 . In contrast, the signals BS_B and BSB_B be supply gate for turning on and off of the respective third and fourth Übertra 131 c and 131 d is used, whereby these signals come from the local control signal generator 20th The Y address signal and the inverted Y address signal (Y address bar signal), each coming from the column controller 24 , are used as signals Y_n and YB_n, both signals being control signals, with the aid of which the fifth and sixth transmission gate 131 e and 131 f are switched on and off.

FIG. 29 shows a second exemplary embodiment of a sense amplifier and input / output control in the event that the local control pulse generator according to FIG. 27 is constructed. Here are NMOS transistors 140 a, 140 b, 140 c, 140 d, 140 e and 140 f in place of the transfer gates 131 a, 131 b, 131 c, 131 d, 131 e and 131 f shown in FIG. 28. The sense amplifier and input / output controller 25 with the transfer gates according to FIG. 28 is preferably used in a low voltage operation, in comparison to the sense amplifier and input / output controller 25 with NMOS transistors according to FIG. 29 The aforementioned sense amplifier and input / output controller 25 receives signals from the local control pulse generator 20 and from the column controller 24 to detect data and to supply it from the memory cell to the data bus line or inverted data bus line in the read mode and to supply data in the write mode, which have been obtained via the data bus line and the inverted data bus line.

Fig. 30 shows input and output waveforms for explaining the operation of the local control pulse generator in the case of a memory cell array shown in Fig. 9. It is a timing chart for the write mode when changing a Y address in the event that CSBpad signal is ena bled, ie is in the "low" state. The time period in which the CSBpad signal is at "low", that is to say the chip enable signal, is divided into intervals t1 to t15. At the beginning of the interval t15 or at the end of the interval t14, the CSBpad signal goes back to "high", so that it is deactivated or disabled.

In the interval t1, the CSBpad signal is activated and is at logic "0", while the WEBpad signal is also activated and at logic "0". In this case, the X, Y and Z addresses are the same as before, and the signals PS1 and PS2 as well as the signals C4N, C3_C, SAP_C and SAN_C retain the states that they had before. The PS1 signal is held at "high" in interval t1, at "low" from the beginning of interval t2 to the end of interval t3, at "high" at interval t4, at "low" at interval t5, at "high" in the interval t6, to "low" in the intervals t7 and t8, to "high" in the intervals t9 and t10, to "low" in the intervals t11 and t12, and to "high" in the intervals t13, t14 and t15 , The signal PS2 is held "high" until the end of the interval t1 and then changes to "low" for the intervals t2 to t4. Then it goes to "high" at the beginning of the interval t5 and remains at "high" until the end of the interval t7. In the intervals t8 and t9, the signal PS2 is at "low", in the intervals t10, t11 at "high", in the intervals t12, t13 at "low" and in the interval t14 and then again at "high". The signals SWL1 and SWL2 from the SWL driver 22 remain "low" in the interval t1 and therefore assume the same state as before. They both change to "high" at the beginning of interval t2. In the present case, the signal SWL1 has the opposite phase to the signal PS1, but has the same transition times. The signal SWL2 has an opposite phase to the signal PS2, but also has the same transition times as this. The signal C4N from the local control pulse generator 20 changes to "high" at the beginning of the interval t2 and then again to "low" at the point in time at which the CSBpad signal is deactivated. The signal P2 first changes from "low" to "high" at the beginning of the interval t2 and is held at "high" until the end of the interval t5 and then changes to "low" when the interval t6 begins. Then it doesn't change anymore. The signal C3_C is kept at "high" until the interval t1 has elapsed and changes to "low" at the beginning of the interval t2 and remains there until the CSBpad signal is deactivated. Together with this, the C3_C signal is set to "high" again. The signal SAN_C is kept "low" until the end of the interval t2 and changes to "high" at the beginning of the interval t3 and remains there until the CSBpad signal is deactivated. The SAP_C signal and the SAN_C signal have opposite phases, but the same transition times. The above-mentioned operation flow diagram of the local STEU erpulsgenerators FIG. 13 shows that if only the Y address changed AEN while the CSBpad signal remains in the "low" state, no change of the signal occurs, the global control pulse generator 16 is to be supplied, with no change in the signal that is finally supplied by the global control pulse generator 16 . If the Y-ATD signal is generated in write mode by changing the Y address, then the local control pulse generator 22 supplies the signals PS1 and PS2 for the purpose of generating the signals SWL1 and SWL2 in the SWL driver 22 .

Begins according to the chart of FIG. 30 to change the Y address for the first time, so in the intervals t7 and t9, respectively, a logic "1" ( "high") is written into the memory cell and in the interval t8 a logic "0 "(" low ") written into the memory cell. If the Y address changes a second time at the beginning of the interval t11, a logical "1"("high") is written into the memory cell in the intervals t11 and t13, while a logical "0"("low") is written into the memory cell.

The timing diagram for the reading mode of the local control signal generator according to the invention is described in more detail below. As with the write mode, the procedure is presented interval by interval, with the total of intervals t1 to t15 being available. FIG. 31 shows the operating sequence diagram of the local control pulse generator for the read mode when only the Y address changes and the memory cell system according to FIG. 9 is formed.

In contrast to the write mode, the WEBpad signal is held at "high" from the beginning of the interval t1, as shown in FIG. 31, while the CSBpad signal is activated or is at "low". This is because the reading mode is affected here. Similar to the write mode, the Y-ATD signal only changes to "high" when the Y address changes. If the Y address changes at the beginning of the interval t7, the signal Y-ATD is kept at "high", specifically during the periods t7 and t8. If the Y address changes again at the beginning of the interval t11, the signal Y-ATD is now held high again, namely from the beginning of the interval t11 to the end of the interval t12. Otherwise the Y-ATD signal remains at "low". The signal PS1 is "low" from the beginning of the interval t2 to the end of the interval t3 and in the interval t5 and is otherwise kept "high" in the other intervals. The signal PS2 is kept from the beginning of the interval t2 to the end of the interval t4 at "low" and is otherwise at "high" in the rest of the intervals. The signal SWL1 has transition times identical to the signal PS1, but a phase opposite to it. The signal C4N is "high" from the beginning of the interval t4 to the interval t15 and then goes to "low" when the signal CSBpad is deactivated. In the rest of the intervals t1 to t3, the signal C4N is "low". Since the signals P2, C3_C, SAN_C and SAP_C have the same transition times and phases as the corresponding signals in write mode, they will not be described again. As can be seen from the timing diagram, there is no change to an input to the global control signal generator if only the Y address changes while the CSBpad signal is activated or is "low". As a result, there is no change in the output from the global control signal generator. The signal PS1 and the signal PS2 from the local control pulse generator 20 do not change in the read mode, even if the signal Y-ATD changes to "high" because of the change in the Y address, so that the signals SWL1 and SWL2 de remain activated , Therefore, the column controller 24 is activated in accordance with the change in the Y address to transmit the data held in the sense amplifier to the data bus. If the Y address changes at the beginning of the interval t7, data present in the sense amplifier are supplied to the data bus in order to carry out the read operation. In addition, if the Y address changes again at the beginning of the interval t11, data is also supplied to the data bus in the sense amplifier in order to carry out the reading operation.

So far, timing diagrams for a nonvolatile ferroelectric memory in the write mode and read mode have been explained when only the Y address changes. In the following, timing diagrams for a non-volatile ferroelectric memory in the write mode and read mode will be described when only the X and Z addresses change. Fig. 32 shows an operational flowchart of the local control pulse generator in the write mode in which only the X and Z address changes. The operating sequence is divided into time intervals t1 to t21.

First, the CSBpad signal is activated by changing from "high" to "low" at the beginning of the interval t1. At the beginning of the interval t21, it then changes to "high" in order to be deactivated. At the same time the WEBpad signal, ie the write enable signal, is set from "high" to "low", ie at the beginning of the interval t1, and at the same time it changes back to "high" like the CSBpad signal. Both the CSBpad signal and the WEBpad signal are external signals. Referring to FIG. 32, only the signals CSBpad and WEBpad are in the interval t1 activated, while all other signals remain as they were before. The signals CSBpad and WEBpad remain activated in the interval t2, as before, but where at the beginning of the interval t2 the signals PS1, PS2 and C3_C change from "high" to "low". The signals SWL1, SWL2, C4N and P2 also change at the beginning of the interval t2, namely from "low" to "high". Changes the signal C4N from "low" to "high", so it is activated, data from the outside on the bit line BL and the inverted bit line BBL are given. In the interval t3, all signals CSBpad, WEBpad, PS1, PS2, SWL1, SWL2, C3_C, C4N and P2 retain their levels already present in t2, while the signal SAN_C changes from "low" to "high" at the beginning of the interval t3 and to at the same time the signal SAP_C changes from "high" to "low". As can be seen, the signals SAN_C and SAP_C have the same transition times, but are opposite in phase. So they are inverted to each other. At the beginning of the interval t4, only the signals PS1 and SWL1 change their previous states, the signal PS1 changing from "low" to "high" and the signal SWL1 changing from "high" to "low". At the beginning of the interval t5, only the signals PS1, PS2, SWL1 and SWL2 change their states, while the rest of the signals remain at the level according to interval t4. In other words, the signal PS1 changes from "high" to "low", after which the signal SWL1 changes from "low" to "high". The signal PS2 changes from "low" to "high", and subsequently the signal SWL2 changes from "high" to "low". At the beginning of the interval t6, all signals except for the signals PS1, SWL1 and P2 remain at the previous levels. The signal PS1 changes from "low" to "high" and then the signal SWL1 from "high" to "low". Furthermore, the signal P2 changes from "high" to "low". At the beginning of the interval t7, the X and Z addresses begin to change. As a result, the signals X- and Z-ATD change from "low" to "high". The signals C4N and SAN_C also change from "high" to "low", while the signals C3_C and SAP_C change from "low" to "high". At the beginning of the interval t8, only the X and Z-ATD signals change from "high" to "low", while all other signals with the exception of the X and Z-ATD signals remain at their levels in the interval t7. If the interval t9 begins, only the signals X- and Z-ATD, SAN_C and SAP_C keep their previously assumed levels, while all other signals change. In other words, the signals PS1 and PS2 change from previously "high" to now "low", the signals SWL1 and SWL2 from before to "low" to now "high" and the signals C4N and P2 from previously "low" to "high"". The signal C3_C also changes from "high" to "low". Since the signal C4N is activated by changing from the "low" state to "high", data can now be loaded from external to the bit line BL and the inverted bit line BBL. At the beginning of the interval t10 the signal SAN_C changes from "low" to "high" and the signal SAP_C changes from "high" to "low". All other signals remain in the states that they had already assumed in the interval t9. At the beginning of the interval t11, the signal PS1 changes from previously "low" to now "high", and the signal SWL1 changes from previously "high" to now "low". All other signals remain in the states that they had already assumed in the interval t10. At the beginning of the interval t12, the signal PS1 changes from previously "high" to now "low", and the signal PS2 changes from previously "low" to now "high". This leads to the change of the signal SWL1 from previously "low" to now "high" and to the change of the signal SWL2 from previously "high" to now "low". All other signals remain at the level they had already reached in the interval t11. At the beginning of the interval t13, only the signals PS1, SWL1 and P2 are changed, while all of their signals remain at the levels they already had in the interval t12. In other words, the signal PS1 is now changed from "low" to "high" and the signal SWL1 from "high" to "low". The signal P2 changes from previously "high" to now "low". The interval t14 then begins, and at this point the X and Z addresses change the second time. As a result, the X and Z ATD signals change from previously "low" to now "high", while the signals C4N and SAN_C change from previously "high" to now "low". In addition, the signals C3_C and SAP_C change from previously "low" to now "high". At the beginning of the interval t15, only the X and Z ATD signals change from previously "high" to now "low", while all other signals remain at the levels they already had in the interval t14. At the beginning of the interval t16, the signals PS1 and PS2 change from. "high" to "low", so that the signals SWL1 and SWL2 change from previously "low" to "high". Since the phases and transition times from the interval t17 to the interval t20 are identical to those from the interval t10 to the interval t13, no further description is given. At the beginning of the interval t21, the signals CSBpad and WEBpad are set from "low" to "high", so that the write operating mode is deactivated or disabled. The signal C4N changes from "high" to "low", while the signal SAN_C changes from "high" to "low" and the signal SAP_C changes from "low" to "high". If the X and Z addresses change in write mode, the local control signal generator according to the invention is activated at the same times as the signals SWL1 and SWL2 are activated. Thus, data can be delivered to the bit lines before the sense amplifier is activated.

The operation of the local control signal generator according to the present invention is explained below for the case where the X and Z addresses change in the read mode. FIG. 33 shows a timing diagram of the local control pulse generator in the read mode when the X, Z addresses change, it being possible to recognize that the transition time of the signal C4N in the read mode according to FIG. 33 is different from that according to FIG. 32 32 that the WEBpad signal is activated to "low" for the write mode in the timing diagram according to FIG. 32, while the WEBpad signal is activated to "high" in the read mode according to FIG. 33. Since, with the exception of the signal C4N in FIG. 33, all other signals are designed and run in the same way as in the write mode when the X and Z addresses are changed, only the C4N signal is explained in more detail below. According to FIG. 33, the signal C4N is kept "low", namely from the beginning of the interval t1 to the end of the interval t3. At the beginning of the interval t4, the signal C4N changes from "low" to "high", so that data amplified by the sense amplifier can be fed onto the data line or into the vertical data line. The C4N signal remains "high" from the beginning of the interval t4 to the end of the interval t6 and then changes to "low" from the beginning of the interval t7 to the end of the interval t10. At the beginning of the interval t11, the signal C4N changes back to "high", so that data amplified by the sense amplifier can now be applied to the bit line and the inverted bit line (bit bar line). After the sense amplifier has previously detected the data, the signal C4N is activated in the read mode in order to be able to output the detected data to the data line and inverted data line in order to carry out the reading operation in this way.

The sense amplifier and input / output controller 25 as well as the operation of the input / output bus controller 26 for connection to an external data bus, both of which are shown in FIG. 10, will be described in more detail below. Fig. 34 shows a cell array block system diagram with cores of ferroelectric SWL memory in accordance with a preferred embodiment of the present invention, identical to the cell array of Fig. 7. More specifically, Figs. 19 to 22 and 28 to 29 show a sense amplifier , currency rend the Fig. 34 shows a plurality of core blocks 601, of which as many as external data buses are provided. Each of these core blocks 601 has a plurality of sense amplifiers. Fig. 35 shows a system block diagram of a first embodiment of a sense amplifier in accordance with the present invention. Fig. 36 shows a system block diagram of a second embodiment of a sense amplifier in accordance with the present invention, and Fig. 37 shows a system block diagram of a third embodiment of a sense amplifier in accordance with the present invention. The Fig. 38 further shows a system block diagram ei nes fourth embodiment of a sense amplifier according to the present invention. Figs. 35 and 36 relate to a system of sense amplifiers in the event that a memory cell sub-block includes a main memory cell and a reference memory cell of FIG. 8. In contrast, FIGS. 37 and 38 each relate to a system of sense amplifiers in the event that a memory cell sub-block has a bit line and an inverted bit line (bit bar line). Each of the sense amplifier blocks 301 according to the present invention includes a system with a sense amplifier corresponding to the system of columns of sub-memory cell blocks shown in FIGS. 8 or 9. Although each of the sense amplifiers has a system according to FIGS. 19 to 22 and 28 to 29 for simplification, there are only main cell bit lines BIT_T_n, BIT_T_n + 1, BIT_T_n + 2, BIT_T_n + 3 and inverted bit lines (bit bar lines) BITB_T_n, BITB_T_n + 1, BITB_T_n + 2, BITB_T_n + RB + 1 + RBITT-T + 1 or RBIT cells and a data connection D_ or an inverted data connection DB_ are shown. The first embodiment of a sense amplifier block 301 according to the present invention includes two sense amplifiers 302 , provided that there are four columns of main memory cell blocks, as shown in FIG. 8. Since there are four columns of main memory cell blocks and two columns of reference memory cell blocks in Fig. 8, four sense amplifiers are required for the four columns of main memory cell blocks. However, since the sense amplifiers are present both at the top and at the bottom with respect to the main memory cell block, ie two at the top and at the bottom, a sense amplifier block 301 has a structure as shown in FIG . The second embodiment of a sense amplifier block 301 according to the present invention is identical to the first embodiment, but there are now four sense amplifiers 302 according to FIG. 36. This is necessary in a case where there are eight columns of main memory cell blocks and two columns of reference memory cell blocks. The third exemplary embodiment of a sense amplifier block according to the present invention applies to a case in which memory cells have bit lines and inverted bit lines without reference memory cells, as shown in FIG. 9, this exemplary embodiment having two read amplifiers according to FIG. 37. The fourth embodiment of a sense amplifier block according to the present invention is identical to the third embodiment, but includes four sense amplifiers as shown in FIG. 38. The sense amplifier blocks according to the first to fourth embodiments have bit lines and inverted bit lines, respectively, in the up and down directions Gradient obligations for reading memory cells in the upper and lower Rich, said data terminals D_ sever more are connected in upper and lower directions 302 in FIGS. 35 and 36 with each of the Le to the SpeI cherzellen in upper and lower directions read to. According to FIGS. 37 and 38, data D_ terminals and inverted data terminals DB_ are connected to the sense amplifiers 302nd

An input / output bus control in the aforementioned sense amplifier block is explained in more detail below with reference to the drawing. Fig. 39 shows a circuit system of a first embodiment of an input / output bus control in a ferroelectric SWL memory in accordance with the present invention, while Fig. 40 shows a circuit system of a second embodiment of an input / output bus control in a ferroelectric SWL memory according to the present invention shows. Fig. 41 shows a circuit system of a third embodiment of an input / output bus control in a ferroelectric SWL memory according to the present invention, while Fig. 42 shows a circuit system of a fourth embodiment of an input / output bus control in a ferroelectric SWL- Memory according to the present invention shows. Fig. 43 shows a circuit system of a fifth embodiment of an input / output bus control in a ferroelectric SWL memory in accordance with the present invention, while Fig. 44 shows a circuit system of a sixth embodiment of an input / output bus control in a ferroelectric SWL Memory according to the present invention. The data bus and the input / output bus control have different systems, depending on whether the data input / output of a sense amplifier takes place via the same data bus ( FIGS. 39 and 40) or not ( FIGS. 41, 42, 43 and 44) and whether the memory cell array has memory cell sub-blocks and reference cell sub-blocks (FIGS . 39, 41 and 43) or bit lines and inverted bit lines or bit bar lines (FIGS . 40, 42 and 44).

In the first exemplary embodiment of an input / output bus control according to the present invention, there are four sense amplifier blocks in each of the cell array blocks, the cell array system being designed according to FIG. 8, the data input and output of the sense amplifier taking place via the same data bus. That is, as shown in Fig. 39, that the first embodiment of the input / output bus control includes the following: four first switching units 303 for switching data from the data terminal D_ of the sense amplifier block in response to a hold enable signal LED (Latch Enable Signal) ; four buffer units 304 for buffering or storing the data from the first switching units in response to the hold activation signal LED; four second switching units 305 for routing the data stored in the buffer units 304 back to the buffer units 304 in order to store them there, in response to the hold activation signal LED; four third switching units 306 for transmitting the data stored in the buffer units 304 to external data buses Dinout_Bus_0, Dinout_Bus_1, Dinout_Bus_2 and Dinout_Bus_3 in response to a read / write signal WRS; and four fourth switching units 307 for supplying data from the external data buses Dinout_Bus_0, Dinout_Bus_1, Dinout_Bus_2 and Dinout_Bus_3 to the respective data connections D_ of the amplifier blocks in response to the read / write signals WRS. Each of the first, second, third and fourth switching units 303 , 305 , 306 and 307 contains a transmission gate, the buffer unit 304 having two or more than two inverters, but in each case an even number of inverters, with output data in the buffer memory 304 as well as held by the second switching unit 305 .

The second embodiment of an input / output bus controller according to the present invention is constructed as shown in FIG. 40. This input / output bus control is identical to that according to the first exemplary embodiment, with the exception that the cell array contains bit lines and bit bar lines (inverted bit lines) according to FIG. 9 and the bus line has the following system: data buses Dinout_Bus_0 and Dinout_Bus_1 and inverted data buses (buses for inverted data) DBinout_Bus_0 and DBinout_Bus_1. Accordingly, a cell array block has four sense amplifier blocks, each having a data connection and an inverted data connection, so this is the system consisting of the first, second, third and fourth circuit units 303 , 305 , 306 and 307 and the buffer parts 304 the first embodiment, except that eight of them are required because they should be connected to the data ports and the inverted data ports of each sense amplifier block.

The third embodiment of the input / output bus control according to the present invention is explained below with reference to FIG. 41. The third embodiment of the input / output bus control is provided in the event that the cell array has a system as shown in Fig. 8, where each of the cell array blocks has four sense amplifier blocks and input and output data buses separately.

In this third exemplary embodiment of the input / output bus control, four fifth switching units 308 are provided for supplying data from external data bussen_Din_Bus_0, Din_Bus_1, Din_bus_2 and Din_Bus_3 to the sense amplifier blocks 301 in response to a write activation signal WE, four sixth switching units 309 for outputting data from the data connections D_ of the sense amplifier blocks 301 in response to a hold activation signal LED, four buffer units 310 for buffering the data from the sixth switching units 309 in response to the hold activation signal LED, four seventh switching units 311 for returning the data buffered in the buffer units 310 into the Buffer units 310 in response to the hold activation signal LED, and four eighth switching units 312 for the final output of the data stored in the buffer units 310 for external data buses Dout_Bus_0, Dout_Bus_1, Dout_Bus_2 and Dout_Bus_3 in response to an output activation signal OE. The fifth, sixth, seventh and eighth switching units 308 , 309 , 311 and 312 each have a transmission gate, the buffer unit 310 having two or more inverters, but an even number of inverters.

Hereinafter, the fourth embodiment of the input / output bus control according to the present invention will be described with reference to FIG. 42. The fourth embodiment of the input / output bus control is provided for a case in which the cell array has a structure as shown in Fig. 9 and data input and output buses are provided separately. Although the fourth embodiment of the input / output bus control is identical to the embodiment shown in Fig. 41, since each of the sense amplifier blocks 301 in the fourth embodiment has a data terminal D_ and an inverted data terminal DB_, the fourth embodiment has the input / output bus control twice more switching units than the third embodiment, since each of the data connections and the inverted data connections should be equipped with switching units for controlling data on each of the connections.

A fifth embodiment of an input / output bus controller according to the present invention is shown in FIG. 43. The fifth exemplary embodiment is provided for the case in which the cell array according to FIG. 8 is constructed and data input buses and data output buses are provided separately for easier data input / data output. The fifth embodiment of the input / output bus control includes ninth switching units 313 for supplying data from the data buses Din_Bus_0, Din_Bus_1, Din_Bus_2 and Din_Bus_3 to the data connections D_ in each of the sense amplifier blocks in response to a write activation signal WE when there is an external write activation signal and an output activation signal is available, as well as tenth switching units 314 for supplying data from the data terminals D_ of each amplifier block to the data buses Dout_Bus_0, Dout_Bus_1, Dout_Bus_2 and Dout_Bus_3 in response to the output activation signal OE.

The sixth embodiment of the input / output bus control according to the present invention is shown in FIG. 44. This sixth embodiment is identical to the fifth embodiment with the exception that the cell array is formed in accordance with FIG. 9 and includes bit lines and inverted bit lines. This means that a data connection D_ and an inverted data connection DB_ are provided for each of the sense amplifier blocks and that a circuit unit is provided for input / output of data to each connection or each connection.

Systems of data buses in accordance with the previously described embodiments are presented below. The Fig. 45 shows a Sy stem of a first embodiment of a data bus in accordance with the present invention, while Figure 46 is a system of a second embodiment of a data bus in accordance with the present displays. The invention. Fig. 47 shows a third embodiment of a data bus according to the invention, while Fig. 48 shows a fourth exemplary embodiment of a data bus according to the invention.

The first exemplary embodiment of a data bus according to FIG. 45 is provided in the event that the data input / output takes place via the same bus as indicated in FIG. 39. Thus, if there are four core blocks 601 for a cell array block, four common input / output data bus lines are required. If a cell array block contains four main cell sub-blocks, each sense amplifier block contains two sense amplifiers and data input / output to or from a sense amplifier in each of the sense amplifier blocks is via a data bus.

The second exemplary embodiment of a data bus according to the invention according to FIG. 46 serves for the case in which the data input / output takes place via the same bus, but with separate data buses and inverted data buses according to FIG. 40.

The third embodiment of a data bus according to the invention shown in FIG. 47 for a ferroelectric SWL memory is used in the event that the data input / data output takes place via separate buses, as shown in FIGS . 41 and 43.

Fig. 48 shows the fourth embodiment of a data bus according to the invention for a ferroelectric SWL memory, this exemplary embodiment serving for the case that the data input / data output via separate data input buses Din_Bus and DBin_Bus and data output buses Dout_Bus and DBout_Bus, as in the FIGS. 42 and 44 shown.

The operation of the input / output bus control according to the present invention is explained below. Fig. 49 shows a signal flow chart for explaining the operation of the input / output bus control according to the first embodiment of the invention, Fig. 50 shows a signal flow chart for explaining the operation of the input / output bus control according to the second embodiment of the invention and FIG. 51 is a signal flow chart for explaining the operation of the input / output bus control according to the third embodiment of the invention.

In a system with a cache memory, random access is provided by a CPU to the main memory, which in connection with such a cache memory cher is used, usually by the cache, the information in Receive block units from RAM. To transfer data in block units too data can be accessed when the column address changes the row address remains fixed, or it is limited to a few bits of Spal ten addresses accessed one after the other. A quick column access function great attention is therefore paid to data with high Ge speed is accessed when the column address changes and fixed line address. There are "m" bit lines, each of which has a Le has stronger. While the SAN and SAP signals, the sense amplifier activation signals  are activated, m bits of data are amplified and ge hold in sense amplifiers connected to the bit lines. The longest time in reading is for creating the row address and for the Detection of the data needed. Therefore, when reading the data, m bits become sel ben time detected while only the column address is changed, the Significantly reduce the access time period, resulting in a faster read opera tion leads. Reading data after activating a column selection line a specific address and reading data from other addresses at fixed Row address can be up to "m" data bits.

Fig. 49 shows waveforms for a case when only one column in a row is selected. If data is loaded from the sense amplifiers to the data buses D_Bus_0, D_Bus_1, D_Bus_2 and D_Bus_3 after the end of a sense amplifier operation, a pulse which is high is output in order to enable or disable an output hold signal LED. As a result, the data of the sense amplifier are held in the latch, which means that the data are still available even if the sense amplifiers are deactivated.

The operating timing chart of the input / output bus controller of FIG. 50 ak tivated column address signals Y_T_0, Y_T_1, Y_T_2 Y_T_3 and in these rows follow expansion by an activation period of the sense amplifier in Le semodus. In this case, the row address signal remains fixed at one, and the output hold signal LED remains enabled.

In the operation timing chart of the input / output bus controller of FIG. 51 are column address signals Y_T_0, Y_T_1, Y_T_2 and Y_T_3 in these rows follow activated, after expansion of an activation time period of the Le sever stärkers in the read mode, when the output holding signal LED is activated only for a period of time, sufficient to store data in the hold buffer portion of core block 601 and is disabled until the following data is provided. The following column address signals Y_T_0, Y_T_1, Y_T_2 and Y_T_3 can thus be activated very quickly, which leads to a high column access speed.

The previously mentioned ferroelectric SWL memory and its control scarf tion have several advantages.  

Because partial word lines are used, which are also used as a cell plate in a fer serve electrical storage, the packing density of the memory can be increased hen and its efficiency, since now when reading data and when writing of data no longer requires a separate plate line control signal.

It has already been mentioned that in the conventional ferroelectric memory only one reference cell is used when the main memory is a few hundred times read and that under certain circumstances the ferroelectric Eigen properties of the reference cell. The reference cell becomes even more common used, their properties can deteriorate greatly, resulting in egg ner unstable reference voltage would lead. In the Spei invention Certainly this is not the case since there are significantly more reference cells are. Deterioration in the properties of the reference cells in the course of loading drive of the memory can thus be largely avoided.

Furthermore, the CSBpad signal in the memory according to the invention is only used as a signal used to activate the memory, since in the invention the signals X-, Y- and Z-ATD can be used together with the CSBpad signal. This leads to egg nem more effective management of the storage operation, such that a ver results in greater chip access speed by activating the fast column access mode. When changing the address, either who only changed the X and Z addresses or only the Y address and continued operation after receiving the CSBpad signal, the X, Y and Z ATD signals are suppressed even when they are received. If only the X- and Z addresses changed, the operation undercuts when the CSBpad signal is activated Use of the X and Z ATD signals since no valid data in the read ver are held stronger. If, on the other hand, only the Y address is changed, the read will read more data, since the sub-word lines SWL1 and SWL2 or whose signals are fixed for the row address. The regular writing operation can be executed using the Y-ATD signal in write mode.

According to the invention, the data input and the data output for a A plurality of columns are executed using the same data bus using the fast column access function where Data can be accessed quickly when the column address changes and the row address remains constant.  

The data 00751 00070 552 001000280000000200012000285910064000040 0002019923979 00004 00632 output / data output for a plurality of columns over the same Data bus also leads to a simplification of the layout of the memories device and a reduction in the chip area.

As already explained above, in the invention, the data are output from the sense amplifier, but not to a data bus that is directly connected to other different cell array blocks. Rather, the data passes through core block 601 , resulting in a reduction in the output load on the sense amplifier's output port and an increase in input / output rates.

Claims (18)

1. Ferroelectric memory with:
a cell array ( 400 ) with a plurality of sub-word lines (SWL or split word lines) and a plurality of bit lines for storing data;
a SWL driver ( 300 ) (partial word line driver) for driving each of the partial word lines (SWL) in the cell array ( 400 );
a plurality of sense amplifier blocks ( 301 ) for detecting data on each of the bit lines in the cell array ( 400 );
an input / output bus controller ( 26 ) as an interface between the sense amplifier blocks ( 301 ) and data buses for outputting the data contained in each of the sense amplifier blocks ( 301 ) and for entering data to be written, characterized in that
each of the cells in the cell array ( 400 ) is connected to a pair of first and second partial word lines and a pair of first and second bit lines and
each of the cells in the cell array ( 400 ) has:
a first transistor whose gate electrode is connected to a first partial word line and whose source electrode is connected to a first bit line,
a second transistor whose gate electrode is connected to a second partial word line and whose source electrode is connected to a second bit line,
a first capacitor, the first connection of which is connected to the drain electrode of the first transistor and the second connection of which is connected to the second partial word line,
a second capacitor, the first terminal of which is connected to the drain electrode of the second transistor and the second terminal of which is connected to the first partial word line. 2. Ferroelectric memory according to claim 1, characterized in that the input / output bus control ( 26 ) contains the following:

• - a plurality of first switching units ( 303 ) for switching data from data connections (D_) of the sense amplifier blocks ( 301 ) in response to a hold activation signal (LE);
• - a plurality of buffer units ( 304 ) for buffering or temporarily storing the data from the first switching units ( 303 );
• - a plurality of second switching units ( 305 ) for returning and storing the data stored in the buffer units ( 304 ) in response to the hold activation signal (LE);
• - a plurality of third switching units ( 306 ) for the final output of the data stored by the second switching units ( 305 ) and the buffer units ( 304 ) to an external data bus (Dinout_Bus) in response to a read / write signal (WRS); and
• - A plurality of fourth switching units ( 307 ) for transmitting data from the external data bus (Dinout_Bus) to a data connection (D_) on each of the sense amplifier blocks ( 301 ) in response to the read / write signal (WRS).

3. Ferroelectric memory according to claim 2, characterized in that the first, second, third and fourth switching units ( 303 , 305 , 306 and 307 ) contain transmission gates. 4. Ferroelectric memory according to claim 2, characterized in that the buffer device ( 304 ) contains two or more inverters, preferably an even number of inverters. 5. Ferroelectric memory according to claim 2, characterized in that the Hold activation signal (LE) Column address signals (Y_T_0; Y_T_1; Y_T_2 and Y_T_3) activated one after the other, namely after extending the activation period of the Sense amplifier in read mode. 6. Ferroelectric memory according to claim 1, characterized in that the input / output bus control ( 26 ) contains the following:

• - a plurality of first switching units ( 303 ) for switching data from data connections (D_) and inverted data connections (DB_) of the sense amplifier blocks ( 301 ) in response to a hold activation signal (LE);
• - a plurality of buffer units ( 304 ) for buffering or temporarily storing the data from the first switching units ( 303 );
• - A plurality of second switching units ( 305 ) for returning the data stored in the buffer units ( 304 ) to the buffer units ( 304 ) and for re-storage in the buffer units ( 304 ) in response to the hold activation signal (LE);
• - a plurality of third switching units ( 306 ) for the final output of the data stored by the second switching units ( 305 ) and the buffer units ( 304 ) to an external data bus (Dinout_Bus) and an inverted data bus (DBinout_Bus) in response to a read / write signal ( WRS); and
• - A plurality of fourth switching units ( 307 ) for supplying data from the external data bus (Dinout_Bus) and for supplying data from the inverted data bus (DBinout_Bus) each to a data connection (D_) and inverted data connection (DB_) on each of the sense amplifier blocks ( 301 ) in response to the read / write signal (WRS).

7. Ferroelectric memory according to claim 1, characterized in that the input / output bus control ( 26 ) contains the following:

• - a plurality of fifth switching units ( 308 ) for supplying data from an external data bus (Din_Bus) to a data connection (D_) on each of the sense amplifier blocks ( 301 ) in response to a write activation signal (WE);
• - A plurality of sixth switching units ( 309 ) for forwarding data on the data connections (D_) of the sense amplifier blocks ( 301 ) in response to a hold activation signal (LE);
• - a plurality of buffer units ( 310 ) for buffering or temporarily storing the data from the sixth switching units ( 309 );
• - a plurality of seventh switching units ( 311 ) for returning the data stored in the buffer units ( 310 ) to the buffer units ( 310 ) and for storing this data in the buffer units ( 310 ) in response to the hold activation signal (LE); and
• - A plurality of eighth switching units ( 312 ) for the final forwarding of the data stored by the seventh switching units ( 311 ) and the buffer units ( 310 ) to an external data bus (Dout bus) in response to an output activation signal (OE).

8. Ferroelectric memory according to claim 1, characterized in that the input / output bus control ( 26 ) contains the following:

• - A plurality of fifth switching units ( 308 ) for forwarding data from an external data bus (Din_Bus) and from an inverted data bus (DB! n bus) each to a data connection (D_) and an inverted data connection (DB_) on each of the sense amplifier blocks ( 301 ) in response to a write enable signal (WE);
• - A plurality of sixth switching units ( 309 ) for forwarding data from the data connections (D_) and the inverted data connections (DB_) on the sense amplifier blocks ( 301 ) in response to a hold activation signal (LE);
• - a plurality of buffer units ( 310 ) for buffering or temporarily storing the data from the sixth switching units ( 309 );
• - a plurality of seventh switching units ( 311 ) for returning the data stored in the buffer units ( 310 ) back to the buffer units ( 310 ) and for storing them again in response to the hold activation signal (LE); and
• - A plurality of eighth switching units ( 312 ) for the final forwarding of the data stored by the seventh switching units ( 311 ) and the buffer units ( 310 ) to an external data bus (Dout bus) and an external inverted data bus (DBout_Bus) in response to an output activation signal (OE).

9. Ferroelectric memory according to claim 1, characterized in that the input / output bus control ( 26 ) contains the following:

• - a plurality of ninth switching units ( 313 ) for supplying data from an external data bus (Din_Bus) to a data connection (D_) of the sense amplifier block ( 301 ) in response to a write activation signal (WE); and
• - A plurality of tenth switching units ( 314 ) for the final forwarding of the data from the data connection (D_) of each of the sensor amplifier blocks ( 301 ) to an external data bus (Dout_Bus) in response to an output activation signal (OE).

10. Ferroelectric memory according to claim 1, characterized in that the input / output bus control ( 26 ) contains the following:

• - a plurality of ninth switching units ( 313 ) for relaying data from an external data bus and an external inverted data bus to a data terminal and an inverted data terminal on each of the sense amplifier blocks ( 301 ) in response to a write enable signal (WE); and
• - A plurality of tenth switching units ( 314 ) for the final forwarding of the data from the data connection (D_) and from the inverted data connection (DB_) of each of the sense amplifier blocks ( 301 ) to an external data bus (Dout_Bus) and to an external inverted data bus (DBout_Bus) in response to an output enable signal (OE).

11. Ferroelectric memory according to claim 1, characterized in that that in the event that the cell array has a number of "m" cell array blocks, of which each has a number of "n" sense amplifier blocks, each for input / output of Data are used, "n" data lines are provided such that one of each of these data lines for data transmission with one belonging to each cell array block Sense amplifier block is connected, which has the same number. 12. Ferroelectric memory according to claim 11, characterized in that the Data lines a number of "n" exclusive input data lines and a number of "n" have exclusive output data lines. 13. Ferroelectric memory according to claim 11, characterized in that  that the data lines have a number of "n" input / output data lines and a number of "n" inverted input / output data lines. 14. Ferroelectric memory according to claim 11, characterized in that the Data lines a number of "n" exclusive input data lines and a number of "n" have exclusive output data lines and a number of "n" exclusive inverted Input data lines and a number of "n" exclusive inverted output data lines have. 15. Ferroelectric memory according to claim 1, characterized in that when the data from the sense amplifiers have been loaded onto each of the data buses after completion of the sense amplifier operation, the input / output bus controller ( 26 ) continues to hold the data even if the sense amplifiers are deactivated in response to a hold activation signal (LE). 16. Ferroelectric memory according to claim 1, characterized in that the input / output bus control ( 26 ) column address signals (Y_T_0; Y_T_1; Y_T_2 and Y_T_3) are activated one after the other, namely after extending an activation period of the sense amplifier in read mode. 17. Ferroelectric memory according to claim 16, characterized in that the output hold signal remains activated while the line signal is fixed. 18. Ferroelectric memory according to claim 1, characterized in that when the input / output bus control ( 26 ) column address signals (Y_T_0; Y_T_1; Y_T_2 and Y_T_3) are activated in succession after an activation period of the sense amplifier has been extended in the read mode, the input / Output bus control ( 26 ) activates the column address signals only for a period of time sufficient to store data in core buffer hold buffers until subsequent data is available.