DE19928570A1 - Semiconductor device, especially a multilayer circuit structure, production process - Google Patents

Abstract

A semiconductor device production process comprises spin etching by applying an etching composition to a rotating semiconductor substrate to leave a via interconnection or to planarize an interlayer dielectric. A semiconductor device production process comprises forming contact vias in an insulating layer on a semiconductor substrate, forming a conductive layer over the insulating layer to bury the vias and etching the conductive layer by rotating the substrate and applying an etching mixture of an oxidizing agent (selected from H2O2, O2, IO4<->, BrO3, ClO3, S2O8<->, KIO3, H5IO6, KOH and HNO3), a promoter (selected from HF, NH4OH, H3PO4, H2SO4, NH4F and HCl) and a buffer solution to leave the conductive layer only within the vias. Independent claims are also included for the following: (i) a semiconductor device production process comprising forming a pattern structure on a semiconductor substrate, forming an interlayer dielectric over the substrate and the structure and planarizing the interlayer dielectric by rotating the substrate and applying the etching mixture described above; (ii) a semiconductor device production process comprising forming contact vias in an insulating layer on a semiconductor substrate, forming a cover layer over the insulating layer to bury the vias, rotating the substrate, heating the substrate by back face supply of hot gas and etching the cover layer by application of an etching composition to leave the cover layer material only within the vias; and (iii) a semiconductor substrate having a core region, with a conductive connection, and a peripheral region with a conductive material-free hole pattern for use as an alignment marking or a scoring frame.

Description

Background of the Invention

The present invention relates to semiconductor manufacturing processes devices.  In particular, the present invention relates to a method for manufacturing semiconductor devices to form a formation of conductive additives lines or joints using tungsten, copper, polysilicon and the like  to provide and the step height of dielectric interlayers by etching thin films on semiconductor substrates using specific etching Minimize compositions and spin-etch processes.  The present inven tion also relates to an etching composition for the production of semi-lead devices, and semiconductor devices made by these methods were.

Recently there has been an increased demand for formation technologies fine pattern for semiconductor devices and the use of multiple ge layered circuit structures for semiconductor devices insofar as they are highly inked be griert. In other words, the surface structures of the semiconductors directions more and more complicated, to the point where the step height between the layers malfunctions in the semiconductor manufacturing processes can cause directions.

In a photolithography process from various manufacturing processes a photoresist pattern on the semiconductor substrate by coating of a wafer with a photoresist. A mask with circuit-forming  Elements are aligned on the wafer and an exposure process is performed leads by exposing photoresist on the wafer with light or irradiating it.

Semiconductor devices with relatively large critical dimensions or dimensions NEN, that is, the smallest dimension that can be manufactured, and a deep stored structure can cause some problems. However, it is with the finer ones Structures or patterns of the currently used on the semiconductor substrates, multi-layered structures difficult, exactly between the top or Position and the lower point of the step height between the layers in the exposure focus process. Hence an exact pattern formation difficult to achieve.

This is why flat machining processes are used to minimize the step height between the layers more important. Different flat machining processes, at for example silicon-on-glass (SOG) layer deposition, from-behind etching or Reflux or the like is used to overcome the above problems, however Such methods have other problems associated with them. Another Process for planarization or flat machining is a chemical-mechanical butt lier (CMP) process.

The CMP process was developed as a flat machining process, wel ches works over the entire surface of the wafer. If the CMP procedure is based on a Manufacturing process for semiconductor devices is used, the ablation or Removal rate or the uniformity of the planarization of the flat machining important CMP parameters.

In the case where a silicon dioxide (SiO ₂ ) layer is leveled using an oxide layer CMP process, the property of the silicon dioxide (SiO ₂ ) is converted into a hydrophilic object with respect to H ₂ O Modified by casualness through a reaction with alkaline sludge. Water that penetrates into silicon dioxide (SiO ₂ ) functions to separate the connecting chain of silicon dioxide (SiO ₂ ). The silicon dioxide (SiO ₂ ) is then removed from a physical mechanism through the use of an abrasive.

In the case where a metallic layer using a CMP The process is leveled or machined flat, however, produces the chemical reactions on the surface of the metal layer by an oxidizing agent inside the Sludge a metallic oxide layer. This metallic oxide layer is covered by the mechanical (physical) friction of the abrasive with the top layer of the uneven pattern removed.

FIG. 1 is a schematic diagram showing the conventional CMP device for manufacturing semiconductor devices.

Referring to FIG. 1, the CMP device includes a polishing head 102 , a polishing table 104, and a polishing pad 108 . The CMP process is performed on the polishing table 104 . The polishing pad 108 is formed on the polishing table 104 and holds a semiconductor substrate 100 . A slurry is then fed from a slurry feed line 106 to polish the semiconductor substrate 100 . The polishing head 102 secures the semiconductor substrate 100 on the polishing pad 108 and can be moved in one direction of rotation.

The polishing pad 108 comes into contact with the semiconductor substrate 100 in the CMP method. The semiconductor substrate 100 is rotated by the polishing head 102 and the slurry is fed onto the polishing pad 108 . The slurry and the surface of the semiconductor substrate 100 react with each other, causing the semiconductor substrate 100 to be polished by the polishing printing plate 108 .

Fig. 2 to 7 are cross-sectional views showing a manufacturing method of the semiconductor device and the conventional procedures for forming a tungsten compound points describes, specifically including dung a CMP method under USAGE. The methods of forming both a tungsten junction portion and an alignment mark are shown simultaneously.

The semiconductor device shown in Figs. 2 to 7 is divided into a core portion (C), which is formed from components of an electrical circuit, and a peripheral portion (P), which is composed of components of the alignment marks, writing lines or scoring frame and the like. Is formed.

As shown in FIG. 2, oxide layer 114 is formed as a dielectric layer on semiconductor substrate 110 and has a plurality of local patterns 112 that are spaced apart. Local patterns 112 may each include a polysilicon or metal pattern as a conductive layer. Oxide layer 114 is a silicon dioxide (SiO ₂ ) layer formed by a conventional chemical vapor deposition (CVD) process, although a phosphosilicate ( PSG) layer or a borophosphosilicate (BPSG) layer can also be used as a dielectric layer between the polysilicon pattern layers or between the metal layers. At this time, the oxide layer 114 is formed on both the cell and core as well as the peripheral portions.

As shown in FIG. 3, the oxide layer 114 , which is initially uneven due to the presence of the local pattern 112, is planarized using the CMP device shown in FIG. 1 and described above.

As shown in FIG. 4, contact holes 116 are formed via a typical photolithography or etching process by covering the oxide layer 114 with a photoresist, forming a photoresist, and then using the oxide layer 114 of the photoresist pattern is etched as an etching mask. At this time, an edge hole 118 , which is used as an alignment mark or a scribe frame, is formed in the oxide layer 114 in the edge region (P) with a diameter larger than that of the contact holes 116 .

As shown in FIG. 5, a dual titanium / titanium nitride (Ti / TiN) is formed over the entire surface of the oxide layer 114 as a barrier layer 120 before a tungsten layer is formed. The dual Ti / TiN barrier layer 120 contains a Ti layer 120 a and a TiN layer 120 b. The Ti layer 120 a is formed using a conventional sputtering process or a CVD process, the TiN layer 120 b being formed using a typical sputtering process. The barrier layer 120 reduces the contact resistance of the tungsten layer and improves the adhesion of the oxide layer 114 and the tungsten layer. In addition, the barrier layer 120 is used as a stopper layer during a later method of removing the tungsten layer. At this time, the barrier layer 120 is formed both over and into the contact holes 116 and the edge hole 118 .

As shown in FIG. 6, a tungsten layer 122 is formed over the entire oxide layer 114 with a thickness which is sufficient to dig in the contact holes 116 and at least partially fill the edge hole 118 . The edge hole 118 has a larger diameter than that of the contact holes 116 of the core part, however, the edge hole 118 of the edge section is not completely filled with the tungsten layer 122 , but its bottom and side walls are covered.

As shown in Fig. 7, the semiconductor substrate 110 is attached with having formed thereon th tungsten layer 122 on the polishing or grinding head 102 of the CMP apparatus of FIG. 1 and the polishing pad 108 contacts the tungsten layer 122 currency rend of the metal layer slurry from the Sludge feed line 106 is fed. The polishing head 102 is then rotated to remove the top portion of the tungsten layer 122 on the barrier layer 120 so that the bottom portion of the tungsten layer 123 remains within the contact hole 116 . At this time, however, the lower portion of the tungsten layer 123 also remains on the bottom and side walls of the edge hole 118 . The remaining tungsten layer 123 in the marginal hole 118 (i.e., the alignment mark or the scribe frame) can later cause particle formation in a subsequent photolithography process, thereby weakening the alignment ability of the photolithography process.

The manufacturing process for the tungsten junction should typically be after the flat processing or the flattening of the dielectric intermediate layer layer (ILD). If the CMP process to flat machining or is added to the flattening for the surface of the semiconductor wafer, ver The CMP process thus reduces the productivity of the production and increases it Spending semiconductor device cost due to the short period of time required for the exchange of the polishing head and the sludge is allowed.

In addition, the respective post-drying process, which during the Formation of the tungsten junction is used, the contact resistance and the poor electrical properties of the transistor because of the associated with it the electrical charge of the plasma.

Therefore, there was a need to develop a process to which wel ches solves the problems described above. For this reason, a procedure will be provided, which solves the problems mentioned above and the efficiency and produc vity of semiconductor device manufacturing improved.

These tasks are with the features of claims 1, 14, 22 or 29 ge solves.

The present invention provides a method of manufacturing semiconductors directions ready, which refer to the conductive layers or the dielek tric intermediate layers on the semiconductor substrate using the rotary  Etching process by etching an etching composition onto a rotating one Semiconductor substrate is supplied.

Another object of the present invention is to provide a method for manufacturing Provide semiconductor devices by the electrical intermediate layer layers are leveled or machined and conductive connection points to be formed without microscratches on the surface of the semiconductor substrate to avoid an unnecessary increase in contact resistance.

Another object of the present invention is to provide an etching To provide assembly to the conductive layers or the dielectric Interlayer layers to be etched using the rotary etching process.

According to the present invention, there is provided a method of manufacturing semiconductor devices which includes forming an insulating layer over a semiconductor substrate, forming contact holes in the insulating layer, forming a conductive layer over the insulating layer to bury the contact holes Rotating the semiconductor substrate and the etching of the line layer comprises, by applying an etching composition to the rotating semiconductor substrate. The etching composition preferably has a mixture of at least one oxidizing agent which is selected from the group consisting of H ₂ O ₂ , O ₂ , IO ₄ ⁻, BrO ₃ , ClO ₃ , S ₂ O ₈ ⁻, KIO ₃ , H ₅ IO ₆ , KOH, HNO ₃ , and at least one performance enhancer or improvement agent or reinforcing agent, which is selected from the group consisting of HF, NH ₄ OH, H ₃ PO ₄ , H ₂ SO ₄ , NH ₄ F and HCl and a buffer solution. The oxidizing agent, the improving agent and the buffer solution preferably have a mixing ratio such that, after the etching, the material of the conductive layer is only present within the contact hole and is not present over the insulating layer.

The buffer solution can contain deionized water. The conductive layer can have a material selected from the group consisting of tungsten (W), copper (Cu) and polysilicon.

The method may further include forming a barrier metal layer over the semiconductor substrate and the insulating layer after the contact holes in the insulating layer are formed, but before the conductive layer is formed becomes. The barrier metal layer can have a material which is selected from the group of Ti, TiN, Ti / TiN, Ta, TaN and Ta / TaN is selected.

The rotation speed of the semiconductor substrate is preferably between 200 up to 5000 revolutions per minute. The etching composition is preferably with a rate or ratio of 0.1 to 2.5 l / min supplied.

The etching composition is through a nozzle, which is above the semiconductor substrate is placed, supplied, the nozzle being a longitudinal beam or boom swing either right to the center or left to the center of the semiconductor substrate carries out. The boom swing preferably varies from 80 mm to the left of that Center of the semiconductor substrate and 80 mm to the right of the center of the semiconductor substrate. The boom swing can be a long swing boom section punch or with a long distance and a boom swing section for short Have distances with a short distance, which are carried out one after the other.

The process temperature is in the range of 20 to 90 ° Celsius and that Semiconductor substrate is preferably up to approximately the process temperature of the etching Heated composition.

In particular, the etching composition may have 0.01 to 30 percent by weight of HNO ₃ as an oxidizing agent, 0.01 to 30 percent by weight of NH ₄ F as an improver and the remaining percent by weight of deionized water. The etching composition may also be 3 to 55 percent by weight of HNO ₃ as an oxidizing agent, 0.2 to 35 percent by weight of HF as an enhancing agent, and a remaining percent by weight of deionized water. The etching composition may also be 0.2 to 30 percent by weight of H ₂ O ₂ as the oxidizing agent, 0.01 to 30 percent by weight of NH ₄ OH as the enhancer, and remaining percent by weight of deionized water. The etching composition may also be 3 to 60 percent by weight of HNO ₃ as an oxidizing agent, 0.06 to 30 percent by weight of HF as an enhancing agent and a remaining percent by weight of deionized water.

A method of manufacturing semiconductor devices is also provided which comprises the steps of: forming an insulating layer over a semi-lead ter substrate, forming contact holes in the insulating layer, forming the conductive Layer over the insulating layer to bury the contact holes, Rotating the semiconductor substrate, performing a first etch in which on the rotating Semiconductor substrate placed a first etching composition at a first etching rate to the conductive layer by a thickness of between 40 to 95% of a total etch away the thickness of the conductive layer; and performing a second etch by the rotating semiconductor substrate has a second etching composition with a second Etching rate is applied, which is smaller than the first etching rate by the remaining To etch off part of the conductive layer, after the second etching the line layer only remains within the contact hole.

There is further provided a method of manufacturing semiconductor devices comprising the steps of: forming a pattern structure over a semiconductor substrate, forming a dielectric interlayer over the semiconductor substrate and the pattern structure, rotating the semiconductor substrate, and etching the dielectric interlayer by the rotating semiconductor substrate is applied with an etching composition which has a mixture of at least one oxidizing agent which is selected from the group consisting of H ₂ O ₂ , O ₂ , IO ₄ ⁻, BrO ₃ , ClO ₃ , S ₂ O ₈ ⁻, KIO ₃ , H ₅ IO ₆ , KOH and HNO ₃ , at least one improver, which is selected from the group consisting of HF, NH ₄ OH, H ₃ PO ₄ , H ₂ SO ₄ , NH ₄ F and HCl and a buffer solution, wherein the oxidizing agent, the improving agent and the buffer solution are mixed in a certain mixing ratio, so that the etching makes the dielectric interlayer flat or flat.

The dielectric interlayer may have a material made of was selected from the group consisting of an oxide, nitrite, borophosphosilicate and tetraethyl orthosilicate.

An etching composition for the production of semiconductor devices is also provided which has at least one oxidizing agent which has been selected from the group consisting of H ₂ O ₂ , O ₂ , IO ₄ ⁻, BrO ₃ , ClO ₃ , S ₂ O ₈ ⁻ , KIO ₃ , H ₅ IO ₆ , KOH, and HNO ₃ and at least one improver selected from the group consisting of HF, NH ₄ OH, H ₃ PO ₄ , H ₂ SO ₄ , NH ₄ F, and HCl and a buffer solution.

The etching composition can be applied to a rotating semiconductor substrate in this way be placed around a special thin layer which is laid out on the semiconductor substrate forms is to etch. The special thin layer can have a material which is selected from the group consisting of tungsten (W), copper (Cu), poly silicon, an oxide, a nitrite, borophosphosilicate or tetraethylorthosilicate.

A semiconductor substrate is also created which covers a cell area or Has core area, which contains a conductive junction, which from egg nem conductive material, and has an edge region which a Lochmu ster for use either as an alignment mark or scratch frame where the hole pattern does not have any of the conductive materials.

Brief description of the drawings

In the attached drawings is or are  

Fig. 1 is a schematic diagram showing a conventional CMP apparatus for the production of semiconductor devices;

Fig. 2 to 7 are cross-sectional views showing a manufacturing method of semiconducting tervorrichtungen using conventional process flows for forming a tungsten junction and an alignment mark or a scribe line;

Fig. 8 is a graph showing the etching rate tendency of an etching composition for a tungsten layer versus the weight percent ratio;

Figure 9 is a schematic diagram etch rotation device is one which is used to perform the manufacturing method of the semiconductor device according to a first preferred embodiment of the present invention.

Fig. 10 is a graph showing the etching rate according to the boom swing according to a first embodiment of the present invention;

Figure 11 is a graph showing the rate and etch uniformity for different boom swings according to a first embodiment of the front lying invention.

Figure 12 to 17 are cross sectional views showing the procedures, wel be used che, and writes be a formation method of a tungsten compound body according to a first preferred embodiment of the present invention.

FIG. 18 is a drawing showing a multilayer structure, which was TO USE A method of manufacturing the semiconductor device according to a first embodiment of the present invention generates;

Fig. 19 to 23 are cross-sectional views showing the formation procedure for Kernausführ- Kernlötstellen with the polysilicon junction using a method for the production of semiconductor devices according to a second preferred embodiment of the present invention; and

Fig. 24 to 28 are cross sectional views showing a flat processing method using a process for producing semiconductor devices according to a third embodiment of the present invention.

Detailed description of a preferred embodiment

The present invention will hereinafter be described with reference to the accompanying associated drawings are fully described, in which preferred embodiment tion forms of the present invention. This invention can ever yet be embedded in many different forms and should not be considered as one restrictive to the embodiment as they are laid out below. Rather, embodiments are provided so that their disclosure is complementary will be complete and within the scope of the invention to those working in the field.

According to the invention, a new rotary etching method or a chemical ver strengthened or supported polishing (CEP) process for etching a certain thickness a layer of a material, for example copper, tungsten, polysilicon, silicon moxide, silicon nitride or the like. Used. This CEP process is by feeding a chemical solution on the surface of a semiconductor wafer, wuh rend the semiconductor wafer rotates.

The CEP process is also used to manufacture semiconductor devices used, which a conductive line or connection point (e.g. those made of copper  fer, tungsten or polysilicon is formed) by adding a chemical solution the surface of the semiconductor wafer is placed and the semiconductor wafer rotates.

A managerial line generally acts as an interconnection line device for transmitting or translating internal signals of the semiconductor device to the outside of the semiconductor device. A lead liaison translates generally the electrical signals from a lower interconnect to an upper interconnection line.

The CEP process is used to make a flat or flat to produce uniform surface of the semiconductor wafer so that the processes of the subsequent process steps for producing the semiconductor devices easily simplify.

In the CEP process, a dielectric material, which over the upper Surface of the semiconductor wafer is formed, for example silicon oxide or silicon leveled or flattened nitrite by one step above the surface of the To minimize semiconductor wafers before it to the subsequent lithographic ver driving is moved. The dielectric material used in this process is typically either a dielectric interlayer or an intermediate location dielectric (ILD) or a dielectric intermediate metal or an intermediate metal dielectric (IMD).

According to a preferred embodiment of the present invention, the etching solution or etching composition has an oxidizing agent, a reinforcing agent and a buffer solution. The oxidizing agent preferably contains at least one material which is selected from the group consisting of H ₂ O ₂ , O ₂ , IO ₄ ⁻, BrO ₃ , ClO ₃ , S ₂ O ₈ ⁻, KIO ₃ , H ₅ IO ₆ , KOH , and ENT ₃ exists. The reinforcing agent preferably contains at least one material selected from the groups consisting of HF, NH ₄ OH, H ₃ PO ₄ , H ₂ SO ₄ , NH ₄ F, and HCl. The buffer solution is used to control the concentration, temperature and contact angle of the etching composition and preferably contains deionized water.

A preferred etching composition preferably contains 0.01 to 60 weight percent HNO ₃ as an oxidizing agent, 0.05 to 35 weight percent HF as a reinforcing agent and deionized water in the remaining percent as a buffer solution. This etching composition, which contains a mixture of HNO ₃ , HF and deionized water, can be used to etch the conductive layers, for example copper, tungsten, and polysilicon etc. or the dielectric layers, i.e. silicon oxide, silicon nitride layer etc. .

Another preferred etching composition contains 0.2 to 30 percent by weight H ₂ O ₂ as an oxidizing agent, 0.01 to 30 percent by weight NH ₄ OH as an enhancer and deionized water in the remaining percentages as a buffer solution. This etching composition, which contains a mixture of HNO ₃ , NH ₄ F and deionized water, can be used to etch the conductive or dielectric layers and also the barrier layers, i.e. Ti, Ta, Ti / TiN, Ta / TaN etc. be used.

Another preferred etching composition contains 0.1 to 30 percent by weight HNO ₃ as an oxidizing agent, 0.01 to 30 percent by weight NH ₄ F as a reinforcing agent and deionized water for the remaining percent as a buffer solution. This etching composition, which has a mixture of HNO ₃ , NH ₄ F and deionized water, can be used to etch the conductive or dielectric layers and also the barrier layers.

Fig. 8 is a graph showing the etch rates tendency of the etch composition for a tungsten film according to the percentages by weight of the oxidizing agent which is used in the etch composition or development.

As shown in Fig. 8, line A describes the etch rate tendency of a composition containing a mixture of HNO ₃ as an oxidizing agent, HF as an enhancing agent and deionized water as a buffer solution. Line A shows that in this case the increase in the etch rate is proportional to the amount, i.e. weight percent, of the HNO ₃ component in the entire etch composition. Li never B describes the etch rate tendency of a composition containing a mixture of H ₂ O ₂ as an oxidizing agent, NH ₄ OH as a reinforcing agent and deionized water as the buffer solution. Line B shows that the decrease in the etch rate is proportional to the amount, i.e. weight percent, of the H ₂ O ₂ component in the entire etch composition.

Fig. 9 is a schematic diagram etch rotation device is one which is used and carries out the manufacturing process of a semiconductor device according to the preferred embodiment of the present invention.

As shown in FIG. 9, a rotary etch device 200 includes a motor 211 , a rotary chuck 212 , a cup 213 , a plurality of nozzles 214 , a bracket 215 , a heater 216 , a drain pipe 217 , a regulator 218 and an N ₂ gas supply 219 . The spin chuck 212 is positioned below the semiconductor substrate 210 with the nozzle 214 placed over the semiconductor device to provide an etch composition. The nozzles 214 can preferably be moved to the left or to the right by the rotary chuck 212 and deliver the etching composition to the semiconductor substrate 210 . One of the nozzles 214 can preferably be used for a cleaning solution, for example deionized water.

The shell 213 is provided to cover the rotary jig 212 and to prevent the etching composition from flowing out during the process. The N ₂ gas supplied via the N ₂ gas line is supplied to the rotary jig 212 to raise the semiconductor substrate 210 by approximately 2 mm. The N ₂ gas is suitable for treating, in particular, the back of the semiconductor substrate 212 .

The preferred rotary etch device shown in FIG. 9 uses heater 216 to control the temperature of the N ₂ gas. In addition, the device may also include another heater (not shown) to control the temperature of the etch composition.

Although N ₂ gas is used to heat the semiconductor substrate 210 in the first preferred embodiment, other gases may also be used. However, it is advantageous that the gases used are an inert gas so that the gas itself does not interfere with the etching process.

The temperature of the etching composition is preferably in the range of 20 to 90 ° Celsius. In particular, the temperature of the etching composition is in the range from 30 to 70 ° Celsius in order to accelerate the etching rate of the material layer on the semiconductor substrate. The preferred temperature of the N ₂ gas is also in the range from 30 to 70 ° Celsius in order to heat the semiconductor substrate 210 on the rotary clamping device 212 . If the semiconductor substrate 210 is not heated while the etch composition is being heated, the temperature difference between the semiconductor substrate 210 and the etch composition causes a different etch rate over the entire material layer (e.g. copper, tungsten, and polysilicon, Silicon oxide, silicon nitrite, etc.). This in turn can result in an uneven surface of the semiconductor substrate 210 after the etching process.

In one operation, the temperature of the etch composition varies, that is, it cools down as soon as it is fed from the nozzle 214 onto the semiconductor substrate 210 and sprayed over the surface of the semiconductor substrate 210 . As the temperature of the etch composition changes as it flows, it varies anywhere on the surface of the semiconductor substrate 210 . In other words, the temperature of the etching composition that is placed on the semiconductor substrate 210 varies across all of the contact points on the surface of the semiconductor substrate 210 .

As a result of these temperature differences, a section on the semiconductor substrate 210 on which the etching composition was first contacted has a higher etching rate than a section on the semiconductor substrate 210 which later contacts or contacts the etching composition becomes.

The etch rate also varies according to the flow of the etch composition over the entire surface of the semiconductor substrate, which results in the uneven surface of the semiconductor substrate 210 . These etch variations are a critical point for large diameter semiconductor wafers such as a 300 mm diameter wafer. This is because the larger the wafer, the greater the temperature differences of the etching composition over the surface of the semiconductor wafer.

For this reason, the principle of the present invention teaches different methods for providing uniform process states, for example the supply of a heated N ₂ gas to the substrate, the presence of a heating device below the rotary clamping device 212 , a method for accommodating or sealing a rotary etching -Process chamber in a closed temperature-controlled process environment and the like.

The feed rate of the etching composition is preferably about 0.1 to 2.5 l / min, and the etching composition can be fed onto the semiconductor substrate 210 either to the right or to the left from the center, by a cantilever swing with different Extent or degree. The boom swing relates to the movement areas of the nozzles 214 over the semiconductor substrate 210 and the supply of the etching composition. For reference purposes, a boom swing to the left of the center of the semiconductor substrate 210 is negative (-) and a boom swing to the right of the center of the semiconductor substrate 210 is a positive (+). For the preferred embodiments described in this disclosure, the boom swing is given in units of millimeters (mm).

The range of motion of the boom swing of the present invention is preferably from 0 to +/- 80. In other words, the nozzle 214 preferably feeds the etch composition while moving up to 80 mm to the left or right side from the center of the semiconductor substrate 210 becomes. The boom swing for a given CEP process should be optimized because the boom swing is a parameter that affects the etch uniformity of the thin layers to be etched.

The boom swing should preferably be carried out with both a boom swing with a long distance and a boom swing with a short distance, which are carried out one after the other. A boom swing with a long distance is a boom swing in which the nozzle 214 is moved over a long distance, for example up to the maximum possible swing, which is made possible by the nozzle 214 . A boom swing with a short distance is a boom swing in which the nozzle 214 is moved over a shorter distance than with a large boom swing, for example a distance less than the maximum possible swing, which is made possible by the nozzle 214 .

Fig. 10 is a graph showing the etching rate corresponding to the swing from different locations in the substrate 210 . The graph shows the etch rate when etching a tungsten layer that uses an etch composition that has a mixture of HNO ₃ as an oxidizing agent, HF as a reinforcing agent, and deionized water as a buffer solution.

Line C shows the etching rate when the etching composition on the semiconductor substrate is supplied with the nozzle 214 , which is fixed to the center of the semiconductor substrate. In this situation, as line C shows, the etching rate at the central portion of the semiconductor substrate 210 is relatively higher than the etching rate at the peripheral edges of the semiconductor substrate 210 .

Line D shows the etching rate when the etching composition is fed onto the semiconductor substrate with the nozzle 214 , which performs a cantilever swing with a long distance. In this situation, as shown in line D, the etching rate at the peripheral edge of the semiconductor substrate 210 is relatively higher than the etching rate at the central portion of the semiconductor substrate 210 .

Line E shows the etching rate when the etching composition on the semiconductor substrate is fed with the nozzle 214 , which successively executes a boom swing with a long distance and a boom swing with a short distance. In this situation, as shown in line E, the etching rates are almost the same both at the peripheral edge and in the center of the semiconductor substrate.

Figure 11 is a graph showing the etch rates and etch uniformity over different boom swings. The graph shows the etch rate when a tungsten layer is etched using an etch composition comprising a mixture of HNO ₃ as an oxidizing agent, NH ₄ F as a reinforcing agent and deionized water as a buffer solution. In particular, the bar graphs show the etch rate and line F shows the etch uniformity.

The etch rate shown in the bar graph of Fig. 11 represents the thickness of a thin layer to be etched, which was etched by an etching solution for a certain time. The etch uniformity, which is shown in line F of Fig. 11, represents a deviation in thickness at a plurality of points of the thin layer, for example a middle point, an edge point and a middle point after the the etching is complete. The lower the value of the deviation between the points shown, the more uniform the resulting or resulting etching.

As shown in Fig. 11, when the boom swing with a long distance and the boom swing with a short distance are successively and continuously performed, the etching rate increases and the etching uniformity is improved. If the boom swing is -20∼0, the etch rate is approximately 540 Å / min which is sufficient for the process conditions. However, the uniformity is about 10%, which is too high. If the boom swing is -40∼0, the etch rate will drop to an unsuitable level and the uniformity will increase to a rather unacceptable amount.

However, when the boom swing is successively made to -40∼0 and -20∼0, the etch rate is approximately 540 Å / min and the etch uniformity is approximately 1%, both of which are acceptable for the process conditions. That is, line E in Fig. 10 can be obtained by combining the process conditions for line D and C. In accordance with the preferred embodiment of the present invention, the nozzle 214 which supplies the etch composition is allowed to linger longer and the etch composition is allowed to be fed for a longer period of time over the portion to be etched when there is a portion of a thin layer over the semiconductor substrate that requires greater etching.

The rotational speed of the rotary jig during the feeding of the The etching composition is preferably in the range of 200 to 5000 revs times per minute (rpm).

A method of manufacturing semiconductor devices using the Etching composition is subsequently used according to the preferred embodiments described, however, the invention should not be constructed or interpreted accordingly will be limited to these subsequent embodiments.  

First preferred embodiment

A first preferred embodiment of the method for producing Semiconductor devices for forming a conductive junction will now be wrote. This embodiment provides a new method for forming a lei tendency interconnection, without the surface microscratches, wel che caused by a CMP process, and without increasing the Kon clock resistance, which is caused by a dry etching-back process.

According to the present invention, a method of manufacturing semiconductor devices includes the steps of forming a dielectric layer over a semiconductor substrate, forming contact holes in the dielectric layer, forming a conductive layer over the electrical layer, and filling the contact holes, rotating the semiconductor substrate, and feeding the etching composition on the rotating semiconductor substrate. The etching composition preferably contains a mixture of at least one oxidizing agent, which is selected from the group consisting of H ₂ O ₂ , O ₂ , IO ₄ ⁻, BrO ₃ , ClO ₃ , S ₂ O ₈ ⁻, KIO ₃ , H ₅ IO ₆ , KOH and HNO ₃ , and at least one reinforcing agent selected from the group consisting of HF, NH ₄ OH, H ₃ PO ₄ , H ₂ SO ₄ , NH ₄ F and HCl and deionized water in a certain mixing ratio, so that after the etching, the material of the conductive layer only remains within the contact hole and does not remain over the dielectric layer.

The conductive layer is preferably a tungsten layer (W) or a copper layer (Cu). The conductive junction preferably connects an upper conductive Layer and a lower conductive layer via contact holes, which in the dielectri layer are formed.

During the formation of the conductive junction, a semiconductor substrate 210 having a conductive layer formed thereover is preferably attached to a rotatable chuck 212 and rotated at a certain rate.

Then, while supplying an etch composition through a nozzle 214 placed over the semiconductor substrate 210 , the conductive layer on the semiconductor substrate 210 is etched so that the conductive layer remains only within the contact hole and not over the dielectric Layer remains.

In other words, the conductive layer is etched by an increased horizontal etching pulse due to the centrifugal force on the semiconductor substrate 210 by the rotation of the rotary jig 214 and by the etching composition which has a good reaction with the conductive layer.

The higher the rotational speed of the rotary clamping device 214 , the more the etching pulse increases in the horizontal direction. As a result, this method improves the etching speed of the conductive layer and the etching uniformity, and prevents the generation of unnecessary gaps that are formed on the surface of the conductive layer.

The supply of the etching composition on the semiconductor substrate is pre- preferably carried out in two steps. The first step involves feeding one first material, which has a first etching composition with a first etching rate having. The second step involves feeding a second material, which is a contains second etch composition at a second etch rate which is less than that first etch rate is.

Figs. 12 to 17 are elevational views showing the procedures of a tungsten splice fabrication method using the method for Her position of semiconductor devices according to the first preferred embodiment of the present invention. These drawings show the formation of the conductive junction, that is, a tungsten junction, and the formation of either an alignment mark or a scribe frame. In these drawings, a core portion (C) for the formation or production of the circuit pattern and a peripheral portion (P) or edge portion for forming the alignment mark or the scoring frame are shown.

Referring to FIG. 12, an oxide layer 224 is formed over the semiconductor substrate 220 , which has a plurality of local patterns 222 formed thereon at a certain distance from each other. Local patterns 222 are preferably either polysilicon patterns or metal patterns used as a lower conductive layer. The oxide layer 224 can be a silicon dioxide layer (SiO ₂ ), phosphosilicate (PSG) or borophosphosilicate (BPSG) or the like, which is preferably by a typical CVD method or a glass spin coating method (SOG; spin-on-glass method) ) be formed. The thickness of the oxide layer 224 is preferably about 4000 to 15000 Å.

Referring to Fig. 13, a photoresist (not shown) is covered over the oxide layer 224 and (not shown) patterned by a conventional photolithography process. A portion of the oxide layer 224 is then etched by a conventional etching process to form a contact hole 226 , and also a peripheral hole 228 which is used as an alignment mark or scribe frame. The circumferential hole 228 preferably has a larger diameter than that of the contact hole 226 .

Referring to FIG. 14, a barrier layer 230 , such as a dual TiA / TiN layer, is preferably formed in the contact hole 226 and in the peripheral hole 228 before a conductive material is applied. The barrier layer 230 preferably has a lower barrier layer 230 a, for example Ti, and an upper barrier layer 230 b, for example TiN. If the barrier layer 230 is formed in the contact hole 226 and the peripheral hole 228 , the thickness of the barrier layer 230 is preferably about 700 Å. The formation of the lower barrier layer 230 a and the upper barrier layer 230 b uses a typical sputtering or CVD process.

The barrier layer 230 is preferably used to lower the contact resistance of the electrode and to improve the adhesiveness between a conductive material and the oxide layer 224 . The barrier layer 230 can also be used as a stopper layer during the removal of the conductive material in the subsequent processes.

Referring to Figure 15, a first conductive layer 232 , e.g. B. a ste he tungsten layer formed over the surface of the semiconductor substrate 220, both in the contact hole 226 and the peripheral aperture 228th Because the circumferential hole 228 in the circumferential portion (P) has a larger diameter than that of the contact hole 226 in the core portion (C), the circumferential hole 228 is not completely filled with the first conductive layer 232 , but only the bottom and side walls thereof are covered .

Referring to FIG. 16, a semiconductor substrate 220 having the first semiconductor layer 232 is placed on the rotary jig 212 shown in FIG. 9. The first conductive layer 232 is then etched around a second conductive layer 232 , such as a second tungsten layer, by rotating the semiconductor layer 220 on the rotary chuck 212 and spraying the etch composition through a nozzle 214 over the semiconductor substrate 220 . and form the first conductive layer 232 . Preferably, the feed amount of the etching composition is about 0.1 to 2.5 l / min, and the etching composition preferably has about 3 to 55% by weight of HNO ₃ as an oxidizing agent, 0.2 to 35% by weight of HF as a reinforcing agent, and the others Percent of deionized water as a buffer solution. Preferably, the etching composition contains 10 to 45 weight percent HNO ₃ as an oxidizing agent, 1 to 24 weight percent HF as a reinforcing agent and the remaining percent of deionized water as a buffer solution. The process temperature is preferably in the range from approximately 20 to 90 ° Celsius, in particular in the range from 30 to 70 ° Celsius. The rotational speed of the rotary chuck 212 is preferably in the range of approximately 200 to 5000 rpm, preferably approximately 1000 to 3000 rpm.

Heated gas, preferably N ₂ gas, is supplied to the back of the semiconductor substrate 220 , preferably at a temperature of about 20 to 150 ° Celsius, to reduce the temperature difference between the etching composition and the semiconductor substrate 220 and thus the uniformity of the To improve etching process. The etching rate of the first conductive layer 232 is preferably in the range of 70 to 22,000 Å / min. The processing time varies depending on the thickness of the first conductive layer 232 and can be adjusted according to the processing conditions. The etched thickness of the first conductive layer 232 (that is, the thickness of the portion of the first conductive layer 232 that is etched away) is preferably about 40 to 95% of the thickness of the first conductive layer 232, and is preferably in the range of 70 to 90%.

Referring to Fig. 17 is then conductive tungsten layer 233 etched so ge to a conductive junction 235 by rotation of the semiconductor substrate 220 via the rotary jig 212, and by spraying the etching composition through a nozzle 214 on the semiconductor substrate 220 and to to form the second conductive layer 233 . Preferably, the feed rate for this process is about 0.1 to 2.5 l / min, and the etching composition preferably contains 0.2 to 30 weight percent H ₂ O ₂ as the oxidizing agent, 0.1 to 30 weight percent NH ₄ OH as the reinforcing agent and the remaining percent deionized water as a buffer solution. Preferably, the etching composition contains 1.0 to 30 percent by weight H ₂ O ₂ as O, 0.01 to 29 percent by weight NA ₄ OH as a reinforcing agent and the remaining percent of deionized water as a buffer solution.

A preferred alternative etching composition contains 0.01 to 30 weight percent HNO ₃ as an oxidizing agent, 0.01 to 3.0 weight percent NH ₄ F as a reinforcing agent and the remaining percent deionized water as a buffer solution.

The process temperature is preferably in the range from approximately 20 to 90 ° Celsius, in particular between 30 to 70 ° Celsius, the rotational speed of the rotary tensioning device 212 preferably being in the range from 200 to 5000 rpm. Heated gas, for example N ₂ gas, which preferably has a temperature of approximately 30 to 150 ° Celsius, is supplied from the rear of the semiconductor substrate 220 to reduce the temperature difference between the etching rate and the semiconductor substrate 220 , thereby reducing the uniformity the etching process is improved. The etch rate of the second conductive layer 233 is preferably in the range of about 30 to 12,000 Å / min. The processing time varies according to the thickness of the second conductive layer 233 and can be adjusted according to the process conditions.

In this CEP etching process, the second conductive layer 233 in the circumferential hole and the portion of the barrier layer 230 in the circumferential hole 228 are removed by the CEP process. Likewise, the portion of the barrier layer 230 over the top surface of the oxide layer 224 in the core portion is also removed by the CEP process. Because the peripheral aperture 228 is larger than the contact hole 226, which includes the conductive junction 235, the etching composition is in the order catch hole 228 inside to the second conductive layer 233 and 230 to remove the barrier layer from the peripheral aperture 228 is sufficient.

In an alternative, the removal of the second conductive layer 233 and the barrier layer 230 can be carried out in two successive stages, i.e. firstly removing the second conductive layer 233 and then removing the second barrier layer 230 .

As described above, the manufacturing process for the conductive junction is preferably divided into two steps. A first step with a high etch rate using a first etch composition, which preferably has a high etch rate, e.g. B. HF and HNO ₃ is used to etch 40 to 95% of the thickness of the first conductive layer 232 . Then a second step with a low etching rate using an etching composition, which preferably has a low etching rate, e.g. B. H ₂ O ₂ and NH ₄ OH or HNO ₃ and NH ₄ F, used so as to etch the remaining portion of the second conductive layer 233 on the barrier layer 230 . As a result of this method, a conductive interconnect 235 is formed so that the conductive material that has been applied as a first conductive layer remains only within the contact holes 226 .

In addition, to form the conductive junction 235, the removal of the first conductive layer 232 can be performed using the multiple steps.

The semiconductor device manufactured according to the invention contains a core area containing a conductive junction and an um capture area, which is a circumferential hole pattern, which is used as an alignment mark or a scoring frame is used. The circumferential hole pattern is preferred by the same method as the via pattern manufacturing method for made the conductive junction, with none of the conductive materials inside half of the circumferential hole pattern remains in the circumferential area.

In addition, the manufacture of semiconductor devices is also part of the invention Multiple structures, i.e. stacked structures, possible.

Fig. 18 is a drawing showing a multiple-structure, showing by an inventive method for manufacturing the semiconductor devices according to a first preferred embodiment. As shown in Fig. 18, a desired multiple structure containing three layers of structures F, S, and T is created by repeatedly executing the junction manufacturing process, a situation which is accomplished using a conventional CMP method is impossible. In this multiple structure, a second layer structure (S) is formed over a first layer structure (F) and a third layer structure (T) over the second layer structure (S). This multiple structure can be created effectively without performing a leveling process on the lower layers. Further, the multi-layer structure is not limited to this three-layer structure as shown in Fig. 18, but can be made with a different number of layers.

In summary, the above method can be used in the manufacture of conductive joints and the manufacture of conductive lines over a Semiconductor substrate with a multi-layer structure can also be used. As As a result of this method, the semiconductor device manufacturing process is united folds, which improves the productivity of the manufacturing process.

Second preferred embodiment

To the same extent as semiconductor devices are becoming more integrated the depth of the contact holes becomes deeper and the diameter of the contact holes become small ner. As a result, it has become more difficult to thin the contact holes To dig layers. Therefore, a solder joint should be made over the section where the vias are formed to reduce the depth of the vias and improve the profile of the contact holes.

Fig. 19 to 23 are cross-sectional views showing the procedure Kernlötstellenherstellungs with a polysilicon junction using a method for the production of semiconductor devices according shows a second embodiment of the present invention.

Referring to FIG. 19, a first dielectric layer 258 is formed over a plurality of gate electrodes 256 formed on the semiconductor substrate 250 . The gate electrodes 256 are spaced apart and surrounded by spacers 254 . A core on the semiconductor substrate 250 is divided into an active region and an inactive region by isolation trench regions 252 in order to isolate different elements on the substrate 250 . The first dielectric layer 258 insulates the core when the core is formed between the gate electrodes 256 . The first dielectric layer 258 is preferably a borophosphosilicate (BPSG) layer.

Referring to FIG. 20, the first dielectric layer 258 is preferably flattened by a CMP process to form a second dielectric layer 259 .

Referring to FIG. 21, contact holes 260 are then formed in the flattened second dielectric layer 259 . In this method, a photoresist (not shown) is covered over the flattened, second dielectric layer 259 ; a photoresist pattern is formed using a typical photolithography process and contact holes 260 are formed by an etching process using the photoresist pattern as an etching mask. The photoresist mask is then removed.

Referring to Fig. 22, a conductive layer 262, that is Polysili ziumschicht formed over the second dielectric layer 259 having a certain thickness out to bury the contact holes 260th

Referring to FIG. 23, the semiconductor substrate 250 , which reveals the conductive layer 262 formed thereon, is placed on the rotary jig 212 shown in FIG. 9. The conductive layer 262 is then etched by rotating the chuck 212 and spraying the etch composition through a nozzle 214 over the semiconductor substrate 250 to remove the portion of the conductive layer 262 over the second dielectric layer 259 , wherein only conductive junctions 263 , that is, polysilicon junctions formed in the contact holes ( 260 ) remain.

In this method, the supply amount of the etching composition is preferably between 0.1-2 l / min. The etching composition preferably has 3 to 60 percent by weight HNO ₃ as an oxidizing agent, 0.06 to 30 percent by weight HF as a reinforcing agent and the remaining percent deionized water as a buffer solution. In particular, the etching composition has 8 to 45 weight percent HNO ₃ as an oxidizing agent 0.3 to 12 weight percent HF as a reinforcing agent and the remaining weight percent deionized water as a buffering agent. The temperature of the etching composition is preferably in the range of 20 to 90 ° C. The rotational speed of the rotary chuck 212 is preferably in the range of 200 to 5000 rpm. The resulting etching rate of the conductive layer 262 is preferably in the range of 30 to 48,000 Å / min. The processing time varies depending on the thickness of the conductive layer 262 and can be adjusted according to the processing conditions.

The conductive junctions 263 made with this method are used as a core solder joint in the subsequent processes.

Third preferred embodiment

Just as semiconductor devices are integrated higher and multiple layers included, the step heights between the core section for the formation increases of the element pattern and the peripheral portion between the core portions. As As a result of this increased step height, it can be difficult to get a precise mu to get a degree because of the difficulties with an ex Focusing between the top and bottom of the Photoli thography. That is why flat machining processes are becoming increasingly important to the To minimize step heights.  

Figs. 24 to 28 are cross-sectional views showing a Flachbearbeitungsver drive using a method for the production of semiconductor devices according to a third preferred embodiment of the present invention. Fig. 24 shows a first step the height (H ₁₎ of a semiconductor device having a capaci tätselektrode 272, which is formed above or over a semiconductor substrate 270th The step height (H ₁ ) exists between the core section (C) for the element pattern and a peripheral section (P).

FIG. 25 is a cross sectional view showing that a first oxide layer 274, which is used as an interlayer dielectric layer, a semiconductor substrate over the half formed 270th Due to the first step height (H ₁ ), the first oxide layer 274 also has a second step height (H ₂ ) between the core section (C) and the peripheral section (P).

The first and second step heights (H ₁ and H ₂ ) can cause malfunctions in the subsequent processes, since the step heights (H ₁ and H ₂ ) make it difficult to precisely focus a photolithography process for producing an element pattern.

The first oxide layer 274 is preferably a BPSG layer, but it is not limited to this material. The first oxide layer 274 is preferably formed using the CVD process and in particular using a low-pressure gas phase deposition using chemical processes (LPCVD).

A uniform layer can be deposited or deposited by this method to be brought.

Fig. 26 is a cross sectional view showing that a second oxide layer 275 is machined flat-flow from a first oxide layer 274 is formed. To achieve this, an oxide layer 274 is flow-machined at a high temperature, preferably above 750 ° C, to minimize the second step height (H ₂ ). After the flow flat machining, the thickness (L ₂ ) of the second oxide layer 275 in the core portion (C) becomes smaller than a thickness (L) of the first oxide layer 274 . In other words, a third step height (H ₃ ) of the second oxide layer 275 is smaller than the second step height (H ₂ ) of the first oxide layer 274 . The first angle (θ ₁ ) for the formation of the third step height (H ₃ ) is thus small. However, the high temperature flow flat working method described above has limitations.

Fig. 27 is a cross-sectional view showing that a third oxide layer 276 can be formed by flat machining the second oxide layer 275 using a rotary etching method.

Using this method, a semiconductor substrate 270 with the flow-machined second oxide layer 275 is placed on the spin chuck 212 , as shown in FIG. 9. The second oxide layer 275 is then etched by rotating the semiconductor substrate 270 and the twist chuck 212 and spraying the etch composition through the nozzle 214 onto the semiconductor substrate 270 .

In this method, the etching composition preferably has a supply amount of 0.1 to 2.5 l / min. The etching composition preferably has 0.01 to 60 percent by weight of HNO ₃ as an oxidizing agent, 0.05 to 25 percent by weight of HF as a reinforcing agent, and the remaining deionized water as a buffer solution. In particular, the etching composition has 0.01 to 60 weight percent of HNO ₃ as an oxidizing agent, 0.5 to 12 weight percent of HF as a reinforcing agent, and the remaining 8% deionized water as a buffer solution. The process temperature is preferably in a range from 20 to 90 ° Celsius, in particular in the range from 30 to 70 ° Celsius, and the rotational speed of the rotary clamping device 212 is preferably in the range from approximately 200 to 5000 rpm.

The etch rate of the second oxide layer 275 is preferably in the range of approximately 30 to 52,000 Å / min. The processing time varies depending on the thickness of the second oxide layer 275 and can be adjusted according to the processing conditions.

By comparing the third oxide layer 276 , which is shown in FIG. 27 and which has been flattened or flattened by the rotary jig method, with the second oxide layer 275 of FIG. 26, the following relationships are effective. H ₃ <H ₄ , L ₂ <L ₄ , L ₁ <L ₃ and θ ₁ <θ ₂ . As a result, a fourth step height (H ₄ ) and the second angle θ _{2 are} both minimized by performing the flat machining by the rotary etching method.

The fourth step height (H ₄ ) can be further minimized and the angle θ ₂ can be made smaller if the rotational speed of the rotary jig is increased. However, the rotational speed has a limit, thereby limiting the increased range of the rotational speed due to the need for a sufficient reaction of the etching composition with the second oxide layer 275 . The thickness of the second oxide layer 275 removed from the spin etch is equal to the amount L ₂ -L ₄ .

Fig. 28 is a cross-sectional view showing that a resist pattern 278 is formed over the third oxide layer 276 , which is made flat by the spin-etch process. The photoresist pattern 278 is formed after applying a photoresist over the third oxide layer 276 and after performing a photolithographic process. By minimizing the step height (H ₁ ) between the top and bottom of the first oxide layer 274 , the depth of focus (DOF) can be improved in the subsequent photolithographic process.

Analysis of the effects of the present invention shows several improvements The manufacturing method for conductive junctions of the present invention dung, which has been discussed above, is characterized in that under Ver  using a rotary etching process is carried out by an etching Composition is put on, which has a good reaction with the conductive Has layers, and by rotating the semiconductor substrate rapidly, so through Increasing the etching pulse in the horizontal direction of the semiconductor substrate by means of the Etch centrifugal force due to the high rotation of the semiconductor substrate. This un differs from the conventional CMP process, in which a polishing device device in contact with a semiconductor substrate through the use of a be agreed pressure and the supply of a sludge is brought.

The present invention provides a conductive connection place that is of sufficient quality, even without the flat machining step of the dielectric interlayer during the manufacture of the conductive Junction, which improves the productivity of the manufacturing process becomes.

In addition, the conductive layer within the hole pattern in the circumference areas, such as an alignment mark and different uneven mu on the scoring frame, completely removed during the CEP process. This ver prevents the generation of particles in the later processes and the presence of microscratches on the semiconductor substrate due to the sludge, the result being nis of it, the alignability of the photolithographic process is improved.

According to the present invention, the etching properties can be easily changed be changed by adjusting the rotational speed of the semiconductor substrate, the Feed amount of the etching composition is varied, the spray pressure is changed and the boom swing of the nozzle is changed, etc.

Therefore, the present invention achieves semiconductor simplification directional manufacturing process, the increased reliability of semiconductor devices and a reduction in procedural costs.  

Additional benefits and modifications are available to those who are on the Area are understandable. Therefore, the invention in its entirety is not limited to the specific details and representative devices shown and described herein. Accordingly, different modifications can be made be made without the inventive concept of the general inventive con to leave zeptes as defi in the pending claims and their equivalents is nated.

A method of manufacturing semiconductor devices is provided that includes the formation of a conductive junction and minimizes the step height of a dielectric interlayer. An etching-together is also provided for such manufacturing processes. The method of manufacturing semiconductor devices includes the steps of forming an insulating layer over a semiconductor substrate, forming contact holes in the insulating layer, forming a conductive layer over the insulating layer to bury the contact holes, rotating the semiconductor substrate, and etching the conductive layer , in which an etching composition is applied to the rotating semiconductor substrate, and spin-etching the tungsten layer using an etching composition, for example such that the conductive layer only remains in the contact holes and does not remain above the insulating layer. The etching composition contains at least one oxidizing agent, which consists of H ₂ O ₂ , O ₂ , IO ₄ ⁻, BrO ₃ , ClO ₃ , S ₂ O ₈ ⁻, KIO ₃ , H ₅ IO ₆ , KOH and HNO ₃ , at least one Reinforcing agents which are selected from HF, NH ₄ OH, H ₃ PO ₄ , H ₂ SO ₄ , NH ₄ F and HCl and a buffer solution which are mixed with one another in certain amounts.

Claims (30)

1. A method for producing semiconductor devices, which comprises:
Forming an insulating layer over a semiconductor substrate;
Forming contact holes in the insulating layer;
Forming a conductive layer over the insulating layer to bury the vias;
Rotating the semiconductor substrate; and
Etching the conductive layer by applying an etching composition to the rotating semiconductor substrate,
wherein the etching composition has a mixture of at least one oxidizing agent which is selected from the group consisting of H ₂ O ₂ , O ₂ , IO ₄ ⁻, BrO ₃ , ClO ₃ , S ₂ O ₈ ⁻, KIO ₃ , H ₅ IO ₆ , KOH, HNO ₃ , at least one reinforcing agent which is selected from the group consisting of HF, NH ₄ OH, H ₃ PO ₄ , H ₂ SO ₄ , NH ₄ F, and HCl and a buffer solution, and
wherein the oxidizing agent, the reinforcing agent and the buffer solution have a mixing ratio such that, after the etching, the material of the conductive layer is only present within the contact hole and is not left over the insulating layer. 2. A method of manufacturing semiconductor devices according to claim 1, wherein the buffer solution contains deionized water. 3. A method of manufacturing semiconductor devices according to claim 1, wherein the conductive layer has a material which is selected from the group, which consists of tungsten (W), copper (Cu) and polysilicon. 4. A method for producing semiconductor devices according to claim 3, which the formation of a barrier metal layer over the semiconductor substrate and  of the insulating layer after the formation of the Contact holes in the insulating layer, however, before the formation of the conductive layer. 5. A method of manufacturing semiconductor devices according to claim 4, wherein the barrier metal layer has a material which is selected from the group of Ti, TiN, Ti / TiN, Ta, TaN and Ta / TaN is formed. 6. A method of manufacturing semiconductor devices according to claim 1, wherein the etching composition is fed via a nozzle which is above the Semiconductor substrate is positioned, the nozzle having a boom swing either to the right of the center or to the left of the center of the Executes semiconductor substrate. 7. A method of manufacturing semiconductor devices according to claim 1, wherein the process temperature of the etching composition in the range of 20 to 90 ° Celsius. 8. A method of manufacturing semiconductor devices according to claim 7, wherein the semiconductor substrate up to approximately the processing temperature of the etching Composition is heated. 9. The method of manufacturing semiconductor devices according to claim 3, wherein the etching composition comprises 0.01 to 30% by weight of HNO ₃ as an oxidizing agent, 0.01 to 30% by weight of NH ₄ F as a reinforcing agent, and a remaining% by weight of deionized water . 10. The method for manufacturing semiconductor devices according to claim 3, wherein the etching composition comprises 3 to 55% by weight of HNO ₃ as an oxidizing agent, 0.2 to 35% by weight of HF as a reinforcing agent and a remaining% by weight of deionized water. 11. The method for manufacturing semiconductor devices according to claim 3, wherein the etching composition comprises 0.2 to 30% by weight of H ₂ O ₂ as an oxidizing agent, 0.01 to 30% by weight of NH ₄ OH as a reinforcing agent and a remaining percentage by weight of deionized water . 12. The method of manufacturing semiconductor devices according to claim 3, wherein the etching composition comprises 3 to 60% by weight of HNO ₃ as an oxidizing agent, 0.06 to 30% by weight of HF as a reinforcing agent and a remaining% by weight of deionized water. 13. A method of manufacturing semiconductor devices according to claim 1, wherein the etching of the conductive layer is carried out by at least two etching methods becomes. 14. A method of manufacturing semiconductor devices, comprising the steps of:
Forming a pattern structure over a semiconductor substrate;
Forming a dielectric interlayer over the semiconductor substrate and the pattern structure;
Rotating the semiconductor substrate; and
Etching the dielectric interlayer, in which an etching composition, which is a mixture of at least one oxidizing agent, which is selected from the group consisting of H ₂ O ₂ , O ₂ , IO ₄ ⁻, BrO, is fed onto the rotating semiconductor substrate ₃ , ClO ₃ , S ₂ O ₈ ⁻, KIO ₃ , H ₅ IO ₆ , KOH, HNO ₃ , at least one reinforcing agent which is selected from the group consisting of HF, NH ₄ OH, H ₃ PO ₄ , H ₂ SO ₄ , NH ₄ F, and HCl and a buffer solution,
wherein the oxidizing agent, the reinforcing agent and the buffer solution are mixed in a certain mixing ratio so that the etching flattens the dielectric interlayer. 15. A method for producing semiconductor devices according to claim 14, wherein the interlayer dielectric layer comprises a material made of selected from the group consisting of an oxide, a nitrite, Borophosphosilicate and tetraethyl orthosilicate. 16. The method for manufacturing semiconductor devices according to claim 15, wherein the etching composition comprises 0.01 to 60 weight percent of HNO ₃ as an oxidizing agent, 0.05 to 25 weight percent of HF as a reinforcing agent and a remaining weight percent of deionized water. 17. A method of manufacturing semiconductor devices according to claim 15, wherein the etching composition comprises 0.01 to 30 weight percent of HNO ₃ as an oxidizing agent, 0.01 to 30 weight percent of NH ₄ F as a reinforcing agent, and the remaining weight percent comprises deionized water . 18. A method of manufacturing semiconductor devices according to claim 14, wherein the rotation speed of the semiconductor substrate between 20 to 5000 rotations per minute. 19. A method of manufacturing semiconductor devices according to claim 14, wherein the etching composition is fed via a nozzle which is above the Semiconductor substrate is positioned, the nozzle being a cantilever swing either to the right of the center or to the left of the center of the semiconductor substrate executes.   20. A method for producing semiconductor devices according to claim 19, the boom swing is a boom swing with a large distance and has a boom swing with a short distance, which one after the other be carried out. 21. A method of manufacturing semiconductor devices according to claim 14, wherein the semiconductor substrate up to approximately the processing temperature or Process temperature of the etching composition is heated. 22. A method for producing semiconductor devices, which comprises:
Forming an insulation layer over a semiconductor substrate;
Forming contact holes in the insulation layer;
Forming a cover layer over the insulating layer to bury the vias;
Rotating the semiconductor substrate;
Heating the semiconductor substrate by applying hot gas to the back of the semiconductor substrate; and
Etching the cover layer by placing an etch composition on the rotating semiconductor substrate, the material of the cover layer being only within the contact holes and not remaining over the insulating layer after the etching. 23. The method for producing semiconductor devices according to claim 22, wherein the etching composition is a mixture of at least one oxidizing agent which has been selected from the group consisting of H ₂ O ₂ , O ₂ , IO ₄ ⁻, BrO ₂ , ClO ₃ , S ₂ O ₈ ⁻, KIO ₃ , H ₅ IO ₆ , KOH, HNO ₃ , at least one reinforcing agent which is selected from the group consisting of HF, NH ₄ OH, H ₃ PO ₄ , H ₂ SO ₄ , NH ₄ F, and HCl and a buffer solution. 24. A method of manufacturing semiconductor devices according to claim 23, wherein the buffer solution contains deionized water. 25. A method of manufacturing semiconductor devices according to claim 22, wherein the cover layer is a conductive layer and a dielectric layer Intermediate layer has. 26. A method of manufacturing semiconductor devices according to claim 22, wherein the hot gas has an inner gas and the temperature of the hot gas in is in the range of 20 to 90 ° Celsius. 27. A method of manufacturing semiconductor devices according to claim 22, wherein the etching composition is fed via a nozzle which is above the Semiconductor substrate is positioned, the nozzle having a boom swing either to the right of the center or to the left of the center of the Executes semiconductor substrate. 28. A method of manufacturing semiconductor devices according to claim 22, wherein the process temperature of the etching composition in the range of 20 to 90 ° Celsius. 29. semiconductor substrate, which has
a core region including a conductive junction made of a conductive material; and
a peripheral portion containing a hole pattern for use with either an alignment mark or a scribe frame, the hole pattern having none of the conductive materials. 30. The semiconductor substrate according to claim 29, wherein the conductive material is a material which was selected from the group consisting of tungsten (W), There is copper (Cu) or polysilicon.