DE19943390A1 - Semiconductor component comprises vertical stack comprising source, drain and intermediate layer, gate comprising insulating and conducting layer connecting source and drain and tunnel current flowing in section of gate - Google Patents

Abstract

Semiconductor component in which a tunnel current can be controlled by a gate comprises an n-doped layer (2) which acts as source and a p-doped layer (3) which acts as drain with an intermediate layer (4) positioned between them to form a vertical stack. A gate made up of an insulating layer (5) and a conducting layer (6) forms a path for current to flow between the n- and p-doped layers, the tunnel current flowing in at least a section of the gate Independent claims are included for: (a) use of the component as a transistor; and (b) a method of preparing the component comprising: (i) applying the source, drain and gate to a silicon substrate (1); (ii) etching their vertical edges; (iii) applying an insulating layer to the edges; (iv) applying a conducting layer; and (v) forming contact holes and metallising to connect the source, drain and gate.

Description

As the transistor dimensions become smaller and smaller, more and more components can be accommodated on a semiconductor wafer, the wafer, in planar technology, which among other things leads to less expensive production. Because of their properties, MOSFETs ( FIG. 1) have so far been most suitable for this high integration; today, more than 85% of all semiconductor components manufactured are MOSFETs. The basic parameters of MOSFETs can be predicted for the future by extrapolation. However, there are still no technological implementation options in many areas, so that a possible scenario could be to achieve the technically feasible reduction.

So-called "tunnels" are the possible successors to MOSFETs. Viewed components. This would be an increase in Switching speed due to the utilization of the quantum mechanical tunneling is an advantage, but it will also be a possible increase in the functionality of quantum mechanical Components viewed as an advantage. Quantum effects can be only in extremely small geometries, typically atomic Realize orders of magnitude with nanometer dimensions. in the Solid such small structures can be realized by different materials with nanometer thickness and atomic sharp interfaces stacked up (heterostructures) (Examples see: S. Luryi, A. Zaslavsky: "Quantum-Effect and Hot- Electron Devices "in S.M. Sze (ed.):" Modern Semiconductor Device Physics ", Wiley, New York, 1998).

Although some variants of tunnel components in some Features have advantages over MOSFETs is one large-volume use for standard applications in digital and analog electronics have not yet taken place. For this, the  Silicon-based components exist in order to existing standard circuits can be integrated.

Well-known tunnel components are Esaki diodes, whose function is based on the abrupt contact of two highly doped p / n regions made of a semiconductor material, see e.g. BL Esaki: "New Phenomenon in Narrow Germanium pn Junctions", Phys. Rev. Lett. 109 ( 1958 ) p. 603, or SM Sze: "Physics of Semiconductor Devices", Wiley, New York, 2nd. ed., 1981, p. 516. Fig. 2 comes from the last-mentioned textbook.

In this geometry, electrons at the pn junction from Tunnel into the valence band and reverse. The tunnel process is so far immeasurably fast. Reverse polarity (p an Minus, n to plus) there is an exponential increase in the current on, in the forward direction an area with negative differential resistance (NDR = negative differential resistance) are bred. In silicon is for material reasons to achieve only a peak valley ratio of about 2. Tunnel diodes operated in this area of the characteristic are the fastest switches known to date and will be used passively to dampen oscillator circuits.

A controllable three-pole, a transistor, would be advantageous compared to the non-controllable two-pole diode. In J. Koga, A. Toriumi, Tech. Digest, IEDM'96, p. The attempt to manufacture such a component using planar technology on SIMOX wafers was also described in 265, and a slight NDR could also be switched. The disadvantages of this attempt are:

• a) Execution in planar technology is subject to the achievable dimensions the restrictions of Photolithography.
• b) The doping profiles become blurred. The endowments are made by Implants realized. Due to the characteristics of the Implantation process itself and the subsequent one  High temperature step to heal crystal damage occurs the dopants run on.
• c) Avoiding those occurring in the planar substrate Leakage currents require additional structures in the channel area that counteract a downsizing of the component, and additionally the use of expensive SOI substrates (SOI = silicon on insulator).

Because of these disadvantages, it has so far been possible in the pass characteristic only a weak switching effect can be shown in the NDR area.

The object of the invention is to eliminate the indicated Disadvantages of realizing a transistor whose current flow is controllable by a quantum mechanical tunnel effect. Instead of Standard silicon wafers are to be used for the expensive SOI wafers be, and the doping profiles should be improved.

This task is solved by a semiconductor component with the Features of claim 1. There are advantageous designs in the subclaims.

There are a structure and a with the present invention Manufacturing process shown which leads to a vertical Lead tunnel transistor. The electricity transport is based on this electron tunneling from a via a control electrode Influenced conductive channel in the drain electrode. Through the Combination of a vertical arrangement and with the principle of a controlled diode, atomically sharp doping profiles are possible, which is the formation of a suitable tunnel area enable, and in many ways the conventional Enable components superior component.

It should be noted that vertical transistor devices are generally known (e.g. from the published patent application DE 196 21 244 A1), but these differ in principle of the components of the present invention since the known ones  vertical MOS transistors have the same source and drain Have doping, and none with these transistors Tunnel currents occur. In other words, at Use of the semiconductor device according to the invention present invention becomes a completely novel vertical Transistor created.

The figures show:

. Figure 1 shows the schematic structure of an n-MOSFET in a planar embodiment;

Fig. 2 is a schematic representation of tunneling in an Esaki diode with electrical characteristic;

Fig. 3 shows an embodiment of the present invention;

Fig. 4 is simulated characteristics for a PIN diode and a diode Esaki-;

Figure 5 is a process sequence for manufacturing a tunnel transistor. and

Fig. 6 experimental characteristics of a device according to the invention.

The invention will now be described in detail with reference to a preferred one Execution described.

1. Structure of the component

Fig. 3 shows an embodiment which meets the invention according to claim 1. The main components of the component are:

• - A first, highly doped n-layer made of silicon, which acts as a source electrode ( 2 ) with an external contact;
• - A second, highly doped p-layer opposite to the first in the doping mode, which acts as a drain electrode ( 3 ) with an external contact;
• - a third, intermediate layer ( 4 ), the doping of which is preferably kept low, ie is intrinsic or doped below a predetermined doping threshold which is lower than the doping concentrations of the first and second layers;
• - A control electrode ( 5 , 6 ), which consists of a dielectric (z. B. SiO2) ( 5 ) and a conductive layer (z. B. highly doped polysilicon) ( 6 ) (MOS gate), and the an exposed vertical side flank has been applied.

The choice of doping types (n or p) can of course also be reversed, ie layer 2 can be selected as a p-layer and layer 3 accordingly as an n-layer. The layer 4 itself can also be subdivided into several layers or have different doping densities in the vertical direction.

In the figure, the gate ( 6 ) is shown as overlapping with the layers ( 2 ), ( 3 ) and ( 4 ). However, it is equally possible that no overlap to the drain ( 3 ) is provided, as will be explained in more detail below.

2. Function of the component

The physical basis of the function of the component is Esaki tunneling ( Fig. 2). In degenerate-doped semiconductors, the Fermi level is no longer in the band gap, but by a few kT in the bands. If two such areas are in contact, the Fermi levels align, the bands shift accordingly, and electron levels from the conduction band of the n-type semiconductor contrast with electron levels of the valence band of the p-type semiconductor. Due to the high doping, the space charge zone that forms is very thin (a few nm) and can therefore be tunneled through by the electrons. When the external voltage is applied, the electrons tunnel from the occupied states in the valence band of the p-semiconductor to free states of the conduction band in the n-semiconductor in the reverse direction or reverse direction (minus on the p-type semiconductor, plus on the n-type semiconductor). This current grows exponentially with increasing voltage. The component presented is to be operated in this area. In the forward direction or major switching direction (plus on the p-type semiconductor, minus on the n-type semiconductor), the tunnel characteristic curve can form with the NDR if the component quality is suitable. This part of the characteristic is not considered further in the context of the present invention.

The formation of the Esaki tunnel is due to the abrupt contact of two highly doped pn regions. Larger space charge zones are formed in the diffused pn contacts that can no longer be tunneled through. If the two heavily doped pn regions are separated by a low-doped or intrinsic (i) layer, tunneling is also no longer possible. The resulting component is named pin diode after its layer sequence. In the forward direction, a classic forward characteristic curve is formed without tunnel effects, in the reverse direction a blocking characteristic curve with extremely low currents. The blocking characteristics of the Esaki diode and the pin diode can differ by many orders of magnitude when a blocking voltage is applied ( FIG. 4).

Switching between the two blocking characteristics and thus controlling the transistor effect is achieved by influencing a conductive inversion channel ( 7 ) in the i-layer ( 4 ) according to FIG. 3 by means of a control electrode ( 5 , 6 ). In the example shown, a positive voltage at the MOS control electrode creates an electron channel, starting at the source electrode ( 2 ). As the gate voltage increases, this channel extends ever closer to the p-doped drain electrode ( 3 ). This approach of the electron channel ( 7 ) to the p-region ( 3 ) corresponds to an electronic introduction of the n-region to the p-region, as is necessary for the tunneling process. A further increase in the gate voltage leads to an increase in the electron density in the channel and to an increase in the field at the tunnel junction, which also leads to an increase in current. The blocking characteristic of the pin diode with extremely low currents has become the blocking characteristic of the Esaki diode with extremely high currents.

As can be seen, the gate ( 6 ) does not have to overlap with the drain layer ( 3 ) since tunneling takes place between the channel ( 7 ) and the drain ( 3 ).

3. Production of the component

Example of a simple process sequence with 4 mask steps for the exemplary embodiment: (see FIG. 5)

A highly doped n + layer is grown on a lightly doped n-silicon substrate using molecular beam epitaxy (MBE) or gas phase epitaxy (Chemical Vapor Deposition, CVD). A value of 10 ¹⁹ -10 ²⁰ cm ^-3 and a layer thickness of approximately 100 nm is preferred for the doping.

In order to ensure an abrupt, highly doped termination of the n layer, the n layer can optionally be terminated by applying a delta doping layer or a doping surface phase. For a delta doping layer, the surface is pre-coated with the dopant (approximately 10 ¹² cm ^-2 ) at a low temperature (typically room temperature) and then covered with an amorphous silicon layer with a thickness of a few nanometers. The dopant is then diffused into the amorphous Si layer in a tempering step, the layer is crystallized (solid phase epitaxy, SPE) and the dopant is activated. To form a doping surface phase, the dopant is applied to the hot substrate in such a large amount (preferably 30-50% of a monolayer, corresponding to 10 ¹⁵ cm ^-2 ) that the dopant settles on lattice sites and a surface phase is formed. This layer or layers form the source electrode ( 2 ).

An undoped silicon layer ( 4 ) is grown on the source electrode at an elevated temperature (preferably 450-700 ° C.), in which the current path ( 7 ) is later to be formed. The channel layer can also be doped to set the threshold voltage. Homogeneous p or n doping is possible, as are doping profiles. In particular, the transport behavior of the charge carriers in the channel region can be additionally influenced by the introduction of delta doping layers. The channel layer can be terminated with a p-delta doping layer or a p-surface phase in order to ensure an abrupt, highly doped contact with the subsequent p-layer.

The layer stack is completed with the application of a highly p-doped layer, the drain electrode ( 3 ). A value of 10 ¹⁹ -10 ²⁰ cm ^-3 and a layer thickness of approximately 100 nm is preferred for the doping ( FIG. 5a)

After the layer system has been applied, the layers are etched in a first mask step using standard methods (wet chemical, for example with KOH or dry, for example with SF ₆ ) in order to obtain more or less vertical side flanks. According to the dimensions of the etched to the non-etched parts, trench or mesa transistors can be produced.

The gate dielectric ( 5 ) is then applied. For this purpose, thermal oxidation is preferably carried out at 800 ° C. for a few minutes, which leads to an oxide thickness of a few nanometers. Alternatively, other process controls, e.g. B. rapid thermal oxidation (RTO) or other gate dielectrics, e.g. B. nitrides or nitrided oxides possible.

The gate electrode ( 6 ) is deposited on the gate dielectric. Highly doped polysilicon is usually used for this, for which there are various production possibilities. Alternatively, metals, e.g. As aluminum or silicides, possible.

The gate ( 5 , 6 ) is then structured in a second mask step ( FIG. 5b).

The entire surface of the structures is covered with an insulation layer ( 8 ). Typically, a nitride layer applied by means of LPCVD can be used for this. At a preferred wax-up temperature of about 750 ° C., a 200 nm thick nitride layer can be applied in about 1 hour.

In a third mask step, the contact holes for the electrodes are opened in the nitride. Source contact ( 9 ), drain contact ( 10 ), gate contact ( 11 ) ( FIG. 5c). This etching can be carried out dry-chemically with CF ₄ .

As the last step, the metallization is applied over the entire surface and structured in a fourth mask step. The structuring can be done with a direct etching or alternatively with a lift-off step. Typically, the metallization can consist of aluminum, but also of other metals or several metal layers ( FIG. 5d).

The component is thus manufactured to be functional.

The layers can optionally at elevated temperature or at low temperature (e.g. room temperature) with subsequent Recrystallization (solid phase epitaxy, SPE) can be produced. The thickness of the layers can range from atomic monolayers to typically vary a few 100 nm. The sequence of layers can can also be applied the other way round (instead of n-i-p the sequence p-i-n).  

When using highly doped substrates, the lower one highly doped layer can also be omitted. The components can in an additional step through isolation be separated from each other (e.g. LOCOS or trench isolation).

4. Wiring example and electrical characteristics

If you connect the component shown in Fig. 3 so that

• - The source electrode ( 2 ) is set to earth potential,
• - The drain voltage ( 3 ) is varied variably from plus to minus, but without exceeding the breakdown voltage of the pin diode, and
• If the gate voltage is changed from zero to plus, the electrical characteristic curves result as they were obtained from a laboratory sample and are shown in FIG. 6.

If the source-drain voltage is varied without applied gate voltage (V _g = 0 V), the characteristic curve of a pin diode is obtained, in particular in the backward direction an extremely small current. If a voltage is now applied to the gate, an inversion channel is influenced when a threshold voltage, the doping-dependent threshold voltage, is exceeded, as in the case of a MOSFET. Electrons in the channel are led directly to the highly doped p-region and can tunnel into the drain electrode via the Esaki mechanism. The reverse current of the pin diode has become the high current of the tunnel diode. This effect can be clearly seen in the output characteristic field ( Fig. 6a). The characteristic field of a transistor is obtained by controlling the gate voltage. Fig. 6b shows the input characteristic field.

The advantages of the component of the present invention are that

• 1. it as a tunnel transistor completely in existing Si-CMOS Technology can be made  
• 2. through vertical alignment using CVD or MBE methods atomically abrupt doping profiles can be produced,
• 3. no exotic substrates, such as. B. SIMOX, or Space-consuming gate structures are necessary to prevent leakage currents avoid;
• 4. in its wiring with smaller supply voltages (at about 0.2 V and below) compared to future MOSFETs (0.5- 0.6 V) can be operated,
• 5. due to the enormous current swing (reverse current to tunnel current about 10 Orders of magnitude) compared to future MOSFETs (current swing about 3-4 Orders of magnitude) has a substantially safe switching level,
• 6. The advantages of bipolar transistors and MOSFETs combined without having their disadvantages. Bipolar transistors are very fast because they have an exponential control characteristic, but they buy this from the controller's constant current consumption by the base. Low-power circuits are not possible here. Due to the MOS gate, MOSFETs only consume power when switching, which is why CMOS circuits have become dominant for maximum integration. However, the control characteristic of the MOSFET has only a quadratic rise (I ~ Vg ² ) and is therefore slower than a bipolar transistor. The component presented is characterized by a MOS gate control and an exponential control characteristic.

Claims (10)

1. Semiconductor component in which a tunnel current can be influenced via a control electrode with:

• a first layer ( 2 ) of a first doping type (s) which is contacted to the outside,
• a second layer ( 3 ) of a second doping type (p) opposite the first doping type (s), which is contacted to the outside,
• - at least one third layer ( 4 ), which lies between the first and second layers,
• the first, second and third layers form a vertical layer sequence,
• - A control electrode ( 5 , 6 ), which is set up to control a current path between the first and second layers, the current path comprising at least one section in which a tunnel current flows.

2. The semiconductor device according to claim 1, characterized in that the control electrode (5, 6) an insulating layer (5) and a conductive layer (6), wherein the insulating layer, the conductive layer of the vertical layer sequence of electrically insulated. 3. Semiconductor component according to claim 1 or 2, characterized in that only one layer ( 4 ) is provided between the first and second layers, and this one layer ( 4 ) is homogeneous and of intrinsic conductivity. 4. Semiconductor component according to claim 1 or 2, characterized in that only one layer ( 4 ) is provided between the first and second layers, and this one layer ( 4 ) is p- or n-doped, or has a doping profile. 5. Semiconductor component according to claim 4, characterized in that only one layer ( 4 ) is provided between the first and second layers, and this one layer ( 4 ) also contains delta doping layers or doping surface phases. 6. Semiconductor component according to claim 5, characterized in that the delta doping layers or doping surface phases are provided at the contact with the first and second layers ( 2 , 3 ). 7. Semiconductor component according to one of claims 1 to 6, characterized in that the vertical thickness of the first and / or the times and / or the third layer in the area from an atomic position to 200 nm. 8. A semiconductor device according to claim 7, characterized characterized in that the vertical thickness of the first and / or the second and / or the third layer at approximately 100 nm lies. 9. Use of a semiconductor component according to one of claims 1-8 as a transistor, in which the current when the first layer ( 2 ) and the second layer ( 3 ) are switched in the reverse direction is controlled by a voltage at the control electrode. 10. A method for producing a semiconductor component according to one of claims 1-8, comprising the following steps:

• - application of the first ( 2 ), third ( 4 ) and second ( 3 ) layers onto a substrate ( 1 ) in this order,
• Exposure of vertical side walls by etching,
• - Application of an insulation layer ( 5 ) on the exposed side wall,
• - Application of a conductive layer ( 6 ) on the insulation layer ( 5 ), and
• - Opening contact holes and applying a metallization to create external contacts for source, drain and gate.