DE2057030A1 - Method and circuit arrangement for checking errors in control information honing - Google Patents

Description

Method and circuit arrangement for checking errors in control information The invention relates to a method and a circuit arrangement for error control ile of control information that intervene in the processes of a computer system and in each memory block, the main memory, which is divided into blocks, of a computer system stand.

In data processing systems it is necessary to process the To constantly check information for correctness. One of those controls consists in the parity check by which a selected for information transfer The code checks whether the number of individual bits is constant and even or odd number.

If an error is detected, a signal generated. Such an error signal can be used to continue the calculation process interrupt until a correction is made or otherwise indicated that there is an error.

If this is the case, a signal is emitted by the test facility, which leads to the abortion of the respective operation.

Another way of control is that the plant or large system parts are built up twice. Both copies calculate from each other independently, albeit at the same time, and compare their results.

It has already been suggested that the control information for a Computing system are stored exactly once in each memory block and that at Access to this control information starts a memory block in which no Storage cycle expires and there is no request for the nocb.

This applies to such computing systems that have several independent memories or have memory blocks to which several works one after the other on a path or in parallel on several. Ways to be able to access.

The control information to be read is then stored in several or all memory blocks, each saved once under certain addresses. So can for example, the first n addresses of each memory block contain such control information contain.

The control information that intervenes in the processes of the computer system and are in the main memory of the computer system, are therefore in each memory block of the memory, which is divided into blocks, in order to quickly access this information to be able to access. There is no validity check for this procedure the control information in the main memory.

The purpose of the invention is to control the validity of the in memory Allow standing tax information and the tax information if applicable to correct.

The object of the invention is to provide a method and a circuit arrangement to create where the fact that the same control information is in the divided into blocks Main memory of the computer system in each Block are once saved, is used to provide error control and a, carry out any necessary error correction.

The object is achieved according to the invention by a method in which the same control information as part of the error handling of the computer system different memory blocks can be read and compared with each other in order to thereby to check whether this control information is still correct in the memory blocks stand, and if there is no equality between two pieces of control information, a flip-flop is created switched on and with the help of the flip-flop a signal is formed which indicates which of the memory blocks needs to be corrected.

Another implementation is that the found to be false Control information is automatically corrected by the cached comparison result is used to form a signal indicating which memory block the tax information to be corrected can be fetched.

Another embodiment of the invention solution consists in the fact that an error message is issued in the event of an error that cannot be automatically corrected is delivered.

There is a further solution to the problem for carrying out the method in a circuit arrangement in which the memory blocks that are to be compared and possibly contain control information to be corrected, of the working memory connected to a comparison device which supplies a comparison statement are and this comparison device with flip-flops in which the comparison statement is stored, is connected and that the outputs of the flip-flops to a decoder which supplies the signals that indicate in which memory block the control information must be corrected and from which memory block the for the information used for correction is to be fetched and that the outputs are at the same time the flip-flops and the outputs of the decoder to a circuit which a Emits error signal, which indicates an uncorrectable error, is performed.

The advantage of the invention is one automatic Control and extensive correction of tax information and in that in the event of an uncorrectable error, an interruption of the process is caused, whereby the greatest possible security of the normal process, z. B. a computer program is given.

The invention is to be described in more detail below using an execution example explained. The accompanying drawings show: FIG. 1: Block diagram for error control of the control information, Fig. 2: Representation of the logic circuit for the formation of the signals Ki and Ri, Fig. 3: Block diagram for error control of the Control information of a micro-programmed system.

The embodiment shown in Fig. 1 is for four memory blocks designed. The four memory blocks 1 ... 4 are connected to a comparison device 5. The output of the comparison device 5 is on six flip-flops A12; A13; A14; A23; A24; A34 led. The flip-flops A12; A13; A14; A23; A24; A34 work on a decoder 6 and at the same time on a circuit 7.

The output of the decoder 6 is also sent to the circuit 7 guided.

The spring of the four memory blocks 1 ... 4 contains the one to be compared and possibly for corrective control information 8. This control information 8 becomes compared in the comparison device 5, and after the comparison, the comparison statements in the six flip-flops A12; A13; A1.4; A23; A24; A34 saved. The comparison takes place by reading the control information 8 in the first memory blockl1 and compared with the same control information 8 located in the second memory block 2 will. In the event of an inequality, the flip-flop A12 is switched on. It will then the one in the first memory block 1 with the same in the third memory block 3 standing 8 control information 8 is compared and, in the case of inequality, the flip-flop Al 3 switched on etc.

It therefore means that in the comparison of the control information 8 off one of the memory blocks 1 2; 3; 4 and a further memory block 1; 2g 3; 4th two control signals are supplied, these control signals in the event of inequality, the respective corresponding flip-flop A12; A13; A14; A23; A24; A34 turn on.

Are several of these flip-flops A12; A13; A14; A23; A24; A34 switched on, must be decided with the help of majority considerations, which tax information 8 are correct.

By means of the comparative statements which are contained in the flip-ilops A12; A13; A14; A23; A24; A34 is saved, the information recognized as incorrect correct. The decoder 6, which is based on the stored comparison statements, is used for this purpose forms eight signals K1 ... K4 and RI ... R4.

Four of these signals KI ... K4 are assigned to the four memory blocks 1 ... 4 and mean that in the corresponding memory block 1 ... 4 the one located there Control information 8 is to be corrected.

Four further signals R1 ... R4 indicate from which memory blocks 1 ... 4 the control information 8 to be corrected is to be fetched.

The signals K1 ... K4 and RI ... R4 are in the decoder 6 according to the following logical equations formed, wherein in Fig. 2 the formation of Signals K1 and R1 is shown again in terms of circuitry.

K1 = A12.A13.A14. (A23.A24.A34vA23.A24.A34vA23.A24.A34v A23.A24.A34) K2 = A12.A23.A24. (A13.A14.A34vA13.A14.A34vA13.A14.A34v A13.A14.A34) K3 = A13.A23.A34. (A12.A14.A24vA12.A14.A24vA12.A14.A24v A12.A14.A24) K4 = A14.A24.A34. (A12.A13.A23vA12.A13.A23vA12.A13.A23v A12.A13.A23) R1 = A14.A24.A34. [A12. (A13.A23vA13. A23) vA12.A13.A23] R2 = A12.A13.A14. [A24. (A23.A34vA23.A34) vA23.A24.A34] R3 = A12.A23.A24.A34. (A13.A14vA13.A14) R4 = A13.A23.A34.A14. (A12.A24vA12.A24) Through these signals K1 ... K4 and R1 ... R4 is the further procedure for the case of a correction to be made is determined. Will now, based on the comparison statements, an error was recognized, but not automatically can be fixed. a circuit 7 becomes effective which emits an error signal 9.; ibt ;, that indicates an error that cannot be corrected.

The error signal 9 results from the logical function FS = (A12vA13vA14vA23vA24vA34) .R1.R2.R3.R4 In the event that the data processing system is microprogram-controlled, is in Fig. 3 a block diagram is shown.

the necessary logical decisions for error detection can be made here and correction can be implemented by a sequence of microinstructions 10. the The logic circuits required for this are and can be much smaller in scope mostly be identical with certain parts of the circuit for the remaining processes. In simple cases, such a system contains two operation registers 11; 12 and a result register 13, an arithmetic-logical work 14, a memory 15 and the controlling micro instruction 10.

For error handling is now to be requested - this request is in most cases fulfills -that the arithmetic logical work 14 allows that Operands in operand registers 11; 12 to be linked logically.

The logical operations are in accordance with the equations given AND, OR, ANTIVALENCE necessary.

There is then the task of using a corresponding sequence of micro-instructions 10 step by step using the above procedure use a part of the memory 15 as an auxiliary memory eiie those logical relationships to realize which are given in the equations.

Claims (4)

Claims 1. Procedures for checking errors in tax information. those in the Processes of a computer system intervene and divided into blocks in each memory block RAM of a computing system are, characterized in that the frame the error handling of the computer system the same control information from different Memory blocks are read and compared with each other that controlled whether these control information match and that if there is a disparity between two control information a flip-flop is turned on and with the help of the flip-flop a signal is formed which indicates in which of the memory blocks the control information must be corrected. 2. The method according to claim 1, characterized in that the as Incorrectly determined tax information can be automatically corrected by the cached comparison result used; is used to form a signal, this indicates from which memory block the control information to be corrected is fetched can be. 3. The method according to claim 1 and 2, characterized in that at an error message is issued for an error that cannot be automatically corrected. 4. Circuit arrangement for carrying out the method according to the claim 1 ... 3, characterized in that the memory blocks (1 ... 4) of the main memory connected to a comparison device (5) in that the comparison device (5) is connected to flip-flops (A12; A13; A14; A23; A24; A34) and the outputs the flip-flops (A12; A13; A14; A23; A24; A34) are routed to a decoder, that at the same time the outputs of the flip-flops (A12; A13; A14; A23; A24; A34) and the Outputs of the decoder (6) to a circuit (7) generating a fenler signal be led.