DE2359036A1 - DEVICE FOR CONNECTING SEVERAL DATA PROCESSING UNITS TO A SINGLE MEMORY - Google Patents

Description

INSTITUT FRaNOAIS DU PETROIE DES'GARBURANTS ET LUBRIPIANTS, Rueil-Malmaison, France

Device for connecting several data processing units with a single memory

The invention relates to a device for connecting several data processing units to a single one Storage.

Each processing unit has, in the usual way, a processing unit or a processing system that is provided by executes commands delivered to a central memory and communicates with external peripheral devices by means of Restore units restores, with a controller

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a logical organ for the synchronization of the one "Microprogram-controlled elementary transfers take place,

The operation of each processing unit includes the use of computer programs and of so-called "channel ^w programs" which include the supply of data from peripheral devices to the computer and the transmission of results to the same devices.

To avoid difficulties in the coordinated execution of the calculation programs and the channel programs may arise, and to account for the priority rank, the operation of each processing unit includes the Use of a building block for specific microprograms, i.e. memory words and binary status numbers, which are suitable to handle different processes. These building units are "referred to as potential process computers.

Each processing unit (sequence calculator) can be in one of the are in the following states:

- available, i.e. it has no program to execute,

- can be activated, i.e. it is waiting for the processing system to have a program carried out,

- active, i.e. it uses the processing system,

- in the waiting state, i.e. it waits for the end of a data transmission and does not work even if she expects tasks.

The processing unit can also remain in one of the states specified above, with the exception of the waiting state, and can therefore never be blocked. The status of a sequence calculation unit is determined by its presence a list assigned to it, which at least

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has a task that she is capable of performing herself. The task is to assign a Elaborated program for the implementation of a certain process and a control block in the central storage unit set. This control block is also known as the "task owner" denotes and consists of a group of word fles Central storage, which define a task and its execution or storage in the "case allow an interruption.

Each task can be in one of the following states are located:

- available, i.e. the corresponding operations have been completed or have not yet started,

- Can be activated, i.e. it is on the waiting list of your process computer and cannot be executed until then until the current task is completed,

- active, i.e. it is currently being executed on your process computer,.

- in the waiting state, i.e. one or more external events require their return to the waiting list of an expiry candidate.

The structure of a potential sequence calculator in a processing unit therefore requires a system to

- to establish a hierarchy between the process computers and the processing system to the primary sequencer to provide,

- on waiting lists assigned to each process computer unit Set up tasks and carry out the same.

• As is also discussed in the course of the description,

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each computer has a data processing system, one Central memory connected to the processing system, devices for restoring data with peripheral ones Devices via at least one data transmission path, and a microprogrammed one Automatic organ on the one hand for controlling the storage processes via the aforementioned transmission path as well as a computation process and on the other hand for the execution of tasks, which the computation and restoration processes are assigned to.

The ■ automatic organ has a first automatic Management system for controlling the execution of commands taken from the memory and a second automatic one Mihring system for the establishment of a hierarchy between the similar transferring processes and arithmetic processes assigned tasks of the lists and available of the processing system for the task at the top of the ranking list. Also, the automatic Organ a third automatic management system for the creation of lists without a hierarchy of those that can be activated Tasks that are assigned to various similar processes and how to carry them out.

The automatic organ is with control devices and testing of a first organ for storing the status of the lists of those associated with the computation and restoring processes Tasks, with a second organ to store when one of the list tasks takes precedence, and with one third organ for storing the process currently being carried out.

When you have several processing units with a single memory connects, each of them has its own peripheral devices. The channel programs are then not only

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dependent on a potential runoff, but also to a specific processing unit. In contrast, the entire reunion program is about any one Process computer carried out.

You enter a word in the central plague address recorder, which the first that can be activated and selected for each process computer Task specifies, and also a binary number, which specifies when the process computer assigned to the task can be activated or not. The connection arrangement must have means for synchronizing the dialogue between the Have processing units with the Speieher.

This connection arrangement is characterized in that it has switching devices which each correspond to the processing units are assigned and are each provided with outputs, the number of which counts these processing units is equivalent to. The connection arrangement also has decoding devices for over the above Switching device made control of the switching of a trigger signal, which by a third automatic .sches System of any processing unit is generated on the actuation input of the second memory member one of the processing units, corresponding to the value of a binary number, which is assigned to a task, the belongs to a new list drawn up by the third body mentioned.

Other features and advantages of the invention are set out below explained in more detail with reference to the accompanying drawings. Show it

1 schematically shows the structure of a processing unit,

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Pig. 2 schematically the elements of the microprogrammed automatic organ assigned to the status registers are, for the EaIl that each processing unit has four potential process computation units,

3 schematically shows several connected to a central storage unit Processing units,

4 schematically shows the devices of the connection arrangement which are assigned to all processing units are to allow dialogue between them and the store,

Fig. 5 schematically shows the circuit assembly of the connection arrangement , and

6 schematically shows a system for synchronizing the requests with regard to the connection between the processing units and the memory.

The microprogrammed computer shown in Fig. 1 has a control device, which by a "dead" Memory 1 is formed, are stored in the microprograms. In addition, the calculator has an arithmetic and logical arithmetic unit, which is generated by an arithmetic unit 2, an instruction register 3, a local register memory 4 and a module 5 formed with status registers will.

A control device 7 of a “living” central memory 6 is interconnected with this via a memory collecting line 8. Likewise, a device controls the transmission of data between the computer and not shown peripheral devices by means of a manifold 10. The transfers between the various elements of the

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Computer are ensured by an internal manifold 11. A so-called test manifold 12 also connects the various elements with the dead memory and leads to these data, which relate to the condition of the reclaner in different places ", and enables the latter, to line up the removed microinstructions one after the other. '.

Fig. 2 shows that the dead memory 1 is divided into three parts or modules. It comprises a standard command execution block, which is assigned to the processing device 15 and allows data taken from the central memory 6 Evaluate and execute commands. This block has a main microprogram block called the "base processor" 13 and four auxiliary microprogram blocks 131 »132, 133 and 134, which are designed to carry out of commands that specifically concern each of the process computers of the arrangement.

The main module and the four auxiliary modules are connected to the central memory 6 connected. The four auxiliary modules 131 to 134 are controlled by the main module and transmit signals to it, if the commands with which they are loaded have been carried out in the process computers that correspond to them.

The four auxiliary modules concern four potential processes— computers that, for example, perform fast data transfer operations adapted "channel" process computer CR, a process computer TR designed for real-time calculation, one for multiplex information processing designed "channel" flow computer CMX and a Reehenablauirechner GAL can be.

The two other dead memory modules are;

- a block 14 »which is controlled by a micro-programmed automatic System is formed to create a hierarchy

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between the sequence of events or also, between the task lists assigned to them and made available to the processing system 15 (arithmetic logic unit) formed by the arithmetic unit 2, the command register 3 and of the register memory 4 (Fig. 1) for the ranking process computer (dispatcher),

- and a block 16 controlled by a micro-programmed automatic System is formed for the creation of waiting lists for activatable, assigned to each process computer Tasks and their implementation (scheduler).

The guide block 14 is connected to the memory 6 and to the base processor (main module) 13. The miter block 16 is also triggered by the main module 13 when it has a command "system" IS in its microprogram, i.e. an activation command for one or more tasks to be performed.

The guide block 16 is specially designed so that a maximum use of the computing system and in particular one Hierarchization of the tasks is made possible. He knows Means for temporarily expiring the waiting position for a task under its exclusion from the waiting list and their subsequent reintroduction. Among the tasks on a waiting list, there may be some of them Be the subject of several different questions. They are known as "auxiliary questions".

To take account of this successive coinage the guide block 16 has means for storing in the "descriptor" of the task in question. He also has a system for recognizing a command that is the end of operations related to a task, and to exclude or reintroduce them, provided that all successive auxiliary queries have been satisfactory or not.

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.If there is a task that needs to be clarified, however, with the same Process computer is linked, is queried, the Task management block 16 means for introducing the descriptor of this task into the waiting list.

The module 5 of the status register has a first register 19 with four bistable flip-flops BGR (191), BTR (192), BCMX (193) and BOAL (194), each of the four process computers GR, TR, OMX and CAL are assigned and by the Mihrungsblock 16 are operated. The guide block 14 is with means for checking the state of these four tipping stages " Mistake. "-

The module 5 of the status register also has a flip-flop EXD (17), which by the! Pührungsblocks 14 and operated and by the basic amplifier (main module) 13 as well as a register 18, which has two bistable flip-flops PAO (181) and PA1 (182) assigned to it, can be checked. The four different binary numbers that can form these latter flip-flops as a whole, each correspond to one of the four process calculators. These - Both flip-flops are controlled by the J control block 14 and can be accessed through the main module 13 of the standard instruction execution block check. The same main module 13 is provided with devices for testing the flip-flop EXD.

The registers 18 and 19 as well as the flip-flop 17 of the module 5 of the status register enable synchronization different blocks of the microprogram memory 1.

The number stored in register 18 is the key of the active process computer fixed The flip-flop EXD is operated by the IT guide block 16 when the latter the Transition from a priority process computer to the one that can be activated

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Controlled state. The main module 13 of the execution block recognizes the test of the flip-flop EXD any deviation in the composition of the process computer that can be activated and in this case activates block H, which creates a hierarchy among the process computers.

The four flip-flops BOR, BTR, BCMX and BCAL are through the block 16 is set in one or the other of its equilibrium states, depending on whether the corresponding Process computers are available or can be activated,

The synchronization mechanism is then very simplified. The task management block 16, which is triggered by an external "auxiliary question" DR or by a command system IS, d * h. is triggered by an activation command relating to one or more tasks to be carried out, is activated when these tasks are arranged. The arrival of a command relating to one of the tasks to be carried out in an available process computer enables this process computer to be activated. In this case, the guide block 16 stores this change in the corresponding toggle stage of the register 19.

If, in addition, the new process computer that can be activated has priority over the active process computer, the guide block 16 triggers the flip-flop EXD (17) and transfers the monitoring to the main module 13. This checks the flip-flop EXD and transfers the monitoring to the guide block 14- »the Execution of the task is interrupted in the course of execution and controls the transfer of the contents of the registers of the local memory 6 (see FIG. 1) to that cell of the memory 6 which is assigned to the control lock of the task that has been interrupted. It deals with the examination of the flip-flops BGR, BTR, BCMX and BCAL of the register 19 to the task

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Look at the top of the list of tasks related to the new activatable process computer are assigned and activates the register 18 for storing nature of the process computer to which the processing system is matched is. It then controls the transfer of a certain number of anticipated words in the control block of the new ones Task (context) in the registers of the local memory 4 · In particular, one of these ¥ words is in its ordinal counter transfer. This last operation is commonly referred to as "InitialisataDn".

The monitoring block 14 again transfers the monitoring to the main module 13 and attaches it to the priority Process computer corresponding program by a usually, operation called initialization. The main module controls the reading of the ordinal counter and the reading of the corresponding Command in command register 3 «It causes register 18 to be checked to interpret the code of a command contained in the command register 3, whether it is a command relating to an invoice or to a "channel" command relating to data transmission acts.

When the operation assembly corresponding to this new priority has completed its work, the main module 13 transfers the supervision to the cutting block 14, which again transfers the content of the control block for the task that was interrupted in the register of the local memory 4 controls. Execution of the interrupted task can then be resumed will.

Each potential process computer is defined as a whole by the state of the trigger stage corresponding to register 19,

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from the word of the address of the descriptor of the first containing this task to be performed Memory, from the main module 13 and for this Process computer specially designed auxiliary modules 131 "to 134.

Im in Pig. 2 are four processing units 20, 21, 22 and 23, which with the previously described match, connected to the living central storage unit 6 by means of a collecting line 24. Each of these units is also connected to a group of peripheral devices, which is done through the buses 251, 252, 253 and 254 occurs. This group is not shown.

Due to this structure, any channel program is not only available to a specific potential process computer, but also fed to a single arithmetic unit. A specific waiting list of channel programs is then set up for each of the channel flow computers of each arithmetic unit is created. In contrast, the entire arithmetic program could equally be carried out on the four arithmetic units.

A single arithmetic program list can be created and is accessible to the four arithmetic units.

Each task is assigned a "task descriptor", i.e. a group of words which define them and their execution or retention in the pail of an interruption enable. Each task descriptor contains a first group of two binary numbers in its first word, which determine the arithmetic unit on which this program is carried out and a second group of two binary numbers, which determine the potential process computer on which it should be done.

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In the case of a computer program, the state is the first Group of numbers is not essential, since this program can be carried out on any of the arithmetic units can.

The address of the first task selected for each AI calculator is stored in the central memory 6. Each Arithmetic unit has three channel flow computers and one arithmetic flow computer on. In total, the group of four arithmetic units is provided with thirteen process computers. The same Due to this fact, the number of words is stored in the central memory 6 with a fixed address.

Each word has the address of the first activatable task ADT and a binary number S, which determines whether the corresponding process computer can be activated. The combination from the address and the number S "determines the state of the Process computer with:

ADT = O process computer is available

S = 1 and ADT £ O process computer can be activated S = O and ADT Φ 0 Process computer is on hold.

The state of the process computer in activity is determined by the flip-flops PAO and PA 1 of the register 18 (see Fig. 2) each arithmetic logic unit determined. The thirteen words, each corresponding to the thirteen process calculators, become in each Arithmetic unit constant through the various guide blocks kept up to date and checked by the blocks 14 provided for keeping the waiting lists of the process computer.

The dialogue between the arithmetic units is facilitated by the introduction these thirteen words of the central memory are secured by the control of a synchronization system, the one -synchronized Interconnection system between the

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various elements of the microprogram memory and also a system for establishing a precedence between has the arithmetic units.

The connection system assigned to each arithmetic unit has (FIG. 4) an assembly 26 which is connected to the guide block 16 of the waiting lists of the activatable tasks. The assembly 26 is provided with a 2-bit / 4-bit decoder of known construction, which is connected to the inner bus 11 (see S ¹ Ig. 1). The four output connections of this decoder are each connected to a first input of four UED gates 281, 282, 283 and 284, the second inputs of which are connected to an output of the routing block 16.

The outputs of the four AND gates 281, 282, 283 and 284 are each to one of four, the four arithmetic units associated bus lines 291, 292, 293 and 294 connected. The leadership blocks of the waiting lists of those that can be activated Exercises 161, 162, 163 and 164 of the four arithmetic units are with the four outer collecting lines 291, 292 293 and 294 connected by means of the assembly 26.

The flip-flops 171, 172, 173 and 174 (Pig. 5), which are used for storing the state of a priority, are provided that can be activated, have a first input, each connected to the four manifolds 291, 292, and 294, and a second input, each with input connected to the four blocks 141, 142, 143 and 144. The latter four blocks 141 Ms 144 are for guidance the process computer of their respective arithmetic units provided.

This system enables the interconnection between the arithmetic units. If one of the guide blocks 161, 162, 163 and 164 the waiting list of a priority process computer

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assigned tasks and this activated 'has switched, it causes the first word of the descriptor of the priority task to be read from the list and controls the transfer of this word to the inner bus 11. One of the decoders, eg 27 ₉ controls the Switching through one of the AND gates 281, 282, 283 and and the transmission of the response control signal of blocks 161 to 164 to one of the outer bus lines 291 to and consequently to one of the input connections of the trigger circuits 17, 1, 172, 173 or 174 assigned to this line.

The two from an internal manifold 11 to one Binary numbers transmitted to decoder 27 are taken from that part of the first word of the task descriptor, which determines the number of the respective arithmetic unit.

Such an interconnection system enables each guide block 161 to 164 to trigger any trigger stage without preliminary knowledge of the arithmetic logic unit _t to which the trigger signal of the trigger stage leads. Because of this, the execution blocks 161 to 164 are absolutely identical, and each of them has access to the group of tasks residing in memory. The arithmetic units differ from each other only in their connections to the external collecting lines.

All in all, this system allows very quickly that in the case of an arithmetic unit, one of its processors changes from the state of availability to the state of being able to be activated.

The transfer between the processing units takes place by means of one of the thirteen words of the memory, each correspond to one of the thirteen process computers, these units should not modify these words at the same time , still check. Therefore the arrangement assigns a system. :

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Creation of a priority between the arithmetic units on.

The priority system assigned to each arithmetic unit has (Pig. 6) a first "bistable flip-flop DSY, which controlled by microprograms stored in the control blocks 14 and 16 (Pig. 2) of each processing unit are, a second bistable flip-flop ESY, a collecting line 30, a common to all priority systems Line 31 and logic gates for connecting these elements to one another.

The output of an AND gate 32 is connected to one of the inputs of the flip-flop ESY. The three entrances to this gate are each connected to the non-inverting output Q of the flip-flop DSY, to the line 31 via a OR gate 33 and to the inverting output Q of the flip-flop ESY via an AND gate 34 and an inverter in series there. The output Q of the flip-flop ESY is connected to the input of the OR gate 33, to the input of an AND gate 36 and connected to the test bus line 12 (not shown) (Pig. 1) via line 37. The manifold 30 is connected to the output of the AND gate 36 and to the input of the AND gate 34. The output Q the flip-flop DSY controls an AND gate 38 between any two consecutive arithmetic units assigned priority systems is switched on.

At the beginning of every microprogram, which is used in every management block and 16 each arithmetic unit is assigned, a microinstruction is introduced which relates to a microprogrammed Guidance query from thirteen, the thirteen process computers corresponding words in memory.

In the absence of such a query of part of a

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Microprogram, the AND gates 38, welclie through the from the output Q of each flip-flop DSY are controlled, unlocked, and the activation signal is present along the line 31.

A command query from an arithmetic unit causes the DST flip-flop to be activated in accordance with the Microinstruction S issued signals and the blocking of the associated AND gate 38. Because of this, the activation signal is no longer on the other priority systems transmitted via this gate.

The activation of a toggle stage DSY causes the unlocking of the corresponding AND gate 32 and the actuation of the flip-flop ESY by one of a not shown Clock emitted signal. This flip-flop ESY thus indicates that the guidance query presented by an arithmetic unit has been given priority and that the others can make such queries as a precautionary measure. The state the flip-flop ESY is transmitted via the line 37 to the test bus, which the arithmetic unit, which the Question, notified of the priority assigned to him.

The actuation of the flip-flop ESY causes the actuation of the bus line 30 and via the AND gate 34 and the Inverse stage 35 the blocking of the AND gate 32 of the priority systems, which are behind the AND gate 38 blocked by the priority question. If the queried When leadership has come to an end, the DSY flip-flop becomes reset to zero by a signal ^ which is issued by a microinstruction belonging to the routing block. This reset to zero enables the Management query from other calculators.

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This operation concerns the creation of a hierarchy between the arithmetic units and the prohibition of several of these Arithmetic units to intervene in the management of the thirteen 'words of memory at the same time.

Modifications can easily be applied to the device without departing from the essence of the invention would be.

Instead of using a register 19 (see Pig. 2) to determine the state of the activatable process calculator, i.e. three of the channel process calculators relevant binary numbers plus a number common to all arithmetic units to determine the state of the process computer that can be activated for the calculation, one could queue these numbers in the central memory. This amendment could apply when testing these binary numbers does not occur very often and therefore, due to this fact, the introduction of additional facilities for Saving the state of the process computer is not justified.

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Claims (7)

Claims Device for connecting a central memory with a plurality of data processing units, each of which is essentially a data processing system, facilities for restoring data with peripheral devices via at least one data transmission path and a micro- programmed automatic device associated with a first automatic mowing system for control the execution of instructions taken from the memory, with a second automatic guidance system for the establishment assigned to a hierarchy between the lists of similar storage processes or a computation process Tasks as well as providing the processing system for those at the top of the priority list current task and with a third automatic feeding system for the establishment of non-hierarchical views' Lists of different similar processes assigned, activatable tasks is provided, with the automatic device control and test means for a first device for storing the status of the Lists of the arithmetic or relocation processes assigned Tasks, for a second facility to store when one of the task lists becomes a priority, and for a third device - for storing an active sequence , characterized in that switching arrangements assigned to the processing units are provided in each case each having a number of outputs and decoding devices corresponding to the number of processing units for controlling the switching of one of a third automatic system of any processing unit generated trigger signal of the second storage device on the switching arrangements. 409823/0848 - 20 - the actuation gear of the second storage device have one of the processing units, corresponding to the value of a binary number, which one au is assigned to an on-gate belonging to a list newly established by the third automatic system. 2. Device according to claim 1, characterized in that each switching arrangement is one with the number of processing units has the same number of logical AND gates and that the associated decoding devices are connected to an inner manifold with facilities for storing from is connected to commands taken from a central memory. 3. A device according to claim 1, characterized in that each processing unit is assigned a validation system, which consists essentially of an element for storing transmitted by a processing unit Durchsolialteabreuren, of an element for registering the validation of the query and of elements that at least by the Speiclisrungseleinent are actuated to validate the query, and that devices for synchronization between the validation systems are provided to block the validity sklarungssysteiae of those of the associated processing units whose interconnection query is subordinate to the valid query. 4. Device according to claim 3, characterized in that the synchronization devices on the one hand an arrangement for series connection of the validation elements of different systems, devices for delivery a trigger signal of the validation elements to the aforementioned arrangement and between 409823/0848 - 21 - the validation elements activated elements to interrupt the transmission of the trigger signal by controlling the storage means and on the other hand with a circuit for interconnection the registration facilities of the validation declarations of the queries is provided. 5. Device according to claim 4 »characterized in that the registration devices of the declarations of validity each system have a bistable flip-flop that the validation elements have a first AND gate have one of the inputs connected to a circuit formed by an AND gate, which is connected to a first output terminal of the bistable multivibrator and to the interconnection circuit is, with a logic circuit in series for reversing the signal output by the second AND gate is provided, and that the interconnection circuit of the systems by means of a third AND gate to a .second output of the bistable multivibrator is connected ... .6. Device according to claim 5 »characterized in that the storage element has a bistable multivibrator, one terminal of which is connected to one of the inputs of the first AND gate and the other connection to the interrupt device the signal triggering device is connected. 7. Device according to claim 5 »characterized in that one of the inputs of the first AND gate is connected to an OR gate, one input of which is connected to the Connection circuit of the validation devices and the other input of which is connected to the second output of said bistable multivibrator. 409823/0848 Blank page