DE2419816A1 - METHOD FOR MANUFACTURING BIPOLAR TRANSISTORS - Google Patents

Description

The invention relates to large scale integrated circuits constructed from bipolar transistors, and more particularly to a Process for the production of such transistors, which enables a great reduction in size.

At the moment, in the construction of highly integrated circuits, which are further abbreviated as LSI as usual, two main goals aimed at: '■'

1. the maximum number of components on a semiconductor crystal wafer to enable it not to be so large as to be inconvenient for manufacture; and

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2. to maintain a prescribed working speed with low power dissipation.

Purely bipolar LSI represents a serious power dissipation Problem. In general, the power dissipation is 1 milliwatt per component. In the case of a semiconductor crystal plate, which contains 5000 components, this leads to a power loss of 5 watts per semiconductor crystal wafer. It is obvious that this is the case with semiconductor crystal wafers which have 40,000 or 50,000 components contain, can lead to a very serious problem.

Both of the above problems can be addressed by downsizing each individual transistor. Downsizing the transistor allows one to be attached larger number of transistors on a semiconductor crystal wafer of a given size and reduces the parasitic capacitances of the transistor. The latter allows operation at a predetermined speed at a higher impedance level, which results in a lower power loss.

For the construction of a conventional LSI, bipolar transistors are manufactured according to a process which includes several Includes steps of a selected impurity diffusion into a semiconductor body or substrate. This verse

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is sometimes used as a triple diffusion process because three separate diffusion steps are carried out around the emitter region to form within the base area and the base area within the collector area.

To define the areas within which the diff-yusions are to take place, a separate masking process will take place for each of the different diffusion steps executed. The masking is carried out using a photolithographic process in which a mask is produced from an oxide layer on the semiconducting substrate, the oxide layer is coated with a photoresist, the photoresist is exposed through a mask template, "the exposed photoresist is developed and the oxide layer is etched away through the photoresist pattern until the surface of the semiconductor is bare. The oxide works for diffusion as a barrier, so that the diffusion areas are limited when the semiconductor plate is subjected to diffusion.

The major factor that limits the size reduction of a triple diffused transistor is the positioning tolerance in the photolithographic process. Making a triple diffused bipolar A transistor can be viewed in a simplified form as an analogue to the production of three interlocked

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Imagine bathtubs of decreasing size corresponding to the collector, base and emitter. Of the Collector has the largest area and is diffused into the substrate. The base is intermediate in size and has diffused into the collector area. The emitter has the narrowest area and is in the base area diffused.

An essential rule for the manufacture of a transistor states that the surfaces of the diffused in Areas or tubs must not touch one another. This has the consequence that the emitter diffusion layer in the vertical direction flatter than the base diffusion layer and the base diffusion layer flatter than the collector diffusion layer have to be. In the horizontal direction there will be a difference in size between adjacent areas or tubs that are large enough to ensure the tolerance within which they fit into each other are arranged, does not have the consequence that their edges touch. This tolerance is the factor that makes a downsizing of triple diffused transistors limited.

A process in which the three diffusion layers of a bipolar transistor align themselves is thereby allows that according to the invention a single tolerance range for all three diffusion layers instead of individual Tolerance ranges between adjacent diffusion layers is set. The only tolerance limit established in this way

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rich defines an annular area within which deposits are prevented.

In one embodiment of the invention, a silicon nitride layer is in particular on the semiconducting Substrate in a ring shape with a single opening, which defines the outer boundaries of the first diffusion area, applied. The silicon nitride layer is used as a permanent mask for all three diffusions. It serves as the only mask within the during the first diffusion Transistor area. For the second diffusion, a region of the opening in the silicon nitride layer is provided with a Covered silicon dioxide layer, and the two layers of silicon nitride and silicon dioxide form a composite Mask for the second diffusion. For the third diffusion, the silicon dioxide layer is separated from the silicon nitride layer removed and a second silicon dioxide layer made around another part of the opening to cover in the silicon nitride layer. The one from the silicon nitride layer and the new silicon dioxide layer composite mask defines the area for the third diffusion.

The only requirement for the positioning of the silicon dioxide masks is that their edges must be within the tolerance range set by the silicon nitride mask.

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In summary, the invention can be described in such a way that in one on a semiconducting substrate applied silicon nitride layer an opening is etched, which the outer boundaries of a diffusion transistor specifies. The silicon nitride layer serves as a permanent, stationary diffusion mask. The first diffusion or doping is passed through the remaining mask opening performed. After that, parts of the permanent mask opening are covered by applying silicon dioxide layers, and successive diffusions or dopings are through different unmasked portions of the permanent mask opening carried out through it.

The invention will now be described in greater detail on the basis of exemplary embodiments and on the basis of the attached schematic representations explained.

Show it:

Fig. 1 is a plan view of part of an arrangement LSIs comprising elongated bipolar transistors;

FIG. 2 shows a section along the line 2-2 of FIG Fig. 3 is a section along line 3-3 of Fig. 1;

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Pig. 4-12 cuts, which show the step-by-step production of an LSI structure according to the Pig. 1-3 illustrate;

Pig. Figure 13 is a plan view of part of an assembly of square LSI containing bipolar transistors;

Pig. 14 is a section along line 14-14 of Pig. 13;

Fig. 15 is a section along line 15-15 of Fig. 13; and

16-25 sections which illustrate the step-by-step production of an LSI structure according to FIGS. 13-15.

Figures 1-3 show a section from an LSI in which an arrangement of bipolar transistors is installed which have been produced by the method according to the invention. The transistors are called NPN transistors shown. Of course, the method according to the invention is also applicable to the production of PNP transistors applicable. In Fig. 1, two transistors are shown completely and four more partially shown, wherein each of the transistors within a large elongated

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outer rectangle 10 is included. In each large rectangle 10 there is a smaller, elongated inner rectangle 12 concentrically. The ring-shaped area Ik between the two rectangles 10 and 12 represents the tolerance range within which the openings of the mask structures for the various dopings to which the transistor is subjected must lie.

Each ring-shaped area Ik represents the delimitation of a permanent mask on which further special masks, which serve to mask different sections of the area delimited by the inner rectangle 12, are superimposed. The entire area within the inner rectangle 12 defines the area of the semiconductor or the substrate which is subjected to the first doping, while other parts of the rectangle 12, which remain unmasked one after the other, define the areas for doping which are carried out after the first doping . In particular, the annular area Ik is formed from a selected coating of silicon nitride, and the portions of the area within the inner rectangle 12 are masked by a selected manufacture of silicon dioxide therein.

The width of the inner rectangle 12 is "S" and its length is divided into nine equal parts from each of which has a length equal to the dimension "S".

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The large rectangle 10 has a distance from the narrower rectangle 12 which is equal to the dimension "S" is. All large rectangles 10 are one below the other, i.e. with respect to the neighboring large rectangles 10,. separated from each other by the same distance in both the longitudinal direction and the lateral direction, the is equal to dimension "S". The dimension "S" corresponds to the smallest for positioning tolerances practical level, which in the current state of the art is 2.5 ^ / u (0.1 mil.). The meaning of the dimension "S" becomes clearer as the description proceeds in the manufacture of the transistor.

According to FIGS. 2 and 3, the comprises bipolar transistors built LSI a substrate 16 or a body of semiconducting material, which in this case P-type silicon is. The substrate 16 contains a multiplicity of transistors 17 »which by means of different dopings have been built up within different areas of the substrate 16.

In a first step, a collector 18 is formed within the substrate by N-doping. this will by applying a permanent mask 20 made of silicon nitride in the annular region IM and then overlay a second mask made of silicon dioxide

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the permanent mask "20 and parts of the substrate 16 accomplished, so that only one rectangular opening remains concentrically within the rectangles 10 and 12. This first rectangular opening is shown in Pig «I by a horizontal line between points 1 and 5» a vertical line between points 5 and 6, a horizontal line between points 6 and 15 and one vertical line between points 15 and 1 shown.

In a second step, a base region 22 is formed within the collector region 18 by P-doping. This is done by overlaying a mask made of silicon dioxide Done over the permanent mask 20 and portions of the substrate 16, a rectangular Opening between points 2, 5, 6, 9 and all areas of the substrate 16 between the large rectangles 10 remain open. The rectangular opening is indicated by a horizontal line between points 2 and 5 »a vertical line between points 5 and 6, a horizontal line between points 6 and 9 and a vertical line between the .Points 9 and 2. In addition to the P-doped base area 22, this P-doping creates an isolation region 24 of the P-type, which surrounds each transistor 17-.

In a third step, an N-type emitter region 26 and

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within the collector region 18, an (N +) -type collector contact region 28 trained. This doping is permanent by superimposing a mask of silicon dioxide on top Mask 20 and parts of the substrate 16 accomplished, with a rectangular opening between the points 3 »4, 7,8 and another rectangular opening between the Points 1, 11, 13 »15 is left over. A rectangular opening is created, for example, by a horizontal one Line between points 3 and 4, a vertical line between points 4 and 7 »a horizontal line between points 7 and 8 and a vertical line between points 8 and 3.

Finally, ohmic metallic contacts are attached to the collector 18, emitter 26 and base regions 22, respectively.

By depositing metal on the collector contact area 28, a collector contact 30 is attached to the collector area 18, an emitter contact is attached to the emitter area 26 on the emitter area 26 and a base contact 34 is attached to the base area 22 on the base area 22. The Ohm ¹ see metallic contacts with the collector 18 ,. the emitter region 26 and the base region 22 of the substrate 16 ′ are produced by superimposing a silicon dioxide contact mask over the permanent mask 20 and the entire surface of the substrate 16. The square surfaces 36, 38 and 40, which are each part of the collector contact area. 28, the emitter region 26 and the base region 22 are formed in that both

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in the permanent mask 20 as well as in the silicon dioxide contact mask corresponding sections are left open. The silicon dioxide mask is shown in FIGS. 2 and 3 identified by the reference number 42. In the pig. I are the surfaces 36 or 38 or 40 also with the letters C or E or B marked to indicate where the contacts for the collector, the emitter and the base • are attached are.

Looking at Figures 1 and 2 in the direction from left to right, it can be seen that a distance from the Size "S" is provided for the doped isolation region 24. For the distance of the isolation area 2.4 from the Collector contact area 28 and for the collector contact area 28 itself is also the size "S". Furthermore, the collector contact area 28 is of the Base region 22 and base region 22 separated from emitter region 26 by a distance of size "S". In the end the emitter contact 32 itself has the size "S" and has opposite the edge of the emitter region 26 a distance of the size "S". A distance of "S / 2" is between the innermost Edge of permanent mask 20 and the innermost edge of silicon dioxide mask 42 are provided to a tolerance range to be provided for incorrect positioning of the masks.

According to Fig. 3, the dimension "S" for the emitter contact 32, the distance between the insulation area 24 and

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Base area 22 and the isolation area 24 itself are provided. The isolation area 24 and the collector area 18 can overlap without adverse effects.

With the aid of FIGS. 4-12, the invention will now be described step by step Manufacturing method of the transistor 17 described «According to Fig. 4, on a, e.g. with boron, P-doped substrate 16, a permanent mask 20 made of silicon nitride is applied. Preferably the permanent one Mask 20 made by the photolithography process well known in semiconductor technology,

According to this technique, an approximately 400 to 500 S thick silicon dioxide layer is first formed on the semiconducting surface and then a continuous silicon nitride layer is applied to this. The silicon dioxide layer will required for electrical stabilization of the semiconducting surface made of silicon, since the silicon nitride when deposited directly on the silicon substrate, it tends to exchange charges with the silicon. the Silicon nitride layer is made by reacting silicon tetrachloride (SiCl.) With ammonia (NH,) to silicon nitride (Si NJ is formed. This releases hydrogen chloride gas as a by-product. The thickness of the silicon nitride layer is about 3000 S.

The silicon nitride layer is made of a 500 S thick silicon

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lizlumdloxldschicht and this covered by a photoresist. The photoresist is patterned and then used as a mask to etch the silicon dioxide. The silicon dioxide then serves as a mask for the etching of the silicon nitride with hot phosphoric acid The silicon dioxide layer, which is now exposed, is etched away with buffered hydrofluoric acid.

The next steps include fabricating various masks from silicon dioxide for a selected doping to fabricate the collector 18, base 22, and emitter regions 26. According to FIG. 5 , the substrate 16 and the permanent mask 20 are covered with a continuous silicon dioxide layer 42. The silicon dioxide layer can be grown thermally by heating the substrate 16 in an oxygen atmosphere saturated with water vapor. In order to obtain a silicon dioxide layer 42 with a thickness of 2000 Å, the substrate can be ^{heated at a temperature of 900 °} C. for approximately one hour. As a result, the thickness of the silicon dioxide layer on the silicon nitride layer is only a small fraction of the thickness of the silicon dioxide layer which is formed on the bare silicon.

With the help of a photolithographic masking and etching technique, which is similar to the technique described above, sections of the silicon dioxide layer 42 are

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range of the substrate 16, in which the doping to Formation of the collector area to be made is removed. According to FIG. 6, the silicon dioxide layer remains 42 in the areas in which no doping is to be carried out. The process stage shown in FIG. 6 1 corresponds to the arrangement of a silicon dioxide mask superimposed on the permanent mask 20, the edges of which a rectangular opening between points 1, 5 »6 and 15 form. The silicon dioxide layer 42 is etched with buffered hydrofluoric acid. During this etching process the silicon nitride layer remains unaffected because it is selectively inert to hydrofluoric acid.

FIG. 6 also illustrates the next process step, namely the N-doping of the P-type substrate 16, which is shown as the (P-) area around the collector area 18, which defines the dimensions of each transistor 17, to train. The collector region 18 can, for example, either by thermal diffusion of arsenic into the semiconducting Substrate 16. or by implantation of phosphorus (III) ions into the substrate 16 and subsequent thermal distribution of the foreign atoms are produced .. The ion implantation has certain advantages, since the concentration of the foreign atoms is more even and better 'controllable over the whole area.

After the formation of the collector area 18 is left one

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further silicon dioxide layer 42 grow on the substrate 16 in order to cover this according to FIG. 7. Thereon portions of the silicon dioxide layer 42 are removed in order to define the areas in which the next doping to produce the base region 22 is to be carried out. This stage of the process is shown in Fig. 8 and corresponds in FIG. 1 to the arrangement of a silicon dioxide mask over parts of the substrate 16 and inside the inner rectangle 12, a rectangular opening zv / ischen the points 2, 5 * 6 and 9 and the entire area between the large rectangles 10 that is not covered by the permanent mask 20, remains free.

The next step in the process is converting a Part of the N-doped collector region 18 in a P-doped base region 22 and the design of a P-doped insulation region 24 within the (P -) region of the substrate 16, so that the insulation region 24 surrounds the transistor 17. This is due to thermal Diffusion of P-type foreign atoms such as boron made.

After the base region 22 and the insulation region 24 have been produced, a further silicon dioxide layer 42 is formed formed on the substrate 16 and covers it (Fig. 9) .. Then parts of the silicon dioxide layer

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removed to the areas in which the subsequent doping for the production of the emitter area 26 and the collector contact area 28 are to be made. This shown in FIG In FIG. 1, the method stage corresponds to the arrangement of a silicon dioxide mask over the permanent mask 20 and parts of the substrate 16, so that a rectangular opening between points 3, 4, 7 and 8 and another rectangular opening between points 1, 11, 13 and 15- remains free.

Fig. 10 also represents the next process stage, namely the N-doping, for example with arsenic or phosphorus, around the emitter region 26 within the P-doped Base area 22 and the (N +) collector contact area 28 within the collector area 18.

According to FIG. 11, after the emitter region 26 and the collector contact region 28 have been produced, the substrate 16 is covered with a further silicon dioxide layer 42. Areas of the silicon dioxide layer "42" are then removed in order to define the areas in which the ohms ¹ see contacts to the collector, the base and the emitter are established by applying a metal. N +) - collector contact region 28, the emitter region 26 and the base region 22 holes in

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of the silicon dioxide layer 42. Metallic contacts are made in these holes, which act as collector contacts 30, emitter contact 32 and base contact 34 are. The metallic contacts can extend over the silicon dioxide layer 42 in the form of Strips or ribbons extend to form various desired paths of communication between them.

As an example, typical values of resistance, the depth of the junction area and the concentration of the Premdatome be given now on the surface: The resistance of the substrate 16 is at a concentration of 2 χ 10 ■> Borfremdatomen per cm. 3 Cl per cm. Due to the first doping, the connection area between the N-doped collector region 18 and the (P -) region of the substrate 16, measured from the surface of the substrate 16, lies at a depth of 4.2

10 cm · The sheet resistance of the N-doped collector region 18 is at a surface concentration "of 1.8 10 ¹⁸ foreign atoms per cm ³ 88 Π / D *.

As a result of the second doping, the sheet resistance of the P-doped base region 22 and insulation region 24 is equal to 1% per surface, the connection surface being at a depth of 1.9 × 10 cm, measured from the surface of the substrate 16. The surface concentration is 1.5 x 10 ^ boron atoms per cm ^. As a result, the third doping of the surface resistance is of

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N-doped emitter region 26 and (N +) - collector contact region 28 4.2 ITvO. The manufacturability will improved when the permanent mask 20 is not used to form the edges of the metal contacts. This leaves more space between the interface and the metal, creating larger diffusion anomalies of the metal to be admitted into the silicon. The parasitic collector resistance can through Relocation of the collector contact 30 from the side opposite the base contact 34 to the edge of the transistor 17 «The depth of the connecting surfaces from the surfaces is 1.4 χ 10" ^ cm and

21 3

the concentration 1.5 x 10 foreign atoms per cm.

The P-doped isolation areas 24 are required to isolate the individual transistors 17 from one another. If the P-doped isolation regions 24 are omitted, the lightly doped P-regions contain at the Places where the isolation areas 24 are left out usually a thin surface layer with N-conductivity, which leads to the formation of conductive channels between the transistors 17. The P-doped Insulation layer 24 prevents the formation of such conductive channels. '.

The material for the permanent mask 20 is preferably here: Silicon nitride used. There are also suitable

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other materials which are relatively inert to the substance corrosive to the silicon dioxide. Such materials can include zirconium dioxide (ZrO) or aluminum oxide (Al ₂ O).

The thin, elongated transistor structure described above has a good property of being very small Size. However, in some cases one may prefer to use some of the space savings against an improved one To sacrifice working methods and manufacturability. A transistor structure with the two modifications mentioned above and their manufacturing method will now be described with reference to FIGS. 13-25. For simplicity is only one transistor 48 is shown and the manufacture of the Isolation areas are only explained in general and not in detail. According to FIGS. 13-25, a permanent Mask 50 made of silicon nitride on a P-type semiconducting Substrate 52 applied. The permanent mask 50 is annular and essentially square everywhere. Instead of one, however, it has two openings 54 and 56 which are approximately in Form an "8" are arranged. One opening 56 is wider than the other opening 54.

17 is over the substrate 52 and the remaining Mask 50 is a continuous layer 58 of silicon dioxide upset. The silicon dioxide layer 58 is then etched away in areas as shown in FIG. 18 in order to form the substrate 52 for the

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Prepare first endowment. Remain for this endowment both openings 54 and 56 of the permanent mask 50 uncovered, and an N-doping is carried out, so that the two areas below the openings 54 and 56 merge into a single N-type collector region 60.

The substrate 52 and permanent mask 50 are then created again covered with a silicon dioxide layer 58 (Fig. 19), and the silicon dioxide layer 58 then becomes the Etched again preparation for the second doping. Referring to Fig. 20, the second doping is P-type to one Base area 62 below the larger opening. 56 to train, while the smaller opening 54 remains masked. The isolation region is also preferably used during this doping 64 of the P-type surrounding transistor 48 is made.

According to FIG. 21, in the next method step a further silicon dioxide layer 58 is grown and then etched in order to prepare the third doping according to FIG. 22 '. The third doping is of the N-type and produces an N-doped emitter region 66 by masking one half of the larger opening 56 within half of the P-doped base region 62, as is shown more clearly in FIGS. Furthermore, an (N +) type collector contact area 68 is created by the un-

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masked smaller opening 5 ^ made.

Figures 23-25 illustrate the location and manufacture the metallic contacts for the elements of transistor 48. This process includes fabrication a further silicon dioxide layer 58, the etching of which, to form matching surfaces with the collector, the base and the emitter area and the attachment of the metallic contacts in these holes. 25 shows a collector contact 70, an emitter contact 72 and a protective silicon dioxide layer 74. The one not shown The base contact is attached in the area marked with the letter B in FIG is. The areas marked with C and E mark the location of the collector contact 70 and the emitter contact 72.

Claims ;

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Claims (1)

Patent claims 1 ») Process for the production of a bipolar transistor in an integrated circuit, characterized in that it comprises the following process stages: a) producing a permanent mask (20; 50) from a ' Layer of a first masking material, which has an opening (12; 5 ^ »56) of a predetermined length and width defines, on the surface of a semiconducting substrate (16; 52) of a first line - type of tongues; b) first doping with prematerials of a second conductivity type through the entire opening of the permanent mask (20; 50) to a first area (18; 60) of a second type of conduction within the substrate (16; 52) to form; c) superimposed on a first mask made of a second masking material (42; 58) Over the permanent mask (16; 52) and masking a partial area of the opening (12; 5 ^, 56) of the permanent mask (20; 50); d) second doping with a foreign substance of the first conductivity type through the unmasked surface part of the 409849 / 07U opening (12j 54, 56) of the permanent mask (20; 50), around a second region (22; 62) of the first conductivity type within the first region To form (18j 60); e) superimposing a second mask of the second masking material (42; 58) over the remaining one Mask (20; 50) and masking another part of the opening (12; 54, 56) of the permanent mask (20; 50), with a surface part that is smaller than the second area (22; 62) within this area (22; 62) remains unmasked; and f) third doping of an impurity of the second conductivity type through the unmasked surface part of the opening (12; 54, 56) of the permanent mask (20; 50) around a third region (26; 66) of the second conductivity type within the second region (22; -62). 2. The method according to claim 1, characterized in that the permanent mask (20) has an annular shape a single, elongated and rectangular opening (12) arranged centrally therein. 3. The method according to claim 1, characterized in that the permanent mask (50) has an annular shape in The shape of an "8" with two rectangular openings (54, 56) arranged next to one another is given. A09849 / 07U iJ. Method according to claim 1, characterized in that that the first masking material is silicon nitride and the second masking material is silicon dioxide « 5. The method according to any one of claims 1, 2 and ^ l, characterized characterized in that it comprises the following process steps : a) Application of a permanent mask (20) made of a layer of silicon nitride, which is a rectangular Defines opening (12) with a width S and a length 9S, the rectangular opening (12) in nine square areas of the same area, which are arranged in sequence and as zones 1-9 • be continuously marked, divisible, on the surface of a semiconducting substrate (16) of a first conductivity type; b) first doping with an impurity of the second conductivity type through all nine zones of the rectangular ones Opening (12) to a collector region (18) of the second conductivity type within the Forming substrates (16); c) Masking zones 1 and 2 of the rectangular opening (12) by applying a layer of silicon dioxide to the corresponding areas of the surface the substrate (16); 409849/0714 d) second doping with impurities of the first conductivity type through zones 3-9 of the rectangular ones Opening (12) around a base region (22) of the first conductivity type within the collector region (18) to form; e) Masking the zones 2, 3 »8, 9 of the rectangular opening (12) by applying a silicon dioxide layer on the corresponding areas of the surface of the substrate (16); f) third doping with impurities of the second conductivity type through zones 1, 4, 5 »6 of the rectangular Opening (12) to a collector contact area (28) of the second conductivity type within the collector region (18) and an emitter region (26) of the second conductivity type within the base region (22) to form; g) Masking zones 2, 3> ^ »6, 7» 8 of the rectangular ones Opening (12) by applying a silicon dioxide layer to the corresponding areas of the surface the substrate (16); and h) Application of metal through zones 1, 5, 9 of the rectangular opening (12) to make metallic contacts at the collector contact (28), emitter (26) and base area (22) to form. 409849 / 07U 6. The method according to claim 5 »characterized in that the semiconducting substrate (16) silicon from P-type is used and an N- or P- or N-doping as the first, second or third doping is carried out. 7 «Method according to claim 5», characterized in that a doping with foreign substances of the first conductivity type In an area (24) with the width S, which surrounds the permanent mask (20), made is to obtain an Xsolationsberelch (24). 8. The method according to claim 7 »characterized in that the doping is carried out simultaneously with the second doping is made by foreign matter. 9. The method according to any one of claims 1, 3 and 4, characterized in that it comprises the following process steps : -. a) Making a permanent mask (50) which defines a rectangular "8", with a rectangular Opening (56) is wider than the other rectangular opening (54), on the surface of a semiconducting Substrates (52) of a first conductivity type; b) first doping with an impurity of the second 409849 / 07U Conductivity type through both rectangular openings (5 ^, 56) to a collector area (60) to manufacture; c) masking the narrower (54) of the two rectangular openings (54, 56) J d) second doping with an impurity of the first conductivity type through the wider (56) of the rectangular openings (54, 56) around a base area Forming (62) the first conductivity type within the collector region (60); e) masking approximately half of the area of the wider opening (56), measured in the longitudinal direction will; and f) third doping of the second with an impurity Conductivity type through the unmasked half of the wider rectangular opening (56) to one Emitter region (66) of the second conductivity type to form within the base region (62) and through the narrower (54) of the rectangular openings (54, 56) around a collector contact area "(68) of the second conductivity type within the collector area (60) to form. 10. The method according to claim 9, characterized in that the permanent mask (50) by application and etching 409849 / 07U a silicon nitride layer is produced on the semiconducting substrate (52) « 11. The method according to claim 10, characterized in that that the rectangular openings (54, 56) by superposition masked by silicon dioxide layers over the permanent mask (50) and then selectively Etching of the silicon dioxide layers is carried out. 12. The method according to claim 9 »characterized in that that metallic contacts are attached to the collector contact (68), base (62) and emitter area (66) . 13. Bipolar transistor for integrated circuits, characterized in that it contains the following features: a) a substrate (52) of a first conductivity type; b) a mask (50) on the substrate (52), which * the Figure a rectangular "8" with a rectangular one wider opening (56) and a rectangular narrower one Has opening (54); c) a collector region (60), which by doping impurities of a second conductivity type in a Volume of the substrate (52), which coincides with the two rectangular openings (54 »56), 409849 / 07U 2419818 is set; d) a base cover (62) which is produced by doping premd materials of the first conductivity type into a volume of the collector region (60) which corresponds to the wider opening (56) of the rectangular openings (5 ² J, 56); e) an emitter region (66), which by doping of - Foreign matter of the second conductivity type is produced in a volume of the base region (62) which corresponds to half the area of the wider opening (56) of the rectangular openings (5 ¹ J, 56); and . f 1st a collector contact region (68) by doping impurities of the second conductivity type in a volume of the collector region (60) which * i _t with the narrower opening (5 ¹ O of the rectangular openings (5 56) coincides prepared) · 14. Transistor according to claim 13 »characterized in that that the mask (50) consists of silicon nitride, 15 · Transistor according to claim 13 »characterized in that it has metallic contacts on the surface of the collector (60), base (62) and emitter area (66) 409849/0714 16. The transistor according to claim 13 »characterized in that the semiconducting substrate (52) made of P-type silicon and the collector (60) or the base (62) or the emitter region (66) of the N-type or P-type and N-type, respectively. 409849 / 07U