DE2554775A1 - Digital control system for heavy goods vehicle - has programmed central memory coupled via four:line bidirectional data bus to control modules coupled to main interface unit - Google Patents

Abstract

The digital control system is used for heavy road vehicle systems where separate computing modules are used for fuel injection, ignition etc. The programmed central memory is coupled to a four line bi-directional data bus. Each computer control module is connected to the bus. An additional bus line provides a status check on which unit is tied to the bus at any instant. All control modules are coupled to a main interface unit providing A/D, D/A conversion etc. The system processing is executed on a byte basis. System operation proceeds with priority assigned to a pre-programmed condition.

Description

Operational or work flow influenced the facility

Rlnzelachner, namely so-called single-purpose computer, which only too completely are capable of certain services. Such mini-calculators are fixed in their structure wired and often include an integrated circuit, with aer today being advanced Miniaturization in this area of the vesar..te computer as a component the form of a so-called. "Computer chips". To control the number assigned to the respective Pechnercliip Process flows receive this data and information, often in analog form, about the respective operational status of the facility or

of the sub-area monitored by it; the computer also needs then information about facility-specific data that is stored in Form are available. By supplying this facility-specific data, the Computer chip capable of control or regulation processes with the same internal structure to arrange for the part of the facility assigned to him, the specifically are correct and applicable for this institution; i.e. in other words that a single-purpose computer of the same structure with many different directions can be used if it is provided with data values that can be used for this respective facility are specific and which he can call up when required can.

It goes without saying that "on-chip" storage of these device-specific Data is impractical, as this requires a change in the computer chip would and a large number of programming required on the individual computer chip would be.

External storage with the help of a central one is therefore expedient Main memory, which is then usually used as read-only memory or programmable read-only memory, thus designed as ROM (= read only memory) or as PROM (= programmable read only memory) is. Since, as already mentioned earlier, it is expedient one A large number of such individual computer chips or fin-purpose computers in one facility are used, in which under certain circumstances very different procedural and Process sequences are to be controlled, it is necessary for a perfect understanding between deiii. respective single-purpose computers and the one central main memory to ensure that the data exchange or data transfer between the main memory and the large number of single-purpose computers run smoothly and sufficiently quickly walk.

On the other hand, in this context it is desirable that in particular The effort for the data transfer can be kept as low as possible, i.e. that As few connections as possible are to be established with effective wiring.

The system described so far becomes more conceivable if this considered for a specific application, what follows using a special Embodiment is carried out for the operation of a motor vehicle, wherein However, it should be pointed out that the inventive. Jata transmission system can also be used successfully in any other application, provided a plurality of process series controlling computers from a central main memory should be served.

If one assumes the operation of a motor vehicle, then this results the need to control or regulate a variety of process flows that very often unrelated to each other and for separate single-purpose computers can be used, which then as a whole part of central electronics in the motor vehicle are. It is particularly advantageous that, if necessary, additional computers without Difficulties can be connected to which then also the one central i1 main memory with the now vehicle-specific data for disposal stand. As process sequences that control or regulate in a motor vehicle require, for example, the ignition, in particular the determination the ignition point, the supply of the fuel to the combustion chambers of the cylinders, preferably by an electronic fuel injection system, the control of the Gear change process with an automatic transmission, climate control inside the Motor vehicle, if there is an air conditioning system or others, in their process Operations and processes that are dependent on the respective operational events of the motor vehicle.

In all of these control processes, single-purpose computers can be used to great advantage in the form of computer chips are used, which are unchanged for all motor vehicles can be designed and built, particularly in the case of larger series favorable production costs result. There is then a need to be vehicle-specific To store data externally, for which the central electronics ijber a PO or PROM; such a central electrical system should then also be used in other motor vehicles only the programming of the central main memory needs to be changed to become. Such an external data storage also makes the Inexpensive supply of]; smaller series with a high-precision working Central electronics possible, test vehicles can still be carried out in a simple manner to be sampled.

The present invention is based on the object of a method and a data transmission device, in other words, a data transmission system to create what for a fast and trouble-free connection of the individual Single-purpose computer to the central main memory of the central electronics.

To solve this problem, the invention is based on the cin-C "-angs named method and according to the invention consists in that before addressing of the memory by the single-purpose computers connected to the common bus line a priority control determining the access to the memory carried out and the bus line is blocked by occupying a separate occupancy line (busy line) is that then from the computer with priority the address of each stored data value to be queried depending on the number of existing bus lines in binary partial word packets is given serially to the memory that after access the determined data value also in the same parallel series packet formation from the memory is fed to the computer and that the occupancy of the busy line is then released is, with all individual steps by a central clock control in your Sequence are determined.

In the invention it is particularly advantageous that in this way all data to be saved in the respective system are summarized in a read-only memory and that the data transfer between this read-only memory, so the central Main memory and the respective individual computers is systematized so that one any system composition is possible.

It is also particularly advantageous that the data transmission system according to the invention, which can also be referred to as an interface circuit "can be designed in this way it is possible that the computers with the highest priority can each be served first; on the other hand, the data transmission system can also be designed so that from Save all computers in faster cyclical sequence it is queried whether there is a need for the transmission of vehicle-specific data for each individual computer. If the single computer answers this question in the affirmative central main memory, nn an additional document line is activated or in brought the state log 1 and the data transfer can take place.

Further refinements of the invention are the subject of the subclaims and laid down in these or can be derived from the description given below refer to the structure and mode of operation of exemplary embodiments in memory using the figures are explained in detail. The figures show: FIG. 1 a schematic diagram the connection between the individual computers and the central main memory, Fig. 2 is a block diagram of that part of the memory page Transmission system, FIG. 3 shows the block diagram of FIG. 2 in a detailed representation, Fig. 4 is a block diagram of the union on the respective computer side Part of the transmission system, FIG. 5 shows the block diagram of FIG. 4 in more detail Representation, Fig. 6 including the timing of the data transmission the priority allocation to the respective computer in the form of time diagrams, Fig. 7a shows the detailed circuit structure of a data transfer controlling the sequence -7d Counter and its functional sequence, 709824/0860 Fig. 8 is another Embodiment to illustrate the distribution of priorities in the data transmission system.

9 shows the timing diagram of the time sequence on the computer side.

Fig. 1 shows the structure of central electronics, especially in one Motor vehicle. The central electronics include a number of computers 1, 2 ... n-1, n, the specific control tasks for the operation of a motor vehicle meet and over a single common connecting line 5 with a single central main memory G are connected. In the embodiment shown in FIG the connecting line 5 comprises four information lines INFO and an additional one Busy line, referred to below as the busy line. Immediately upon it pointed out that basically any number of individual connection lines, so INFO lines can be used. For technical reasons The number of INFO lines is limited, however, because each line requires on each computer an additional connection terminal or a connection pin, the number of which of importance for the manufacturing costs of such a device, which should not be underestimated Transmission system are. The present transmission system of Fig. 1 works with 8-bit words, this means that normally those from the respective n computers 1, 2 addresses to be transmitted to the main memory 6 comprise 8 bits, out of 8 bits also exist the data values transmitted from the main memory 6 to the single-purpose computers, which they need to carry out certain arithmetic operations. Hereinafter The term 1 byte is also used instead of the term 3 bit.

For a better understanding of the transmission system, the following first of all a basic operating principle of such a single-purpose calculator and its relationship to the main memory 6 explained in more detail, with the main computer for reasons of expediency for gasoline injection is described, although of course even any other computer in this or another form according to the one described below Principle works.

The representation of Fig. 1 can be seen, <leave the computers a block 7 is connected upstream, which this with the respective, for the given operation operating status data available at the time. At the petrol injection calculator it can be an analog signal that tells the computer that the internal combustion engine to be controlled in its process sequence is approximately idling is located (an idle switch operated by the accelerator pedal may be closed), at the same time, the main computer receives information for the fuel injection about the current temperature of the internal combustion engine, for example by scanning the cooling water temperature. From these two and possibly others, below Analog information called status signals must be used by the main computer for the Petrol injection, with simultaneous consideration of the speed of the separating engine develop a pulse train which is fed to the injection valves of the internal combustion engine and where the duration of the individual impulses is the duration of the opening times of the Injectors determined. As already mentioned at the beginning, it is from a technological point of view Reasons inexpedient to provide chip-internal storage for each computer, which could transmit a corresponding data value to the computer, which during the generation the fuel injection pulses could be processed. It is therefore with the present Embodiment proceeded so that, for example, the Jlauptrechner 1 for the Fuel injection an address from the two status signals received compiles (dics can also run a separate address calculator), this Address is to be described in more detail below and to be determined Times are transmitted to the main memory 6, which has a vehicle-specific address corresponding to this address information The one data value in forest of an 8 bit first location the Pechner transfers back.

It is clear that due to the fact that only one Connection line 5 is provided, with which s: -all computers connected in parallel are, the respective connection through main memory G / computer n within a period of time during which the other computers are not using the main memory 6 and must also be prevented from establishing a connection to be able to take.

closer to discussing such a data transmission system first of all to deal with the concept of priority, by which it is determined when and under what conditions a computer contacts the main memory 6 can take and make a data transfer.

There are several possibilities within the scope of the invention Establishing and establishing contact between the computer and the main memory 6 provided, but it is useful to begin with the following using the illustration 2 shows the basic structure and mode of operation of a data transmission system to be explained before any other options for priority access to be discussed between computer and memory; this will be discussed further below to be discussed in detail with reference to FIG. 8. At the present time it is only pointed out that there are other possibilities of memory access, in order to prevent incorrect double assignment of the connection line 5.

In the following in connection with the illustration of FIG The memory access described is one from the main memory 6 itself certain contact between computer and memory in such a way that the main memory 6 cyclically polls all computers 1, 2, n connected to it and offers memory access; one of the computers requires information the main memory f, we can establish the connection and the occupancy of the 1 Connection line 5 blocked for all other computers, at the same time the cyclic one Interrogation of the other computers by the main memory 6 itself is interrupted. Here computers with the highest priority can be given preference.

Before the embodiment of FIG. 2 is discussed in more detail, it should be noted that the data transmission system according to the invention is based on a connecting line 5 is described, which consists of four individual lines INFO 0 for data transmission as well as a BUSY document line.

Of course, as indicated briefly above, also more or less than four lines INFO or drains possible, in particular If the wiring capacity is low, a two-wire bus is advisable.

If four shower lines and one BUSY line are used, then the data transmission system works in such a way that after clarification of the priority on the four INFO bus lines initially the first half of the address, i.e. a 4 bit word resp.

1/2 byte is transferred, the next clock period becomes the second Half of the 8 bit word of the address transmitted; then leads in the next bar or in the next step the main memory has its access and transfers during the next two clock steps serially each a binary half-word packet, in the present case Embodiment consisting of 4 l) it or 1/2 byte. rTan therefore needs how will be explained in detail further below, in the case of a five-line bus only 6 basic clock cycles for memory access, compared to a two-line bus where significantly more basic clocks are required for the data transfer and therefore also the contact period between one of the single-purpose computers and the main memory 6 is considerably extended.

T.C already mentioned at the beginning, takes place in the following first The exemplary embodiment to be discussed based on Fig.

the distribution of memory accesses cyclically, whereby the memory itself before the actual data transfer, i.e. before the transfer of the ac'ressc land of mediated data values determines the individual computer, which with it to a predetermined Time should come into contact, but not necessarily.

For this purpose, the main memory 6 has a sequence control circuit 8, which can be designed, for example, in the form of a counter in cyclic Sequence at its three outputs Ql, Q2 and n3 a binary consisting of 3 bits Word generated, which can be used as a basis for computer identification. As can be seen can if the 3-bit counter on which the sequence control circuit is based is in the usual tteisc, fed by a.

Basic clock fo circulates, eight different identifiers are generated, so that in this embodiment eight different single-purpose computers, if desired, can be connected cyclically with the main storage unit rather 6. Each 3 bit-full word (according to a computer knowledge, either directly on three of the connecting lines, for example on the bus lines a, 1), c or the outputs Q1, Q2 and Q3 of the sequence control circuit 8 are initially one Priority decoding circuit 9 supplied, the priority code according to their coding generated for the respective computer controlled via the bus lines a, b and c. The output of the priority decoding circuit is applied to a transmission register on the input side 10, which can be switched clock-controlled. At the time of memory access distribution the transmission register 10 is connected so that the bus lines a, b and c with the Outputs of the priority decoding circuit 9 are connected, so that at every clock on the bus lines a, b and c a new one to the cyclically circulating counter reading the Sequence control circuit 8 declining computer identifier leigt. On the computer side, this identifier is taken from the. Calculator for which it is intended in each case is recognized and the respective computer 1, 2, n may occupy the return line or document line BUSY, whereby the sequence control circuit 8 is stopped in this position and is held. r. it goes without saying that the entire process is therefore clock-controlled and must be synchronized.

As soon as the respective addressed computer 1, 2, n by occupancy the line BUSY has stopped the flow of the sequence control circuit 8, arrives the first 1/2 eyte of the address to and from the bus lines a, b, c, d a receiving circuit 11; after a further step, the second will also be Half of the address, i.e. the last 1/2 byte, is transferred to the receiving circuit 11. for precise address formation, the transmitted address can also be; another one of the Signal derived from punch detection, namely corresponding to the outputs Q1, Q2, Q3 can be added to the sequence control circuit, whereby the main computer 6 knows which Pedlncrr is connected to him and the address in the correct memory compartment got.

A memory clock circuit 12 is provided for the clocked data transfer, which generates a cyclical signal at its outputs JO - J5, whereby the process of the data transfer is controlled. Received from the receiving circuit 11 the entire 8-bit address is then transferred to the actual read-only memory 13, the one this address corresponding data value to the transmission circuit 10, which then, controlled by the clocks j4 and J5 of the memory clock circuit 12 the asc determined Data word in two half-word packets on the INFO connecting line. Perpetually all this time, the BUSY line is busy and a connection is established other computers are not possible because the busy BUSY line takes longer to respond computer as a result of blocking the sequence control circuit. When the data transfer is finished, the line is released again and further identifications are cycled through starts again.

The block diagram of FIG. 2 is shown in more detail in FIG. 3 explained, the individual skirts being bordered by dashed lines.

For priority distribution or for computer access control included the! \ hlaufsteuersehaltung 8 of the 3lock circuit diagram of FIG. 2 has a counter 14 which the priorities one after the other. The counter 14 is a 3 bit counter switched, Caher appears eight times at its outputs Q1 - Q3 a different one Binary location before the first binary word is repeated; but it goes without saying that the counter 14 can of course be switched so that depending on the number the computer to be connected to the main memory 6 is the cyclical circulation of the counter 14 also to a smaller number of different binary words to be generated can be set before a repetition takes place. For early resetting the counter 14 a comparator logic is provided, which consists of three exclusive OR gates 15, 16 and 17, their lengths with the inputs of a downstream NrSD gate 1 8 are connected, which via a further NAND gate 19 with the Reset input Pr of counter 14 is connected. The other entrances of the exclusive OR gates 15, 16 and 17 are voltage signals from an arbitrary one switchable resistor matrix 20 supplied, which switched in the exemplary embodiment is that each time a certain binary word occurs at the counter output of the The counter is reset to zero and its cyclical sequence is repeated.

The respective output binary word according to the logical states of the outputs Q1, Q2 and Q3 of the counter 14, which is also used as a precedent for priority can be designated, goes to the assigned inputs of the in the lower part of the Fig. 3 shown priority decoding circuit 9, the priority pre-identifier possibly still recoded, but possibly also without change on the output side transmits to a downstream switchover logic 22. Furthermore, the computer identification goes Q1, Q2 and Q3 still to an auxiliary address formation circuit 23, which is derived from the computer identification Q1, Q2 and Q3 in the corresponding desired recoding at their outputs B1, B2 and B3 allows logical states to appear which precede the read-only memory 13 Address summing circuit 24 are supplied, which will be discussed further below will.

but first of all the following results. The from the priority decoder circuit 9, if necessary, recoded computer identification goes to correspondingly assigned inputs a switching logic 22, which is connected to assigned outputs depending on their switching state either the (recoded) computer identifier to a downstream transmission circuit 25 transmits, which is connected on the output side directly to the bus lines a, b, c, d or the outputs of the permanent memory 13 in their other switching state the transmission circuit 25 puts on the bus lines a, b, c, d.

The switching states of the switching logic 22 are determined from the state of the signal on the voucher line or on the BUSY line. Know them Line on the BUSY signal, i.e. 3ttSY "not", is the entire connection line 5 not assigned, then the switching logic 22 is in its first switching state and transmits the possibly recoded computer identifier Q1, Q2, Q3 to the first three bus lines a, b, c. In this case it goes without saying even the transmission circuit 25 in its through-connected state. On the computer side Receiving circuit of the computer identification, which is on the bus lines a, b, c after the the sequence just described occurs cyclically with each clock pulse changing, will be discussed in more detail below, initially it should only be pointed out, that the computer addressed by his: ennuna two needs to establish contact with the read-only memory 13 has the opportunity to seize the line BUSY, thereby the cyclical process of the computer identification. stop the counter 14 and the To bring Umschaltlogil 22 into their other switching state, namely how. from the Representation of FIG. 3 can be seen by supplying the signal BUSY to an input the Umschaltloalk 22. The same signal PUSY comes from the BUSY line c'en input Ci of the counter 14 and stops it. By agreement, that corresponds The BUSY signal has the status log 1 on the BUSY line.

rci of the switching logic 22 can be a simple relay switch act, but aucyh befv @ grated electronic switching gates can be used such as those sold by the CA under the designation 4019 will. The counter 14 is the integrated counter chip 4029 of FIG RCA. The transmission circuit 25 connected downstream of the switchover logic consists of so-called transmission gates of the designation 4016 of the RCA in an integrated design. There are two quadruple transmission gates 25 and 25a provided alternately on the output side are connected to lines a - d.

As soon as the computer identification is on the flusleitunqen a, b, c and a computer then seizes the BUSY line, switches, as already mentioned, the signal Busy also the switchover logic 22 um and prompted over a line 26 with the signal Busy to the reset input 'Reset' one in the form of a feedback shift register formed counter 27, to which in the following 7, the clock-wise sequence control will be discussed in more detail immediately for data transfer. For the rest, the clockwise sequence is based on below of the timing diagram of FIG. 6 is discussed in more detail.

The structure of the counter 27 can be seen in the illustration in FIG. 7a; it consists of a number of bistable flip-flops connected to one another, preferably so-called D flip-flops 28, 29, 30, which are the basic system clock fo for the cyclic Forwarding is supplied and the output of the last D flip-flop over an inverter 31 is fed back to the input. Accordingly, a generated such a counter, known as "Johnson Counter", on his Outputs PO, P1, P2, the sequence of states 1 - 6 indicated in FIG. 7b. These counter states 1. - 6. are via the decoder circuit 100 of Fig. 7c, consisting of a row from NO attern 101-106, decoded. The output signals JO, J1, J2, J3, J4, J5 of the Decoding circuit 100 run through the log 1 state in a cyclical sequence In the present case, output signals JO-J5 are used to control the data transfer process used. Fig. 7d shows a timing diagram of the control signals Ja - J5.

4hrenu of the first cycle time JO of the Johnson counter, as described in the following (available under number 4022 of the RCA) takes place first the resetting to zero of the read-only memory 13 connected upstream in exemplary embodiment 8 bistable flip-flops, via a common return line 32. The flip-flops are each provided with the reference numeral 33 and consist of four separate ones Look integrated circuits under the trade name 4027 of the RCA, with each block containing two so-called J-K flip-flops. With these flip-flops 33 is the receiving register 22 of the read-only memory 13, which is divided into two 1/2 byte packets are supplied with the address from the respective computer and from the flip-flops 33 is made available at its outputs c'em read-only memory 13.

Before discussing the further clock-based control of the data transfer the following should be noted. Each of the computers 1, 2, n generates as required the information to be supplied to him an address, with the computers a specific Area portion in the read-only memory 13 is assigned, in which the for this Correct stored data values are located on the computer. For example, the Computer 1 has 32 memory locations, so the read-only memory can have 32 addresses feed and receive 32 8 bit types as required information. Other calculators have, for example, 16 or only one storage space, wherein the read-only memory 13 itself can be designed, for example, so that it has 256 memory spaces of 8 bits each. As a memory, for example under the designation 1702 from the INTET. Corp. uses available memory will.

If only a single computer is connected to the read-only memory 13, then the address transmitted by the computer can be saved directly to the read-only memory 13 are transmitted; if several computers are calibrated, each one transmits the computer, from its point of view, has addresses O-15 or O-31, where the main memory 6 these addresses, namely the 3 MSB (most significant bit = most important bit) adds an auxiliary address in the present exemplary embodiment so that the from the respective computer also in the correct area of the read-only memory 13 arrives. To this The purpose is the one already mentioned above Address summing circuit 24 is provided; the generation of this "auxiliary" old additional address is not difficult, because the main memory 6 has the computer identification Ql, Q2, Q3 already have a binary word that is only valid for this computer, which, if necessary, it is still recoded via the auxiliary address formation circuit 23 and in the form of outputs B1, B2, B3 to correspondingly assigned inputs of the address summing circuit 24 arrives. The address summing circuit then forms at its outputs S1, S2, S3 the 3 MSB of the "correct" address for this computer, so the address also how already said, in the correct compartment of the read-only memory 13 comes. The remaining 5 LSB are reached directly via switchover logics to be described below to the read-only memory 13. The address summing circuit 24 is an adder available from RCA under the designation 4008, which from the two inputs A1, B1; A2, B2; An, Bn is the sum S1, S2, respectively and S3 educates and makes it available at its outputs.

At the next cycle time of the Johnson counter (J1 = log 1) each of which controls one inputs of NAND gates 35 ', which in the exemplary embodiment first 4 bits of the address that are on the bus lines a, b, c, d, reach the associated flip-flops 33 ', via inverters 36 '.

It should be pointed out again at this point that it is essential The meaning is that the main memory 6 and the respective computer with the same Work cycle, which is due to the forced synchronization via the system basic cycle fo is achieved, which is also the respective sequence control circuits on the computer side, which will be dealt with further below, as already mentioned, is supplied. This Working with the same Tact is also especially important in that Case in which the computer uses the computer identifier assigned to it on the bus lines a, b, c recognizes and with the same clock edge by seizing the BUSY line the priority counter 14 stops. This means that this state is embedded for the system " and the actual data transfer can begin, also controlled by a pulse.

After the cycle time J1 has run alone, the Johnson counter 27 switches to the Clock time J2 around and, as can be seen, correspondingly assigned NAND gates are set 35 switched in such a way that the transmission of the second direct address via this and downstream Inverter 36 is possible. After doing the entire address initially while doing this of the two clock times J1 and J2 into the flip-flops 33 and 33 'and from there to the Read-only memory has been transferred, with the subsequent clock time J3 of the Johnson counter 27 reset via line 38 of priority counter 14; the line 38 goes through an inverter 39 to the other input of the further forward already mentioned NAND gate 19, which is used for resetting.

The priority counter 14 can be reset at this point in time take place, since this special computer identifier is no longer required. Alternatively it is of course possible to set the priority counter 14 to this value and when the BUSY line is switched to the log O state, the count continues to cause. The cycle time J 3 also enables the memory to access the stored Word.

The following two measures J4 and J5 are used to transmit the Data value pending at the outputs D1 to D8 of the read-only memory 13. to At this point in time, the timing logic 22 has anyway because of the state Busy = log 1 switched to the outputs D6 to D8 of the residual value memory 13; by Feeding of the clock time signal J4 via an inverter 40 to a downstream NAND gate 41, the transmission gate 25 is turned on, i. E. the transmission gate transmits the logic states present at its inputs to the bus lines a - d. The transmission gates can be bilateral switches using COS / MOS technology Act. The signal J4 or J5 in the case of the transmission CAT 25a reaches the Gate electrodes, whereby the semiconductor switches switch through. It comes like this during the clock time J4 for the transmission of the first data value half-block, which comprises 4 bits and is present at the outputs DS to D8 of the read-only memory 13. At cycle time J5 finally turns on the transmission gate 25a and transmits the second half of the stored data value via the bus lines a to d. Thereupon then takes the assigned computer returns the assignment of the bus lines and the system is up ready for the next access cycle.

6 shows the timing diagram of the various pulse processes on the memory side of the transmission system; Fig. 6a shows the basic clock of the System, which in an exemplary embodiment can be at 600 KHz; Fig. 6b shows the voltage profile on the BUSY line; Figures 6c to 6e show the Signal processes at the output of the priority counter, their course as a result of the special Coding is not important; It is only essential that at time TO there is such a coding that one of the computers at the same time a There is a request signal for data exchange, the BUSY line is busy, whereupon as a result of the priority counter being locked, the signal outputs Q1, Q2 and Q3 of the Priorities of the counter are retained and at the same time when the BUSY signal is switched the first clock pulse JO begins on log 1; then close in cyclical Follow the other clock pulses according to the course of the signals in Figures 6f to 61; 6m is generated by the computer side of the data transmission system then one last reset or acknowledgment pulse (this will be followed in the following still to be entered); the last two timing diagrams according to the figures 6n and So indicate the times at which the first 4 bits of the address (Fig. 6n) and to which the second 4 bits of the address are stored. These Points in time Ta and Th are formed by the pulse J1. fO or by the impulse J2 In the following, the basic structure of the subcircuit area of the transmission system assigned to each individual computer 1, 2, n or the bus interface circuit. It has already been pointed out that both the individual computers and the main memory 6 have the same basic system clock are acted upon; for the compulsory synchronization of the procedures on both The computer side also has sides of the bus line or connecting line a memory clock circuit 46, which is also designed as a Johnson counter and in the present case has been expanded to include an additional flip-flop element, so that a total of 7 cycle times are generated by the computer. First run in the case of access control or distribution of priorities on the flow lines a, b and c in the exemplary embodiment, the respective computer identifications one per period of the basic system clock; each circuit part assigned to the computer side accordingly 4 has a computer identification decoding circuit 47, when the identifier assigned to this computer on the bus lines a, b and c appears, forwards an output signal to a sequence control circuit 48, which in the presence of a request signal on a line 49 the line BUSY can occupy the logical state log 1 by a busy signal; then arise those already explained in detail above with reference to the main memory Effects.

The computer side of the bus interface circuit can be designed in such a way that that from the respective computer 1, 2, n or from one of these computers in turn assigned Address calculator creates an address if necessary and to inputs X and Y of switching logics 50 and 51 are created. At the same time, the sequence control circuit 48 becomes a request signal zugebeitext, The sequence control circuit 48 occupies, as just mentioned, the Busy line and at the same time sets the Johnson counter via the connection line 52 returns or initiates the generation of the first clock pulse JO, which is therefore at the same time as the pulse JO of the memory clock circuit 12 of the main memory 6.

As you can remember, the J1 pulse of the Johnson counter 27 served the memory side Circuit of Fig. 3 for switching through the first half address, which is therefore on the Bus lines a to d are present. Therefore, the computer-side part of Fig. 4 with the pulse J1 through the first switching logic 51, so that the at the inputs Y addresses present on these bus lines a to d. The next impulse then switches the second switchover logic 50 for the transfer of the second half address.

Accordingly, there are then still for the receipt of the retrieved data information two t3mschaltlogiken 54 and 55 are provided, at their outputs after the clock pulse has elapsed J5 the entire 8-bit flat word from the read-only memory 13 is present.

In detail, the circuit of FIG. 4 looks so that accordingly the illustration of FIG. 5 for decoding the computer identifier at the Embodiment three exclusive OR gates 57, 58 and 59 are provided, whose Inputs the signals on the bus lines a, b and c, according to the cyclically running computer identifier, are constantly fed. The other entrances these exclusive OR gates 57 to 59 are corresponding to the identifier of this particular one The computer is permanently wired, so that only when there is a very specific signal composition on the bus lines a, b, c and with a certain state of the BUSY line in the previous one Basic clock, the signal of which is via a bistable multivibrator, preferably via a so-called D flip-flop 60 is delayed by this basic clock, the decoding circuit 47 for the computer identification and the status "BUS-not occupied" responds and an output signal via one of the exclusive OR gates 57, 58, 59 and the negated output from the D flip-flop 60 downstream NE4D gate 61 outputs. If this output signal is present, then this indicates that the memory page of the data transmission system is ready is to get in touch with that particular computer; the calculator is like that switched so that it answers on the busy line and by applying a logical 1 or a logical 0 informs the main memory 6 whether a data exchange of is desired for him.

For example, is the identifier for the one described in FIG Computers on bus lines a, b and c log 1, log 0, log 1, then the others are Input: inge of the exclusive OR gates to be wired according to log 0, log 1 and log O; in this case all outputs of the exclusive OR gates are in the state log 1. If the BUSY line was now in the previous basic cycle, for example in the log 1 state (i.e., BUS "busy"), it is going to NAND gate 61 The signal on the line 60a is log 0. The output of the NAID gate 61 is thus log 1 and the computer does not take one Contact with the main memory 6 via the BUS line.

If, on the other hand, the BUSY line was in the previous basic cycle, for example in the log O state (i.e. BUS "free"), then the Exclusive OR gates 57, 58, 59 in the above example also line 60a in the state log 1 and at the output of the MAND gate 61 the state log 0 results when this computer-specific identifier is selected from the memory. Via an inverter 65 the output signal identifier <= identifier "not") is sent to an OR gate 62, which actuates a switch 63 on the output side in the simplest case, in such a way that that a signal SK supplied to the switch is transmitted to the busy line and thus indicates the occupancy or non-occupancy of the entire bus lines. This Signal SK depends on the state of a flip-flop 64, which, for example, as JK flip-flop can be formed and a request signal via line 66 5A is delivered by the assigned computer, which indicates whether the computer has a Information needed. The signal generated by a separate address computer the line 66, which can be referred to as the primary request signal, brings the flip-flop 64 into its set with the leading edge of the basic system clock f0 State so that on the output line 68 corresponding to the output O of the flip-flop 64 a request signal log 0, that is, Anfo is present. The signal on signal line 68 is used together with the J6 output of the memory clock generation circuit to be described in more detail later 46 to a NOR gate 67, the output of which is the control signal Sst for the switch 63 forms.

If a request from line 68 is in the state log output from Johnson counter the signal Sst on line state via the switch; assigned computer, so is O and if at the same time the J6-46 is also log O, then log 1 becomes what means that this 63, which in the embodiment expedient a so-called transmission gate or a transistor switch in MOS technology can be transmitted on the busy line. If there is no requirement, then Line 68 in the logic state 1, so that via NOR gate 67 and switch 63 on the busy line a log O is transmitted.

The intervention of the J6 output of Johnson counter 46 through the NOR gate 67 takes place for the purpose that after the data exchange has taken place in the clock phase J6, at which the J6 output is equal to log 1, the busy line is set to log O and thus is marked as clearly not used.

In the case of the request, there are also those with reference to FIG. 4 mentioned input lines X and Y in each case the half words of the address, the computer side The bus interface part therefore opens the transit gate 63 to occupy the line BUSY in principle when the specific computer identifier assigned to it occurs and then leaves, depending on whether there is information and therefore an occupancy of the bus lines is required, seize the BUSY line. This occupancy must be used throughout Data transfers are maintained, but there is the computer identifier on the bus lines a, b, c only remains until the data transfer is carried out on these must is a hold circuit consisting of an OR gate 69 and one of these controlled flip-flop 70 provided. The OR gate receives the information as an input Anfo, identifier and the signal delayed by the D flip-flop 60 by a basic clock The busy line is supplied with signals that occur when the computer disconnects the bus lines wants to occupy and the bus line was not previously occupied. This will set the NOR gate 69 enabled the flip-flop 70 in its set State to tilt, which remains in this state until it reaches it via a line 71 from the memory clock generation circuit 46, which, as already mentioned, is also one Johnson counter that is supplied with reset pulses. The flip-flop 70 therefore holds with its output signal via the OR gate 62, the transmission gate 63 also then still open if the computer ID is transferred from the r, outgoing lines at the next system cycle a, h and c is removed.

The data transfer and the other clock circuits then run synchronously with the part on the storage side. The computer in question takes it over the bus line there is no data exchange with the main memory 6, so the memory clock generation circuit 46 reset via line 52 and generates the clock JO. Exists on the computer side a request and the bus line was not occupied in the previous cycle, so, as already described, a log 1 appears at the output of the NOR gate 69, which, in addition to setting the JK flip-flop 70, also resets the memory clock generation circuit 46 via the NOR gate 72 and the subsequent line 52 enables, in the next The clock phase is then the output of the JK flip-flop 64, as already described, likewise log 1 and continues to give the Memory clock generating circuit 46 free. : i go with the next clock pulse J1 the 4 MSB (1/2 Bytc) of the first partial address Y on the bus lines a, b, c, d, the next clock pulse J2 places the following 4 LSBs of address X on the bus lines; the cycle time J3 enables the main memory to be accessed and made available of the endured data word; with the following clock pulse J4 the Adoption of the first Ilaib word of 4 bits; the clock pulse J5 enables Acceptance of the next 1/2 byte of the determined data value from the memory.

There are 4 double flip-flops 75, 76, 77 and 78, with only the takeover mimic for one half of the first double flip-flop 75 is shown in more detail is, also for the reason that these are only preferred exemplary embodiments in any case acts, but a complete and operational system for a better understanding is explained throughout. It should be understood that the invention is not directed to the specific Arrangements of logic circuits and memory is limited, but that any electronic component and solid-state switching element that is capable of is to fulfill the functions described, can be used.

One input Dl 'of flip-flop 54, which is the noppelbaustein 4013 the RCA can act is via cascaded logic circuits in the form from NPJD gates 79 and 80 once the signal on the bus line i, which is here for any bus line can be 'fed to the other input of the NAND gate 79 the clock pulse J4 is supplied. The flip-flop 75 takes over the signal of Bus line at its output and holds itself through the feedback of the line 81 and the further NAND gate 82, the other input of which is the J4 pulse via a Inverter 83 is supplied. The writing of the so at the input D1 of the flip-flop 75 prepared information is then carried out with the basic cycle fO. This related on the one part of the double flip-flop 75 specified circuit arrangement is repeated in all remaining flip-flops 75 to 78 in the same form, where the flip-flops 77 and 78 from the second clock pulse for the word transfer from the main memory, namely J5, are controlled. At the outputs of the flip-flops A1 to A8 is after Expiry of the sixth clock pulse J5 the desired data information of the main memory for further processing.

The clock generation circuit 46 prepares with the clock time pulse J5 advance the flip-flop 64 to reset. A seventh clock pulse then follows J6, which prepares the flip-flop 70 for resetting via the line 71, whereby the busy line is released in the next cycle and also the output of the NOR-G, atters 67, since the second input of the NOR-gate 67 Anfo = log 1, on log O, so that the switched through switch 63, as already described, the BUSv line is set to log O in clock phase J6. At the same time, the Cycle time pulse J6 an acknowledgment pulse can be derived which is sent to the main memory 6 or other parts of the circuit is supplied.

The clock pulse Jh is no longer required for the transmission of information interesting, it enables the busy line to be occupied during another Clock with log 0, so that the main memory and all others are on the bus line lying computer 1, 2, or 3, etc. clearly recognize the end of the data exchange can.

The log O of the busy line in clock pulse J6 is the counter 14 again free for counting, which means that the memory-side circuit part another bar is still held before the system switches to its cyclic The starting point.

In addition, it should be pointed out that the fit the cycle time sequences responsible Johnson counter 27 or 46 count with the basic clock fO, which is when selected Embodiment has a frequency of 600 KlIz, as already mentioned.

The illustration of FIG. 9 shows the timing diagram of the circuit sequences on the computer side of the bus interface circuit; Fig. 9a shows again, accordingly 6a, the basic clock f0, FIG. 9c shows the request signal Anfo, the to has taken over the status log 1 at any point in time. As soon as accordingly 9b the signal of the identification of the computer or the signal naming "not" is present, as already explained above, the busy signal goes according to FIG. 9d to the state log 1, at the same time, as shown in FIG. 9f, the reset signal from the Johnson counter 46 from log 1 to log 0, which therefore generates the signal J1 at the next basic clock (corresponding to FIG. 9h), assuming that the signal JO when the Johnson counter 46 was stationary from the start. Figure 9e shows the output of the flip-flop 70, which assumes the state log 1 and via the OR gate 62 holds the transmission gate 63 open. According to Figures 9h to 9m then run the clock pulses J1 to J6 of the Johnson counter 46; there the beat J3 has no meaning for the computer side, its course is not shown here, however, the cycle J4 begins offset by one cycle time after the cycle J2 of FIG. 9i.

In the following there are still some possibilities for the distribution of priorities for the computer access to the main memory explained.

So far it has been assumed that the main memory itself which responds cyclically to the computer connected to it via the bus lines 5 and asks for a query; however, it is as shown in FIG. 8 also possible that the requirements for the data exchange from the computers themselves come.

In principle, this can be done by using the computer as required data information from the main memory, for example when a request signal is present Anfo immediately occupy the bus line, whereupon the data exchange is controlled by the signal log 1 now present on the busy line, which is also the Johnson counter 27 of main memory 6 can start goes. It must be taken into account here, however, that with the same basic cycle two or even more computers try to use the bus lines to the main memory 6 to get through. Priority control is necessary for this special case, for which there are several safety irons.

A first possibility is that the computers have their access to the memory by the fact that the busy line through the state log 1 from Computer controlled occupied and at the same time on the positive lines, of which how next Already mentioned above, any number can be present, one assigned to them Set computer identification. Such a possibility is shown in FIG. 8 for two computers; in this case, only one INFO line needs to be assigned the computer ID so that the priority of access can be decided on two computers can be. In Fig. 3, the first computer with E and the second computer with F where only the parts required for prioritization are shown are. Both computers E and F go with their name or their assigned code word at the same time on the bus line, whereby they can short-circuit each other, as can also be seen from the illustration in FIG. 8. Will one of the calculators go through short-circuited the identifier of another computer accessing at the same time and if he is trained in such a way that he notices this "short-circuiting", then it is also at the same time decided on the priority, because the "short-circuited" Pechner will then be his Withdraw the request.

For priority control between only two connected As will be explained in more detail below, computers are just a bus line required, the priority of three computers must be decided upon two bus lines etc.

The one for routing the code words from the computer to the rJusleitung Relevant circuit parts can in the embodiment of FIG. 3 from two series-connected inverter amplifiers 90, 91 or 90 ', 91' exist, with the computer part F corresponding to the calculator part E in its circuit structure, such as Incidentally, the entire circuit, as an integrated chip, preferably in MOS-FET technology is constructed; in the case of the inverter / amplifier 91 'controlled by the inverter 90' it is a M0S-FET transistor whose "drain" connection is via a "load transistor" 92 is due to positive potential. If the state log O is passed as a code word via the Inverters 90 'and 91' on bus line a, this also results in the State log 0, the state log 1, with which the inverters 90, 91 of the computer partly E (as a code word) can be controlled, it is shortened.

Such an interconnection of the lines on the Rus line corresponds to a a logical wired AND operation, as it is in the course of the priority comparison the log 0 state of one computer short-circuits the log 1 state of another computer. The computer with the lower priority defined in this way recognizes the short circuit of its log 1 priority bit by comparing it, whereupon it requests the memory and so that the BUSY signal withdraws. The comparison can be carried out as shown in Fig. 8, i.e. the code word of the computer which the inverter / amplifier Controlling 90, 91, at the same time arrives at the one input of an exclusive OR «attendant 93 or 93 '; the other input of the OR gate is the same as the one controlled Bus line connected.

The exclusive OR gate is as will be recognized by those skilled in the art trained that it is able to differentiate between its two To respond to incoming signals; in the present case there is one Inequality in the computer part, which therefore has the low priority.

As can be seen, the entire priority control during a single clock step of the basic clock run, if enough bus lines are available are, in the previous embodiment, 4 bus lines were assumed, so that the priority control of a total of 5 connected single-purpose computers can be carried out in the manner just described, with the Computer with the highest priority, i.e. with a code word "OOOO" all lower priority Computer shorts.

For example, if you only have a two-line bus and should more than 3 single-purpose computers are controlled in their priority access to the main memory 6 then the distribution of priorities can also be made over time solve that in each case at the same cycle time from the connected lin-purpose computers at the same time the first bit of the priority identifier or the computer's code word is placed on the information line (s). Appear with the next bars the other bits of the priority identifier one after the other. Here, too, corresponds to Interconnection of the lines on the 3us a "wired AND" and in the course of the priority comparison the log 0 state of the higher priority computer becomes the log 1 state of the other short circuit. In other words, the priority control of the "wired AND" also partially serial, if this is due to the number of available standing bus lines is desired.

Another possible priority control is that depending on Number of existing individual bus lines for each individual purpose one of these lines is permanently allocated and the computer sends its request to the main memory via this line feeds. The main memory, for its part, has a distribution logic that gives priority weighting the computer with the highest priority is allowed to access it. In the practical Embodiment this can be done by having one or more single-purpose computers on them permanently assigned bus lines (the computers can be soldered to these) Relay the log 1 status as a request to the main memory and the main memory closes all log 1 states of the single-purpose computers with the exception of the highest priority short. In this way, the remaining, "short-circuited" single-purpose computers recognize that your access has been rejected (the recognition can be designed in such a way that as shown in Fig. 8), the assumed single-purpose computer is also informed, since its priority request signal has stopped. The memory then occupies the busy Leituna on its own and blocks any further access, then leaves the data transfer in the manner already described above, if desired, in front of you.

It should be noted that the rest of the earlier in Priority control specified in connection with the overall explanation of the system of the cyclical counting on the "memory chip", with successive times the individual computer IDs are counted with the 5 basic clock fO, prioritized can be, i.e. the counting process begins with the higher priorities, see above that they also have the option of memory access first when a request is made to do this.

The logic levels at the bus interface are, if with integrated C-M0S technology is to be worked, defined in the usual positive logic, i.e. the state log 1 = + UO log O = 0.

Since negative logic is used in P-MOS technology, all signals are inverted that are exchanged between the bus line and the P-MOS chip will. The following correspond to: log 1 = O (UDD) log O = + UO (VSS).

However, this does not affect the principle of operation of the systems touched.

As an alternative for data exchange with a four-line bus It is also conceivable that the Pusy line and the fourth information line are dispensed with is used for bus reading.

In this case the DUSY-Sidnal must be used in all single-purpose computers during the information transfer are stored.

The invention thus enables the unchanged use of computer chips for all purposes or vehicles with an off-chip storage with the lowest Wiring effort and minimal effort on connection pins.

Claims (11)

P a t e n t a n s check 1. Method for data transfer between a central memory and at least one computer connected to it, preferably with a central electronic circuit in a motor vehicle that consists of a large number of Linzel computers, for example ignition timing computers, main computers in a fuel injection system, transmission computer and the like. exists, which is connected via a common connection line (bus line) before memory by addressing for the respective vehicle specific or Query data values pertaining to the respective operating status, marked by this, that prior to addressing the memory, the bus line connected to ctic is curch Single-purpose computer carried out a priority control determining the access to the memory and the bus line by using a separate occupancy line (busy line) It is blocked that the address of the each stored data value to be queried depending on the number of existing bus lines in binary partial word packets is given serially to the memory that after access the determined data value also in the same parallel series packet formation from the memory is fed to the computer and that the occupancy of the Dusy-Leituna is then released is, with all individual steps by a central clock control in your Sequence are determined. 2. The method according to claim 1, characterized in that the access of the computer with priority authorization through fixed wiring of all computers permanently assigned to the bus lines (wired AND) and routing from each computer Priority code words on the bus line is decided, with lower priority Code words of higher priority code words are short-circuited. 3. The method according to claim 1, characterized in that: fl each computer is permanently connected to one of the pusleituncten and via this a request for Data transfer transmitted to the main memory, which the request with the help of a accepts or rejects priority-weighted distribution logic and at the same time the busy line is occupied for the computer with priority authorization. 4. The method according to claim 1, characterized in that for priority control the main memory, weighted if necessary, computer identifiers cyclically and via the bus lines reserved for the exchange of information Transferred to computers that when there is a request signal for data exchange seize the busy line. 5. Device for data transmission between a central memory and at least one computer connected to this, preferably in a central electronic circuit in an I; raft vehicle, dic from a large number of individual computers, for example Ignition timing computer, main computer in a fuel injection system, transmission computer and the like exists, which is via a common connection line (bus line) from the memory by addressing for the respective motor vehicle specific or the respective Query data values relating to the operating state, characterized in that a Priority control circuit (8; go, 91, 93) a clock timer circuit (12, 46) a Receiving circuit (11) for the address transmitted by the respective computer (1, 2, n), which is connected to the read-only memory (13), and a transmission circuit (10) is provided is the total of the data value determined from the read-only memory (13) or time-controlled in serial partial packages the bottom lines (a, b, c, d) and that a receiving circuit (54, 55) arranged on the computer is provided that the transmitted data value is timed in the same way saves. 6. Apparatus according to claim 5, characterized in that the area of the main memory (6) assigned a priority sequence control circuit (3) is provided Is that cyclically and, if necessary, priority-weighted depending on the number of Main memory (6) connected individual computers (1 2, p) encoded computer identifiers generated in parallel and via bus lines connected as information lines (a, b, c, d) supplies all computers (1, 2, n) so that each individual computer has a decoding circuit for the computer identifier (21, 22, 23) that one has the priority flow control circuit (8) with the bus lines (a, b, c, d) connecting switching logic (22) is provided and that a switching logic (22) controlling and the clock timing for the data transfer determining cycle time control hold (12) is provided. 7. Apparatus according to claim 6, characterized in that the clock time control circuit (12) in the main memory (6) a clock time control circuit running synchronously with this (46) is assigned (1, 2, n) for each Tinzelreehner. 8. Device n rch one or more of claims 5-7, characterized characterized in that the number of available bus lines (a, b, c, d) for the Information exchange corresponding switching logics (transmission gates 25, 25a: 5n, 51; 54, 55) provided sinc ', each of which is controlled by the memory cycle the bus lines (a, b, c, d) during a clock pulse transferable binary Parallel value the other side (receive register 11 in the memory or memory logic circuits 5d, 55 on the computer), in such a way that a rear Code word (address or data value from memory) depending on the number of available Bus lines can be transmitted in serial binary word sub-packets, clock-time-controlled from the synchronously running clock timing control circuits (27, 46). 9. Device according to one of claims 5 to 8, characterized in that that a priority counter (14) controlled by the occupancy signal on the busy line it is provided that the output signals of the priority counter (14) on the Bus lines (a, b, c, d) receiving decoding circuit (47) on the computer side from logical combination circuits connected to these bus lines (E-clusive OR gates 57, 58, 59), the other inputs of which are the respective computer's own Identifier defining signals are supplied in such a way that when the for the respective computer an output signal for the occupancy of the line BUSY can be generated. 10. Apparatus according to claim 9, characterized in that the output signal the decoding circuit (47) for computer recognition of a switching logic (transmission gate G3) can be supplied, which puts a request signal (SK) on the BUSY line and then blocks this line or all of the connecting lines when the request signal (nnfo) has the state log 1. 11. The device according to claim 10, characterized in that the Occupancy signal log 1 for the BUSY line indicates the cyclical sequence of the priority counter (14) interrupts. Device according to one or more of Claims 5 to 11, characterized characterized in that the occupancy signal of the busy line on the memory side a the clock generation circuit (12) assigned sequence counter (Johnson counter 27) throws, whose clock-wise in the temporal sequence the state log 1 exhibiting output connections (JO to J5) control the data transfer process. Device according to claim 12, characterized in that parallel to control the flow counter (27) in the memory another, similar flow counter (Johnson counter 46) in the computer from the input and output signal of a flip-flop (70) triggered via a NOR gate (72) and for the cyclical generation of the clock time signals (JO to J5) synchronous clock time signals (JO to J6) is caused and that the flip-flop (70) is set via a 2X0F gate (69) and the output is simultaneous with the Starting the sequence counter (46) via the OR gate (62) which occupies the BUSY line Switching logic (63) is maintained in its through-connected state. Device according to one or more of Claims 5 to 13, characterized characterized in that with 4 bus lines (a, b, c, d) 2 signal transmission circuits (Transmission gates 50, 51) are provided, each of which has an input Half of the address to be transmitted to the main memory (6) is present that the transmission gates are connected on the output side to the bus lines (a, h, c, d) and each from the cycle time signals (J1 or J2) of the countdown counter (46) in the computer one after the other are controlled for the transmission of the respective computer address. Device according to Claim 14, characterized in that the receiving circuit (11) on the memory side from lo «isehen logic circuits (NAND gate 35, 35 '; Inverter 36) consists, in each case a first half of the logic circuits from the time-synchronous output clock time signals (J1, J2) of the sequence counter on the memory side (27) are controlled for transmission of the assigned partial address to the read-only memory (13). Device according to claim 15, characterized in that the other input controlled by the clock time signals (J1, J2), as a NAND gate (35, 35 ') formed logic circuits as a buffer for the address operating flip-flop circuits (33, 33 ') are connected downstream, the outputs of which on the inputs (A0 to A7) of the read-only memory (13) in the main memory (6) are present. Device according to claim 1G, characterized in that for completion the address generated by the computer to one or more of the address MSBs an adding network (24) is connected upstream, which on the output side with the logic circuits (35 ') is connected in front of the read-only memory (13) and the input side in each case to the computer address attached to the output lines (a, b, c, d) and, on the other hand, one from the computer identifier from the priority counter (14) derived binary coding (21, n2, B3) is fed to the device according to claim 17, characterized in that a from the computer identifier (Q1, 2, a3) the additional address sub-area (B1, B2, B3) generating address precoding circuit (23) is provided. Device according to one or more of Claims 5 to 18, characterized marked that one after address transfer from the clock time signal (J3) of the flow counter (27) in the memory acted upon reset line (38) for the Priority counter (14) is provided. Device according to claim 19, characterized in that for resetting of the priority counter (14) one of exclusive OR gates (15, 16, 17) with one downstream NAND gate (18) existing logic circuit is provided, the priority counter by permanently connecting the other inputs of the exclusive OR gates depending on the number of computers available (1, 2, n). Device according to one or more of Claims 5 to 20, characterized characterized in that for the return transmission of the data value addressed by addressing from the read-only memory (13) which the computer identification with the bus lines (a, b, c, d) connect Umschalylohik (22) on the input side by supplying the receipt signal the BUSY line to the outputs (D6, D7, D8) of the read-only memory (13) and that the output side is connected in parallel with the bus lines (a, b, c, d) Transmission gates (25, 25 ') one after the other from the clock time signals (J4, J5) of the sequence counter (27) are controlled, the inputs of the transmission gates (25, 25 ') with the assigned outputs (D1 to n4 or D5 to D8) of the read-only memory (13) are connected. Device according to a. or according to claims 5 to 21, characterized characterized in that each computer has a flip-flop that can be set by the request signal (64) is assigned, the output signals of which are used as occupancy signals for the line 3USY serve and which of the clock pulse (J5) of the sequence counter assigned to the computer (46) can be reset. Device according to one or more of Claims 5 to 22, characterized characterized that to take over the from the memory at the clock times (J4, J5) partial data values from the cycle time output signals placed on the bus lines (a, b, c, d) (J4, J5) of the computer-side sequence counter (46) controlled logic circuits (79, 80, 82) are provided, which the respective data subword from the read-only memory (13) Transmit temporary storage in the form of bistable flip-flops (75, 7G, 77, 73). Device according to Claim 23, characterized in that the transfer clock time pulses (j4, J5) can each be fed to one of the inputs of NAND gates (79, 82), with the other input of a NAND gate (79) that on the respective bus line (a, h, c, d) pending signal from the read-only memory (13) is supplied and the other input of the other NAT4D gate (82) from the output of the as a buffer memory acting flip-flops (75) is fed back, the signal transfer being controlled by the system clock he follows. Device according to one or more of Claims 5 to 24, characterized characterized in that the sequence counter for generating the cycle time signals (JO, J1, Jn) consists of D flip-flops (28, 29, 30) connected in series, and that the Output of the last flip-flop (30) via an inverter (31) to the input of the first flip-flops (28) is fed back, the indexing of the contents of the Flip-flops takes place system-clock-controlled.