DE2725504A1 - DATA PROCESSING SYSTEM AND INFORMATION OUTPUT - Google Patents

Description

PAT EN TA N W. \ LT E
SHIP V. FÜNER STREHL SCHÜBEL-HOPF EBBINGHAUS FINCK

MARIAHILFPLATZ 2 A 3, MUNICH 9O
POSTAL ADDRESS: POSTFACH 95 O1 6O, D-8OOO MÖNCHEN 95

KARL LUDWIG SCHIFF DIPL. CHEM. QR. ALEXANDER V. FÜNER DIPL. ING. PETER STREHL DIPL. CHEM. OR. URSULA SCHÜ3EL-HOPF DIPL. ING. DIFITER EBBINGHAUS DR. ING. DIETER FINCK TELEPHONE (OSS) 48 9OB « TELEX [> 23 66S AURO D TELEGRAMS AUROMARCPAT MUNICH

AMDAHL CORPORATION DA-14149

JUNE 6, 1977

Data processing system and information from 2 & be

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- 2T-

The invention relates to digital computers, and more particularly to methods and arrangements by which the states blanked by locking and other circuits in the data processing system for the purpose of maintenance and error analysis or issued.

In fast-working, extensive data processing systems, it is particularly useful for analyzing and recording Disturbance conditions desirable to be able to monitor the state of interlocking and other circuits in the data processing system capture. In known systems, there are often directly wired key points in the data processing system provided and routed to a control panel or console to illuminate the console lamps to let and so an indication of the state of the memory circuits, to give in the system. However, direct wiring is unwieldy in large data processing systems and extensive because the number of indicator lights on the system console for convenient analysis by the operator gets too big.

In other known systems, the computational capability of the data processing system is used to output data, specifically utilizing appropriate data paths of the data processing system to store the state of the circuits within predetermined storage locations in the system memory. The use of appropriate data paths in the memory system, however, has the difficulty that if there is a faulty data path or faulty control circuit connected to the data path, the information output is faulty, so that the localization of faults and their isolation is difficult and time-consuming.

In view of these difficulties with known data processing systems, there is a need for improved access to memory circuits in the data processing system in order to analyze information for maintenance and other purposes to facilitate. 709851/0923

The invention relates to a data processing system with a primary arrangement for carrying out the main ones or first-rate instruction-controlled data processing and a secondary arrangement for independent Addressing and independent access to memory locations in the primary or main arrangement.

In a preferred embodiment of the invention contains the secondary arrangement is an instruction-driven digital computer that communicates with the rest or the main arrangement of the data processing system is in communication via a console control interface. The console control interface receives addresses from blocking or other circuits in the primary arrangement and addresses or controls such circuits via an output address rail, which is parallel to the entire primary arrangement is switched to several places. A group of circuits including the addressed circuit within the system is controlled to its states through the console control interface via the data output rail transferred to. The information on the data output rail is stored back in the digital computer. The digital computer analyzes the returned information and identifies errors or performs other operations.

According to a further embodiment of the invention, the data processing system is implemented with logic circuits on integrated circuit chips. The integrated circuit chips, which each contain several circuits, are formed on a carrier which is referred to as a carrier for receiving several chips (MCC). Each MCC receives address bits from the output address rail and feeds an output line for returning the information. The output lines from all of the MCCs together form the output data rail.

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In a preferred embodiment, each MCC is off 32 logic chips built, which are arranged in four rows and eight columns. The columns are made up of the three bits higher order of the address rail addressed. Individual circuits on each chip are identified by the four address bytes lower order addressed. Many or all of the interlocking or electronic circuits and other circuits are individually addressable, regardless of the operating status of the main arrangement and the main program. In the preferred embodiment, each MCC is addressed in parallel so that each MCC is one when driven Provides output information on the secondary arrangement. The secondary arrangement contains an access device in the form of four 16-bit key gates, which are each selected individually by two additional address bits. The 16 bits the information that is driven by the selected key gate is corresponding to four additional address bits further processed, which specify or designate one of the 16 bits of the controlled information.

Since addressing and access are controlled by the secondary program in the digital computer, the The sequence in which the circuits are addressed and selected can easily be changed, resulting in a large Flexibility results in the way in which the information is used to locate the fault or to any other information Purposes is made accessible.

Thus, in view of the foregoing summary, the invention provides improved methods and arrangements for addressing and for access to circuits in a data processing system.

Other objects, objects and advantages of the invention will appear more preferably from the following description Exemplary embodiments based on the drawing. Show it:

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1 shows the block diagram of a data processing system according to the invention ;

Fig. 2 shows the schematic representation of the console unit of Fig. 1;

3 is a schematic representation of the interface control and the console control interface in FIG Console unit of FIG. 2;

FIG. B shows the schematic representation of the design of the data processing system of FIG. 1 with carriers for several chips (MCC) which are addressed and queried by the console control interface of FIG. 3;

5 shows a schematic representation of the physical training a typical MCC;

6 shows the schematic representation of the logical arrangement of the chips on a typical MCC;

7 shows the schematic representation of various data paths in the execution unit in the system of FIG. 1;

8 shows the schematic representation of the chip arrangement of the 1H register which is part of the data path of the arrangement which forms Fig. 7;

FIG. 9 shows the schematic representation of a chip assigned to a bit in the circuit of FIG. 8; FIG.

Fig. 10 shows the schematic representation of the recording chip the MCC containing the circuit of Figure 8; and

11 shows the schematic representation of an alternative embodiment the chip select circuit.

The data processing system according to the invention shown in FIG. 1 contains a main memory 2, a memory control unit 4, an instruction unit 8, an execution unit 10, a channel unit 6 with associated input / output and a Console unit 12. The system of Figure 1 is controlled by commands from the main system where an organized group of these Commands form a system program. The system commands and the data processed by the commands are

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from the input / output unit via the channel unit 6 and the Memory control unit 4 fed into main memory 2. The system commands and data are processed by the main memory 2 the instruction unit 8 is passed through the memory controller 4 and processed in such a way that they control the execution in the execution unit 10. The system of FIG. 1 is more specifically shown in FIG U.S. Patent 3,8AO,861.

According to Fig. 4, the logic circuits and other circuits, which comprise all or a major part of the system of FIG. 1, executed on an MCC 602, each Carrier contains multiple integrated circuits implemented on chips (Fig. 5), e.g. up to 64 MCCs 602 starting with MCC (0,0), ..., MCC (7,7). Each of these carriers typically contains up to 42 chips, which are shown in FIG. 5 in one (6x7) rectangular arrangement are arranged. Further details of the structure of chips for arrangement on chip carriers are disclosed in U.S. Patent 3,808,475.

FIG. 2 shows further details of the console unit 12 of FIG. 1. The console 12 contains a digital computer 501 which connected to 32K memory 502 in a conventional manner. The digital computer 501 is with several control units connected, e.g., a disk control unit 516, a channel control unit 411, a console control unit 513 and an interface control unit 511. In an analogous manner, additional control units can be connected to the computer 501 shown be connected.

Disk control unit 516 interfaces between computer 501 and a 256K disk input system 528. Channel control unit 411 is one of the channel control units associated with channel unit 6 of FIG. The console control unit 513 interfaces between the computer 501 and the control console 524. The interface control unit 511 interfaces between the console control interface 525 and the digital computer

The computer 501 is typically a computer named Nova 1200 from Data General Corporation. The details of how such a calculator works and the The manner in which the control units, such as the control units 411, 511, 513 and 516 of FIG. 2, are in connection with the computer stand or form interfaces for the same, are in the document DG NM-5 "How to use the Nova Computers", April 1971, the Data General Corporation.

The interface control unit 511, which is connected to the computer 501 by the 48-bit rail 535, is connected via rail 533 to the console control interface (CCI) 525, which in turn is connected via an output rail 436 is connected to circuitry in the data processing system of FIG. The ones with I-unit, C-unit and Connections, labeled S-Unit, from the console control interface 525 are described in more detail below.

Fig. 3 shows more details of the console control interface 525 and the interface control unit 511. The console control interface (CCI) 525 includes a 16-bit command register (CR) 551 with a 16-blt control command rail 540 providing input to the represents the I and the C unit , which will be described below. The interface 525 also includes 16-bit addressing registers 552 and 553 which feed the 32-bit output address rail 542 which is connected to the address paths in the I and S units of the data processing system.

Interface 525 also includes 16-bit data registers 554 and 555 'whose outputs feed the 32-bit console data rail 543 which serves as the console data input to the data paths in the C, S and I units of the data processing system of FIG.

The console registers 551 to 556 and the gates 561 to 565 are determined by the decoded output signals of a decoding

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rers 567, which corresponds to the address in the 4-bit memory address register 554 in the interface control unit 511 decodes and selects one of these eleven entities.

The interface 525 also contains a 9-bit output address register 556 which, via a 9-bit output address rail 590, determines the circuits in the data processing system that are to be queried.

Interface 525 also includes a 64-bit output data rail 591 connected to 16-bit output gates 561-564. A controlled 16-bit rail 592 connects via selector circuit 476 and rail 535 to state gate 572 via selector circuit 576 and the rail. 535 with console computer 501. Decoder 567 receives the 4-bit input from the memory address register 574 and decodes the 4-bit address on one of the eleven lines 621-1 through 621-11. The dial-up lines 621-7 to 621-11 select the sensing gates 56I to 564 and the state gate 565, respectively. The gates 561 to 565, in which if the gates are 16-bit, the rails will be 634-1 through 634-4 which form the 64-bit output data bus 591. The controlled rail 592 receives the status information from the I unit in the data processing system of Fig. 1.

Interface 525 also contains the console interface control (CIC) 570, which contains a logic circuit corresponding to the total as lines 541 designated input signals and output signals are generated. In detail, through the START line, the Triggered clock signals of the I-unit, whereby the control signals for the entire system of FIG. 1 are formed. The S, I and C VALID lines 545, each of which is per unit S, I and C each one is provided, give a signal when one or more of the selected units are energized to receive control commands from the console unit.

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When the S, I or C units receive a VALID signal they point over the S, I, and C-COMP lines 544 the receipt of this signal, whereby per unit S, I or C a COMP line 544 is provided. The line 595 indicating the active state of the I-unit signals the states STOP, PSV / WAIT, CHECK STOP and METERING when they occur in the system of FIG. The OP END management detects the control pulses in the system of Fig. 1. If the delay between pulses exceeds a fixed duration, so there is an error condition in the system of FIG. The administration OP END serves as an input to a STOP detection circuit 581 which detects the length of time between control pulses and generates an output signal indicating an impermissible delay.

The control unit 570, the STOP or interruption detection circuit 581 and the STOP line point over the Active state gate (AS gate) 582 via the to the selector circuits 576 connected lines 584 indicate the state of the system of FIG. The gates 583 ask the 8-bit - Interrupt Mask Register (IMR) 579. The gate

582 and the register 579 have a bit-bit relationship, that is, bits 0, 1 ..., 7 correspond to the control commands S COMP, C COMP, STOP, PSW WAIT, CHECK STOP, HANG DETECTOR or METERING correspond.

The interrupt mask register 579 determines the signals on the output line DONE from gate 583. Because of the bit-wise correspondence between the bits in IMR 579 and the bits in active state gates 582 is indicated by the activation of a bit in the active state gates, the line DONE is set if the corresponding bit in the Register 579 is not set. If the bit in register 579 is set, the output line of the gate is DONE

583 not set.

Enable register 578 stores three bits of information which determine which of the S, I and C VALID lines

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should or should be excited. The bit O denotes the Selection of the S-unit, bit 1 the selection of the I-unit and bit 2 the selection of the C-unit. The rest of the decoded States of the three bits in register 578 are ignored.

The control circuit (CIC) 570 responds on an input START line which also causes the output START line to be energized. In addition, the START-CIC input line is in charge the operation of the control circuit 570. The input line CLEAR-CIC clears the CIC logic circuit 570 before the arrival of a new command for the system of FIG. 1 from the computer 501.

Referring to Figure 4, the output address bar 590 is from the output data register 556 of FIG. 3 connected in parallel to multiple MCCs 602 so that a particular chip on each MCC and further a specific blocking circuit on the address chip can be controlled for each MCC. The state of the addressed blocking circuit appears as an output signal on the corresponding output line 603. For example an output signal is emitted from the addressed blocking circuit on the MCC (0,0) on the output line 603 (0,0). Similarly, each of the 64 MCCs of Figure 4 has a corresponding output line 603; this creates the 64-bit rail 591. The rail 591 is the data output rail 591, which is used as an input to the sensing gates 561 to 564 (Fig. 3) is connected.

5 shows a typical MCC 602 made up of 42 chips 606. The chips are conveniently in seven rows 1 to 7 and arranged in six columns A to F. Each of the logic chips 606 contain several circuits for implementation the logic and memory functions performed in the system of FIG. Further is at least one of the chips, for example the chip 1F in Fig. 5, an output or registration chip to which the 9-bit

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Output address rail 590 is connected and which feeds the 1-bit output line 603, which together with the other 1-bit output lines from the other MCCs form the output data rail. Instead of place 1F in the exemplary embodiment 5, any chip location can contain the registration chip, as the actual location is unimportant in the arrangement. In Figure 5, each MCC is typically embodied as containing up to 42 chips shown, each chip is arranged on its chip carriers in a specific place.

In FIG. 6, the MCC shown physically in FIG. 5 is shown in such a way that its logical accessibility through the output arrangement according to the invention becomes clear. The logic MCC of FIG. 6 includes 32 addressable logic chips, with each logic chip 608 in FIG. 6 including at least one chip 606 of FIG. Since only 32 addressable chips are provided in FIG. 6, each logic chip 608 can expediently contain a non-addressable chip 606 or a part of a chip 606. The registration chip 611 in Fig. 6 corresponds to the chip 1F in Fig. 5. The logic chips C (0,0), C (0,1), ..., C (0,7) of Fig. 6 are in one arranged first of four lines. The chips 608 in FIG. 6 can correspond to any combination of the chips 606. The registration chip 611 in FIG. 6 is supplied as an input with the 9-bit output address rail 590; it feeds a 1-bit output line 603 of the output data bus 591 of FIGS. 3 and 4. In addition, the registration chip 611 feeds eight output column select lines 614-1 to 614-8 and four chip select lines 613 -Bit-bar 612 connected, which consists of four row keypad lines 612-1 to 612-4. Each row line 612-1 through 612-4 receives the output data from a row of eight logic chips 608 which feed a common line via an OR operation.

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The registration chip 611 of Figure 6 receives the 9-bit address on rail 590. The three higher order bits of this 9-bit rail 590 become one of the eight lines 614 decoded. The selected line 614, e.g. line 614-1 selects the appropriate column, e.g. column C (0,0), C (1,0), C (2,0) and C (3.0). The low order four bits of the 9-bit address on line 590 are transferred via rail 613 to the Choice of 1 to 64 circuits on each chip 608 transmitted. The state of the selected circuit on each chip will be then output to the corresponding row line 612-1 through 612-4. The remaining two (middle) address bits on the rail 560 are used in the registration chip 611 to select one of the four output lines 612 for transmission als.Outssignal on the output rail 603. In the following the output arrangement is in connection with a typical embodiment described in more detail. The embodiment described is that shown in FIG 1H register in the execution unit 10 of the system of Fig. 1.

In Fig. 7 is between the LUCK unit 20 and the byte adder 32, the 1H register 24 is shown, all of which are parts of the execution unit 10 of the system of FIG. Further details of the 1H register and its operation in the execution unit of the system of FIG. 1 are described in U.S. Patent No. 3,792,362, among others.

In general, the 1H register 24 is a 32-bit register to which input data from the LUCK unit 20 is supplied and whose output is connected to the byte adder 32, among other things. The information is in the register 24 fed in by a clock pulse on a line 631 from a clock generator 102. The details the clock operation for entering data into register 24 is described in U.S. Patent No. 3,792,362, cited above. In this document, a typical bit is shown as

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Bit position 124 is designated as a lock or input circuit containing described. The lock or input circuit 124 of the register 24 in FIG. 7 is further in FIG Figs. 8 and 9 shown in more detail.

In FIG. 8, bit 124, which represents bit location 24, the 32 bits 0 to 31, is located on chip 606-1. Additionally for bit 24 of register 24 in Figure 7, bits 25 to 31 are arranged on chips 606-2, 606-3, 111, 606-8, as BIT 25, BIT 26, ... or v /. BIT 31 are designated. Bit 24 labeled 606-1 is one of the chip 606 like that previously described with reference to FIG. 5, everyone is of the other chips 606-2 to 606-8 are also identical to chips 606 in FIG. 5. The eight chips 606-1 to 606-8 form part of the eight chips forming a line, for example line 0 in FIG. 6, which have a common, have output 612-1 designed as an OR link.

In addition to the chips 606-1 to 606-8, the logic chips of FIG. 6 contain further logic circuits in a row which are not formed on the same chip. For example, logic chip C (0,0) includes physical chip 606-1 and logic gate 623-1. Similarly, logic chip C (0,1) of Figure 6 includes chip 606-2 of Figure 8 and column select gate 623-2. The column selection gates 623-1 and 623-2 are formed on different physical chips in a preferred embodiment. Similarly, chips 606-3, 606-4 and 606-5 of Figure 8 are three different physical chips and are each connected to a column selection gate 623-3, 623-4 and 623-5, respectively. The column select gates 623-3 through 623-5 are formed on a single physical chip in a preferred embodiment. Similarly , the chips 606-6, 606-7 and 606-8 are each three different physical chips, while the corresponding selection gates 623-6, 623-7 and 623-8 are arranged on a different physical chip. In the

709851/0923

ORIGINAL INSPECTED

The circuit 617-1 arranged on physical chips in the manner described forms a Row from C (0,0) to C (0,7) of logic chips 608.

In the same way as circuit 617-1 one line of eight logic chips for a 601-type MCC, similar additional circuits form 617-2, 617-3 and 617-4 rows of logic chips, each with one output line 612-2, 612-3 or 612-4. The four lines 612-1 through 612-4 form the 4-bit rail 612. Each of the row circuits 617-1 through 617-4 become the eight column select lines 614 and the four chip addressers lines 613 supplied, which extend from the registration chip 611 of FIG.

Further details of bit 24 chip 606-1, which represents bit 24 in 1H register 24 of FIG. 7, are shown in FIG. Referring to FIG. 9, chip 606-1 includes lock or hold circuit 124-1 which is bit 24 of bits 0 through 31 of 1H register 24 in FIG. The latch 124-1 receives its input from the LUCK unit 20 over lines 652, one of which is a data line and the other is a control line. Similarly, circuit 124-1 receives inputs from the shifter on lines 653 ', one of which is a control line and the other is a data line, and from the adder on lines 654, one of which is also a data line and the other is a control line. The circuit 124-1 further includes a synchronous reset input connected to the line 651 for resetting the circuit at given times during the operation of the data processing system. In addition, circuit 124-1 receives input signals on lines 631 and 632 for controlling the clock of the circuit. Line 631 is an input line from clock 102, while line 632 is an inhibit control for preventing clock control of circuit 124-1. Of the

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272550 /,

Output 656 of circuit 124-1 is connected to a phase splitter 637 which is the first level I of the byte adder associated logic (U.S. Patent 3,814,925). In addition to the connection with the phase splitter 637, the normal Representing the data path of the system of FIG. 1, latch 124-1 has an output to an additional one Phase splitter 638 which is the beginning of the output data paths of the system of FIG.

In addition to circuit 124-1, chip 606-1 includes in According to a preferred embodiment of the invention, a latch 124-2 which corresponds to the BIT 24 in the 2H register 25 of the Circuit of FIG. 7 is assigned. Similarly, chip 606-1 includes latch circuits 124-3 and 124-4, respectively bits 24 of the 1L and 2L registers, which are additional registers connected to execution unit 10, which, however, are not otherwise specifically described in the present specification. The output of the hold circuit 124-2 on line 657 is similar to the outputs of circuits 124-3 and 124-4 with the phase splitter 637 and your phase splitter 638 connected.

The phase splitter 638 contains a gate 639 which the state circuit 124-1, as indicated on line 656, to select gate 641. The dial gate

641 is one of four gates in selection circuit 640 to appropriately select which of the four circuits 124-1 through 124-4 is to be connected to an output line 643. The selection of the gate in the selector 641 is made by a decoder

642, which includes two bipolar gates 645 and 646, which respond to two bits on lines 613-1 and 613-2 address the 4-bit rail 613. The two bits on the Lines 613-1 and 613-2 are decoded so that one of the four gates in selector circuit 640 is uniquely selected will. When the lines + LA and + LB from the gates 645 or 646 are energized, the gate 641 is selected and provides an output signal on the line 643 which

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is applied as an input to gate 644, which provides the output signals on line 619. According to Fig. 8 the output on line 619 is the output for the selected chip BIT 24. In circuit 606-1 of FIG. 9, only two of the four chip address lines the rail 613 is used, namely the lines 613-1 and 613-2. The two through these two lines uniquely determined binary addresses determine one of the four holding circuits 124-1 to 124-4. There can be additional Lines 613-3 and 613-4 are v / ends, so that according to a preferred embodiment of the Invention up to 16 hold or other circuits each Chip can be applied. The output on line 619 (FIG. 9) provides one or four latches on chip 606-1. If more, up to 16, latch circuits are applied, the output signal represents represents one of 16 hold states on line 619, which are addressed by the address on the 613 rail.

Fig. 10 shows further details of the recording or Registration chips 611 of FIG. 8. The registration chip 611 receives the nine input address bits on input rail 590. The three higher order bits on the lines 590-1, 590-2 and 590-3 are inputs to column select decoder circuit 626, where they are commonly used Way to choose eight output lines 614 decoded will. The eight lines 614-1 through 614-8 from rail 614 are as inputs to each of the row select circuits 617-1 to 617-4 of Fig. 8 are connected. In the circuit of FIG. 8, the column select lines act so that one of the gates 623-1 to 623-8 is selected in accordance with the three input address bits.

The next two higher order bits of address rail 590 appear on lines 590-4 and 590-5, v / o them as input signals to the row decoding and selection circuit

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627 serve. In circuit 627, the two bits on lines 590-4 and 590-5 are counted to select one of four gates 661-1 through 661-4 which is shown on rail 612 from the MCC of FIG 8 receives row status lines 612-1 through 612-4. The correspondingly coded in the input bits 590-4 and 590-5 I _n formation selected line of the four lines 612, and the pending on this signal appears as an output signal on line 603, which represents one of the 16 bits of the rail 634-1 , which is one of the 64 bits in the 64-bit rail 591 of the figure.

Similarly, the lower order four bits are on lines 590-6 through 590-9 in the power driver circuit 628 and via rail 613 to each of the chips on the MCC 601 of FIG. 6 and in particular to the Line chips 617-1 of FIG. 8 transferred back. The signals on lines 590-6 through 590-9 appear to be identical Signals on each of the lines 613-1 to 613-4.

The operation of the device is described in more detail below.

The main or primary arrangement of FIG. 1 receives, controlled by those processed by the instruction unit 8 Main instructions Information from the memory controller 4 and the main memory 2. The execution unit 10 processes the main commands controlled by the information from the command unit 8. For example, use some main instructions in the main arrangement an adder in the execution unit 10 (Fig. 7). When editing of a main instruction, the information is fed to the adder 32 of FIG. 7 via the LUCK unit 20, where it is im 1H register 24 and in the 2H register 25 is stored. The information held in registers 24 and 25 becomes added by adder 32; the results appear in register 38. How the main arrangement of the Fig. 1 in the execution of main instructions is in the

7 (19851/0923

U.S. Patents 3,840,861 and 3,792,362.

The data is entered in register 24 at one of the Clock signal on line 631 controlled or predetermined Time. The line 631 sets each of the bit positions 0 to 32 of the register 24 and the particularly emphasized bit 24 of the 1H register, which is labeled 124-1. The setting of latch 124-1 and the other bit positions in register 24 are generally used by the main arrangement in the execution of the instructions of a main instruction stream controlled.

The console computer 501 of FIG. 2 takes the information from address locations in the main arrangement of FIG. 1 corresponding to a program of secondary commands. The operation of the secondary arrangement and the program of the secondary commands in the computer 501 is independent of the operation of the main arrangement in the execution of the main commands.

In a preferred embodiment, the address spaces in the main arrangement of FIG. 1 are corresponding a 16-bit binary address that is generated or specified by the computer 501. This address has the following Meaning.

Bits 0 and 1 designate one of four groups of 16 MCCs and especially their output lines 603. The bits 0 and 1 are decoded to one of the four key gates 561 to 564 in FIG. 3 and thus one of four groups of the 16 lines to choose.

Bits 2 to 5 designate one of the 16 information bits, that appear on the one group of 16 lines that were selected by bits 0 and 1.

Bit 6 determines whether the selected information bit 5 of the 64 HCCs of FIG. 4 must be inverted in order to obtain the correct one Maintain polarity. Bit 6 is in a preferred

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ferred embodiment of the invention useful because at In a preferred technology, inverting logic is used. In the case of the inverting logic, the presence of an odd or even number of logic levels in the transmission of the information to the Key gates determine whether the information has correct or inverted polarity. By using bit 6 In the present address format, the addressed information can be arbitrarily returned to the sensing gates without having to apply an odd or even number of logic levels. Appropriate setting of bit 6, the correct polarity is established for each information bit that is tapped off.

Bits 7 through 9 select one of eight columns of chips 608 in Figure 6. Bits 7 through 9 represent three of the nine Address bits outputs on output address rail 590 of FIG.

Bits 10 and 11 select one of four rows of chips 608 in Figure 6. Bits 10 and 11 are two of the nine Address bits on the output address rail 590.

The four bits 12 through 15 select one through 16 circuits on each chip 608 of Figure 6. Bits 12-15 are the four remaining bits of the nine address bits on the rail 590 of FIG. 3.

Whereas in the main arrangement any arbitrary circuit position can be addressed for access by the console computer 501 can be made, the 1H register 24 and especially the bit 24 location is used as a special example for explanation (Fig. 7) selected.

Bit 24 of 1H register 24 has the following 16-bit binary address:

0 1 2 3 4 5 6 7 8 9 10. 11 12 13 14 1010100000000000

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In the binary address of bit 24, bits O and 1 represents a binary 3 indicating that SCAN-2 gate 563 is the energized gate. Gate 563 receives the addressed information from the main device and in particular the 16 lines 603 from the MCCs MCC (0, A), MCC

(1,4) MCC (7.4) and MCC (0.5), MCC (1.5),

MCC (7.5).

Bits 2 to 5 of the 24-bit address represent a binary 10, v; as means that the desired information bit is on the tenth MCC, the MCC (1,5) appears in the group of MCCs determined by bits 0 and 1.

The 0 in bit 6 of the above binary address indicates that there is no inversion in the returned to bit 24 of the 1H register Information is required.

All 0 for the column selection bits 7 to 9 and for the Zei lenv / ählbits 10 and 11 indicate that bit 24 in the 1H register on your chip, which is arranged in column 0 and row 0 of the chips. According to Fig. 6 is in the column or line 0 the chip C (0,0).

Referring to Figure 10, bits 7, 8 and 9 on the lines ground 590-1, 590-2 and 590-3 to select the output line 614-1 of column 0 of the eight lines 614. the Line 614-1 in FIG. 8 selects O-gate 623-1, the other input of which is the output signal on line 619 from location 606-1 of bit 24 in the O column of the O row 617-1 is fed. Simultaneously, rows 617-2, 617-3 and 617-4 select a 0 column output on their lines 612-2, 612-3 and 612-4.

In FIG. 10, bits 10 and 11 for row selection are input signals on lines 590-4 and 590-5 and are selected for selecting the gate 661-1, which thereby becomes the 0-row line 612-1 from the four row lines 612 which proceeds from the circuit of FIG.

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In Figure 10, bits 12, 13, and 14 and 15 are inputs on lines 590-6 through 590-9 that are on the output rail 613 appear, which in turn is entered into the chips of FIG. 6, including chip C (0,0), which is chip 606-1 in FIGS. 8 and 9. In Figure 9, two of these four bits actually become one preferred Embodiment used, in particular the two bits on lines 613-1 and 613-2. Since bits 12 to 15 are on Level 0, they switch the gates 645 and 646 with + LA and + LB in the state 0. The 0 state of these two Output signals are fed to the decoder 640 as an input signal, so that the gate 641 switches through and opens the inputs + LA and + LB are at level 0. With gate 641 switched through in this way, the output of the gate becomes 641 is controlled by the state of line 656 'from gate 639. Gate 639 provides a connection from the inverting Output of latch 124-1 on line 656. The inverted output on line 656 has the inverted value of the addressed bit 24 of the IH register.

The output on line 656 is applied to gate 639, gate 641, gate 644, gate 623-1 (FIG. 8) and inverted in gate 661-1 (FIG. 10) and supplies one of the 64 addressed input signals on line 603 64-bit rail 591. The number of reversals from line 656 to line 603 of FIG. 6 is five, so that when connected to the inverted output signal itself on line 656, the correct polarity im Sensing gate 563 of FIG. 3 is presented.

The console computer 501 of FIG. 2 acts via the interface control 511 and the console control interface 525 for performing the required addressing and the required information access in the main arrangement of FIG. 1 in accordance with a secondary program of commands according to the following table I:

709851/0923

- & Γ-

Table

Sl XLOGB: S2 STANDARD: S3 S4 S5 S6 S7 S8 S9 SLO SIl S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25

STA 3.2 LDA 1, LGAMK AND 0.1 SUB 1.0 MOVS 1.1 MOVR 1.3 MOVR 1.1 COM 1.1 .PTY 100 DOB 1, CCIl LDA 3, SADR DOAP 3, CCIl MOVZL 0.0 MOVL 0.0 i MOVL 0.0 LDA 1, RMSK AND 0.1 MOVR "0.0 LDA 3, GRPT ADD 1.3 LDA 1.0.3 DOA 1, CCIl DIA 1, CCIl .PTY

$ 709851/092

ORIGINAL INSPECTED

S26 BITS! ι SADR: S27 GRPT: S28 S29 S30 S31 S32 LGAMK S33 RMSK: S34 S35 S36
S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50

MOVZL 0.0, SZC MOVS 1.1 MOVL 0.0, SZC ADDL 1.1, SKP MOV 0.0, SKP ADDL 1.1 MOVL 0.0, SZC ADDL 1.1 MOVL 0.0, SZC MOVL 1.1 SÜBZR 3.3 MOVZL .1.1 AND
MOVC 3.0, SNR
0.0 MOVL 0.0 JMP 0.2 120000 . + 1 000000 010000 130000 040000 000777 000003

709851/0921

ORlGlNfAL INSPECTED

The processing of the above secondary command program is written in connection with bit 24 in 1H register 24. In a preferred embodiment, the Computer 501 is a Nova computer that uses / ends the standard Nova commands. A jump subroutine (JSR) is used to enter the program in Table I. The computer jumps to the address XLOGB (S1). According to instructions S1, a return address is stored in accumulator 3 in accumulator 2.

The 16-bit address of the 1H register bit was used before the S2 instruction 24 stored in accumulator 0.

According to instruction S2, the accumulator 1 is loaded with the content of a fixed address LGAMK at S49. As with S49 shown, the value 000777 is given in octal values.

In instruction S3, the contents of accumulator 0 and accumulator 1 are subjected to a logical AND operation, so that the address bits 7 to 15 in the positions 7 to 15 of the accumulator 1 are stored.

In instruction S4, bits 7 to 15 in the accumulator subtracted from the contents of bits 0 to 15 of accumulator 0, so that bits 0 to 6 in accumulator 0 are sent to the Positions 0 to 6 remain and bits 7 to 15 of accumulator 0 are now equal to 0.

In the case of instructions S5, S6 and S7, bits 7 up to positions 7 to 15 of accumulator 1 are assigned to positions 0 to 8 of accumulator 1 shifted.

In the case of instruction S8, the content of the accumulator 1 is complemented to convert the information into the required Form when transferred to the system through Output Data Register (ODR) 575 of FIG. 3.

With the instructions S9 and S10, a system call prevents an interruption of the instruction stream until the instruction

709851/0923

gen S25 and S26.

Address bits 7 to 15 are in The positions 0 to 8 of the accumulator 1 are transferred to the output data register (ODA) 575 in the interface controller 511.

In the case of instruction S12, accumulator 3 with the content a fixed address SADR loaded at S43. As stated in S43, the SADR address content is 1200000 in octal code.

When S13 is indicated, the content of the accumulator 3 to the interface control 511 and in SAR 574 entered. The decoder 567 decodes the octal code 1200000 and switches input gate 548 to SADR register 556 via line 621-6. Instruction S13 also becomes generates a signal on line 549 which turns on gate 548, along with the signal on line 621-6 enters the 9-bit address from ODR register 575 into SADR register 556. In the case of instruction S13, the addresses Secondary arrangement, in response to the secondary program of Table I, the primary arrangement corresponding to the 9-bit address in register 556.

In the case of instructions S14, S15 and S16, the address bits 0 and 1 in accumulator 0 moved from positions 0 and 1 to positions 14 and 15. This operation leaves the Bits 2 through 6 are transmitted in places through 4.

In the case of instruction S17, the accumulator 1 is loaded with the content of a fixed address RMSK in S50. As mentioned in S50, the W _e rt in octal code 000,003th

In instruction S18, the contents of the accumulator 0 subjected to an AND operation with that of accumulator 1, so that the accumulator 1 has address bits 0 and 1 in positions 14 and 15 because of the mask.

In the case of instruction S19, address bits 2 to 6 are grounded

709851/0923

four transfer points of the accumulator 0 in the places O to 5 of the accumulator 0.

At the instruction S20, the accumulator 3 becomes with the content a fixed address CSIPT which is the address of S44 plus one.

In instruction S21, the content of bits 0 and 1 of the accumulator is 1, which is a binary 2 for bit 24 of the 1H register are added to the address in the accumulator 3 to generate the addressed gate of the four key gates 561, 562, 563 or 564 in FIG.

In instruction S22, the accumulator becomes 1 with the key gate address loaded from the content of the location whose address is in accumulator 3.

At instruction S23, the key gate address of the accumulator 1 is entered into the SAR register 574 and is available for selection of the gate 563 is decoded by the decoder 567.

In the case of instruction S24, input gates 572 are switched through and so the 16 bits of the output information from the Gates 563 are input to the accumulator 1. In the case of instruction S24, the information is accessed by the primary unit accomplished. The information acquired in S24 is the information addressed in S13.

In the case of the instructions S25 and S26, the blocking effect is applied to the interruptions formed in the case of the instructions S9 and S10 removed.

Instructions S27 through S38 analyze address bits 2 through 6 in accumulator 0 using conventional programming techniques and determine which of the 16 bits of output information in accumulator 1 is the desired bit that corresponds to the state of bits 24 in the 1H register. The program determines that this is the tenth bit. In the case of instruction S38, this bit is transferred to the transfer locations. ,

Ϊ09851 / 092Ι

In instruction 339, the address bit 6 becomes obgofrart. this leads to a jump or a delay to S ^ i 0, v / enn the tenth output bit must be complemented.

In the case of instruction S40, the complement is formed, if this proves to be necessary, given by S39.

With SA1, the tenth output bit is in the carry position entered in place 15 of accumulator 0.

At the instruction S43 the program is terminated, and that secondary data processing system returns to that specified in S1 Return address back.

Fig. 11 shows an alternative embodiment for the decoding and selection circuits, the four bits for the Addressing can be used by a chip. In detail, the 9-bit rail 590 connects the four 1-chip bits 590-6, 590-7, 590-0 and 590-9 as input with a 4/7 converter 586. The translator 587 is coding in a preferred embodiment the four input bits 590-6 to 590-9 according to the following Table II. In Table II are the four address lines 590-6 through 590-9 are indicated in the column lines 590-. The encoded output signals appear in Table II as lines 597-.

709851/0923 OBlGiNAL INSPECTED

Table II; °°

LEITIJMG FM 590- LINES 597-

6 7 8 9 ABCDE

0 0000 0011111

1 0001 0110111

2 0010 1001111

3 0011 1100111 I 4 0100 0101111 j 5 0101 0111101

! '6 0110 1101011

! 7 0111 1101101 I.

j 10 1000 1011011

, 11 1001 1110011

12 1010 1010111

13 1011 111010 1

14 11000111011

I 15 1101 1111001

■ 16 1110 1011110

j 17 1111 1011101

709851/0923

ORIGINAL INSPECTED

Referring to Figure 11, translator 586 is on a 7-bit rail 597 connected to decoders 567-1, 587-2, ..., 587-8. The decoders 587 contain each middle input gate 598 three entrances. The gate 598-0 is supplied with two of seven output signals and one on rail 597 Input signal via a line 473, which is connected to certain switching cars of the data processing system of FIG is to whom the information must be transmitted, when the gate 598-0 is switched through by input signals with the level 0 on the two lines 597. That Gate 598-0 typically receives input signals 597-A and 597-B from seven lines 597. The signals on these lines correspond to the octal code 0 and clearly select the gate 598-0.

Similarly, gate 598-1 is connected to input lines 597-A and 597-D, which are shown in Table II represent octal 1. The output signals of gates 590-0 to 598-7 are commonly supplied to the first gate 599-1 of eight column gates 599-1 to 599-8. The exits the decoders 587-2 to 587-8 are each connected in a similar manner to one of the column gates 599-2 to 599-8.

The eight column gates 599-1 to 599-8 are in turn connected to one another and feed the output line 612'-1, which is analogous to line 612-1 in FIG. Similar the lines 612'-1 to 6i2'-4 are analogous to the four lines in the rail 612 of FIG. 10.

In a preferred embodiment of the invention, both decoding systems of FIGS. 9 and 11 are used. In a preferred embodiment, the typical circuitry attached to line 473 is taken from the console. Line 473 detects the active state of the circuit. The lit 24 of the ill-iieris lorz is, as explained with reference to FIG. 9, a blocking or holding circuit for comparison. Accordingly, the invention

709851/0923 ORIGINAL INSPECTED

application either to the task or to reading out the status a of holdings or other storage elements in the data processing system or on the output of the state of certain lines angov / ends v / earth, independent of the Keeping data dynamically changeable. While the scanned circuits predominantly hold circuits it can be seen that the state Any Circuit to be queried.

Further details of the interaction between the main and secondary arrangements are described in the simultaneously filed patent application (internal file number DA-14150) entitled "Konnole imd Datenverarbeitungssystem".

Claims

709851/0923

ORIGINAL INSPECTED

Claims (14)

Data processing syc'ieni with a storage device, a command processing device and command execution device for processing stored command programs for the execution of data processing, characterized by a main device for processing a main command program, which aroused several according to the Kauptprogranim Has main noises, and by a secondary device for processing a secondary command program independent of the main command program, whereby the Secondary device contains an addressing device, which is connected according to the secondary program for addressing the main circuits, and an access device that according to or responsive to the secondary program the main circuits Bit of secondary arrangement connects. 2. Data processing system according to claim 1, characterized g ekennzei seframe that the secondary device has the following components: a programmable digital computer for exchanging information with devices over a plurality of control devices corresponding to the secondary program, an interface control means for exchanging information with the digital computer comprising a Ausgabedatenrepister for outputting addresses the main circuits and an output address register 709851/0923 ORIGINAL INSPECTED holds, and a control interface device that between the interface controller and the Main device is switched and contains acIi essiereinrichtungen and access devices that are switched are that they are processed accordingly by the execution address register the secondary program for addressing and access of the main circuits are switched on. 3. Data processing system according to claim 2, characterized in that the addressing device further includes an output address data register which, when switched on, is connected to the output dot register and has an output which forms an output address rail which is connected in parallel to a plurality of the main circuits, and that the system further includes scan gates connected in series to a plurality of the main circuits by an output data bus, and further means responsive to the addresses generated by the secondary program to turn on the output address data registers and scan gates, thereby addressing and retrieving the information in the main apparatus . 4. Data processing system according to claim 3, further e- g characterized by a plurality of integrated circuit chips which contain a plurality of main circuits Je, by several Chiptr: he, each containing a corresponding amount of the chips and are each connected to the address track and an input signal to% the data- 709851/0923 originally inspected output rails provide devices connected to each chip carrier for addressing one of the associated number of chips in accordance with the information on the
Address rail, and means on each of the chips responsive to the address rail for addressing a particular main circuit on the chip and for connecting each addressed main circuit to the data output rail. 5. Data processing system with integrated circuit chips, each with several circuits in first data paths
for information storage have corresponding data processing operations which are executed in accordance with first instruction programs, characterized in that an output device for
Addressing and querying the states of the circuits is provided independently of the first data paths and in accordance with the second command programs. 6. Data processing system according to claim 5 »characterized by one on the second
Programs responding to digital computers for addressing circuits on each of the chips and for receiving data indicating the status of the addressed circuits. 7. The data processing system according to claim 6, furthermore marked by one on the operation of the digital computer appealing interface control 709851/0923 device that includes a console control interface that interfaces the controller with the Connect the chips of the data processing system. 8. Data processing system according to claim 7, characterized in that that the console control interface has an output address data register for storage contains the addresses of the circuits to be queried, which supplies the addresses and feeds the output data rail, and also an output data bus connected to a plurality of the circuits in the data processing system is to receive the state of the circuit specified by the output data register. 9. Data processing system according to claim 8, characterized in that that several chip carriers are provided, each chip carrier having a line for the Data output rail feeds. 10. Data processing system according to claim 8, characterized in that each chip carrier contains means for receiving the signals on the address rail for selecting a circuit to be connected to the associated output data line. 11. Data processing system according to claim 10, characterized in that the address rail contains nine bits, and that up to 64 output data lines are provided. 708851/0923 12. Datenvorarbe.itungssystem according to claim 11, characterized marked that each chip carrier up to contains 32 addressable chips arranged in four lines and eight columns are arranged, and that the output outputs of the chips in each row are ORed are connected to each other. 13. Datonvorverarbeitungsystein according to claim 12, characterized characterized in that the columns are represented by the three higher order bits of the 9-bit address rail are addressed, and that the lines are addressed by the next two address bits of the higher order will. 14. Data processing system according to claim 13, characterized characterized in that each chip uses the four lower order bits to determine up to 16 addressable circuits per chip for connection that receives output lines. 709851/0923