DE2906249A1 - Integrated, complementary MOS circuit - has pairs of active regions of two MOS elements coupled by polycrystalline silicon strip and has short circuit at undesirable junction - Google Patents
Integrated, complementary MOS circuit - has pairs of active regions of two MOS elements coupled by polycrystalline silicon strip and has short circuit at undesirable junctionInfo
- Publication number
- DE2906249A1 DE2906249A1 DE19792906249 DE2906249A DE2906249A1 DE 2906249 A1 DE2906249 A1 DE 2906249A1 DE 19792906249 DE19792906249 DE 19792906249 DE 2906249 A DE2906249 A DE 2906249A DE 2906249 A1 DE2906249 A1 DE 2906249A1
- Authority
- DE
- Germany
- Prior art keywords
- polysilicon
- mos
- circuit
- strip
- active
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 46
- 230000000295 complement effect Effects 0.000 title claims description 5
- 229910052751 metal Inorganic materials 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 14
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 11
- 229920005591 polysilicon Polymers 0.000 claims description 42
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 24
- 229910052697 platinum Inorganic materials 0.000 claims description 12
- 230000007704 transition Effects 0.000 claims description 12
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 2
- 229910052793 cadmium Inorganic materials 0.000 claims description 2
- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium atom Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 claims description 2
- 239000011651 chromium Substances 0.000 claims description 2
- 239000011733 molybdenum Substances 0.000 claims description 2
- 229910052758 niobium Inorganic materials 0.000 claims description 2
- 239000010955 niobium Substances 0.000 claims description 2
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 claims description 2
- 229910052763 palladium Inorganic materials 0.000 claims description 2
- 229910052715 tantalum Inorganic materials 0.000 claims description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 229910052720 vanadium Inorganic materials 0.000 claims description 2
- LEONUFNNVUYDNQ-UHFFFAOYSA-N vanadium atom Chemical compound [V] LEONUFNNVUYDNQ-UHFFFAOYSA-N 0.000 claims description 2
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 claims 1
- 229910021357 chromium silicide Inorganic materials 0.000 claims 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 claims 1
- 229910021334 nickel silicide Inorganic materials 0.000 claims 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 claims 1
- 229910021342 tungsten silicide Inorganic materials 0.000 claims 1
- 229910052726 zirconium Inorganic materials 0.000 claims 1
- 238000000034 method Methods 0.000 description 13
- 239000004020 conductor Substances 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 229910052594 sapphire Inorganic materials 0.000 description 5
- 239000010980 sapphire Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 238000012856 packing Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 238000005507 spraying Methods 0.000 description 3
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910021339 platinum silicide Inorganic materials 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000005496 tempering Methods 0.000 description 2
- FRWYFWZENXDZMU-UHFFFAOYSA-N 2-iodoquinoline Chemical compound C1=CC=CC2=NC(I)=CC=C21 FRWYFWZENXDZMU-UHFFFAOYSA-N 0.000 description 1
- VLJQDHDVZJXNQL-UHFFFAOYSA-N 4-methyl-n-(oxomethylidene)benzenesulfonamide Chemical compound CC1=CC=C(S(=O)(=O)N=C=O)C=C1 VLJQDHDVZJXNQL-UHFFFAOYSA-N 0.000 description 1
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 1
- LTPBRCUWZOMYOC-UHFFFAOYSA-N beryllium oxide Inorganic materials O=[Be] LTPBRCUWZOMYOC-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- MUMZUERVLWJKNR-UHFFFAOYSA-N oxoplatinum Chemical compound [Pt]=O MUMZUERVLWJKNR-UHFFFAOYSA-N 0.000 description 1
- 229910021340 platinum monosilicide Inorganic materials 0.000 description 1
- 229910003446 platinum oxide Inorganic materials 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 238000005475 siliconizing Methods 0.000 description 1
- 229910052596 spinel Inorganic materials 0.000 description 1
- 239000011029 spinel Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 229910052845 zircon Inorganic materials 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4825—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body for devices consisting of semiconductor layers on insulating or semi-insulating substrates, e.g. silicon on sapphire devices, i.e. SOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
"Integrierter. komplementärer MOS-Schaltkreist' "Integrated. Complementary MOS Circuit"
Die Erfindung betrifft einen integrierten, komplementären MOS-Schaltkreis mit einem ein erstes Paar aktiver Bereiche des einen Leitungstyps aufweisenden ersten MOS-Element und einem ein Paar aktiver Bereiche des anderen Leitungstyps aufweisenden zweiten MOS-Element, sowie das Herstellen von Kontakten an integrierten CMOS-Schaltkreisen.The invention relates to an integrated, complementary MOS circuit with a first having a first pair of active regions of the one conductivity type MOS element and one having a pair of active areas of the other conductivity type second MOS element, as well as making contacts on integrated CMOS circuits.
In einem in der Zeitschrift Bell System Journal", Band XLV, Nr. 2, Februar 1966 von M.P. Lepselter veröffentlichten Aufsatz mit dem Titel eBeam-Lead Technology" wird ein Verfahren zum Herstellen von Transistoren mit Streifenleitern beschrieben, wobei die Leiter sowohl bauliche als auch elektrische Aufgaben erfüllen. Bei diesem Verfahren wird ein ohmscher Kontakt aus Platin-Silizid hergestellt und auf diesem ein aus aufgesprühten und anschließend galvanisch vergoldeten Titan- und Platin-Schichten bestehender Zuleiter gebildet. Mit der im Hinblick auf engere Packung und verminderte Herstellungskosten fortschreitenden Entwicklung der integrierten Schaltkreise wurde es jedoch offenbar, daß das in dem Aufsatz vorgeschlagene Verfahren nicht zu akzeptieren ist, da die Leiter einen übermäßig großen Teil der Chip-Fläche einnehmen und der zusätzliche Verfahrensschritt des Aufsprühens der Titan-und Platin Schichten sowie des galvanischen Aufbringens des Goldes die Herstellungskosten über die tragbaren Grenzen anhebt.In one in the Bell System Journal, "Volume XLV, No. 2, February 1966 by M.P. Lepselter published an essay entitled eBeam-Lead Technology "is a process for manufacturing transistors with strip conductors described, the conductors fulfilling both structural and electrical tasks. In this process, an ohmic contact is made from platinum silicide and on this one made of sprayed and then galvanically gold-plated titanium and platinum layers of existing leads are formed. With the in terms of closer Packing and reduced manufacturing costs progressive development of the integrated Circuits, however, it became apparent that the method proposed in the paper is unacceptable as the conductors take up an inordinate amount of the chip area take and the additional process step of spraying the titanium and platinum Layers as well as the galvanic application of the gold over the manufacturing costs raises the wearable limits.
Als Alternative zu den aus elementarem Metall bestehenden Verbindungsleitern des früheren Standes der Technik besteht ein neuerliches Verfahren zum Herstellen der in integrierten Schaltkreisen hoher Element-Dichte notwendigen Verbindungsleiter darin, daß dotiertes polykristallines Silizium (Polysilizium) verwendet wird. Zum Erzielen noch höherer Packungsdichte in integrierten Schaltkreisen sind weit verbreitet auch vergrabene Kontakte benutzt worden. Bei Anwendung in der NMOS-Technologie treten auch nur geringe Schwierigkeiten bei Benutzung der Polysilizium-iechnik auf, da sowohl die Polysilizium-Streifen als auch der Siliziumkörper N-leitend dotiert sind0 Für das Herstellen von CMOS-Bauelementen, die also sowohl Elemente mit N-leitendem Kanal als auch Elemente mit P leitendem Kanal enthalten, gibt es jedoch keine brauchbaren bekannten Verfahren zum Herstellen einer Verbindung der beiden Elemente mit Hilfe eines aufgrund der bekannten NMOS-Technik hergestellen, dotierten, vergrabenen Kontakts, ohne daß ein unerwünschter bzw. unzulässiger PN-Übergang entsteht. Das rührt daher, daß unabhängig von der Dotierung des Polysilizium-Streifens ein Ende des Streifens in einem Element mit N-leitendem Kanal und das andere Endo des Streifens in einem Element mit P-leitendem Kanal endet ?Jnn z.B. N-dotiertes Polysilizium als Lei terstreifen benutzt wird, wird ein PN-Übergang an der Stelle gebildet, an der der Leiterstreifen in das Element mit dem P=leitenden Kanal mündet. Umgekehrt entsteht der PN-Übergang an dem Element mit dem N-leitenden Kanal wenn eine P-dotierte Polysilizium-Leitung als Verbindung des P-Kanal- und des N-Kanal-Elements verwendet wird.As an alternative to the connecting conductors made of elemental metal In the prior art, there is a new method of manufacture the connecting conductors required in integrated circuits with a high element density in that doped polycrystalline silicon (polysilicon) is used. To the Achieving even higher packing density in integrated circuits are widespread buried contacts have also been used. When used in NMOS technology, step only minor difficulties in using the polysilicon technology, there Both the polysilicon strips and the silicon body are doped in an N-conducting manner0 For the production of CMOS components, i.e. both elements with N-conducting Channel as well as elements with P-conductive channel contain, but there are none useful known method for connecting the two elements with the help a doped, buried contact produced on the basis of the known NMOS technology, without creating an undesired or impermissible PN transition. This is because that regardless of the doping of the polysilicon strip, one end of the strip in one element with an N-conducting channel and the other endo of the strip in one Element with P-conducting channel ends? Jnn e.g. N-doped polysilicon as conductor strips is used, a PN junction is formed at the point where the conductor strip opens into the element with the P = conductive channel. The reverse is the case for the PN junction on the element with the N-conductive channel if a P-doped polysilicon line as a connection of the P-channel and N-channel elements are used will.
Der Erfindung liegt die Aufgabe zugrunde, für einen Schaltkreis eingangs genannter Art eine elektrisch leitende Verbindung zwischen Elementen verschiedenen Leitungstyps zu schaffen, die relativ wenig Platz erfordert und daher eine hohe Packungsdichte ermöglicht und die ohne den von dem aus elementarem Metall bestehenden Verbindungsleitern her bekannten hohen Aufwand herzustellen ist. Die erfindungsgemäße Lösung dieser Aufgabe ist gekennzeichnet durch einen einen der aktiven Bereiche vom ersten Leitungstyp des ersten MOS-Elements mit einem der aktiven Bereiche vom zweiten Leitungstyp des zweiten MOS-Elements verbindenden, dotierten Polysilizium-Streifen und mindestens einen am Ort eines unerwünschten, potentiellen Übergangs einen niederohmigen, den Übergang überbrückenden, leitenden Pfad bildenden Kurzschluß.The invention is based on the object for a circuit at the outset called type an electrically conductive connection between elements different To create line type that requires relatively little space and therefore a high Packing density made possible and that without the one consisting of elemental metal Connecting conductors is known to produce high effort. The inventive The solution to this problem is characterized by one of the active areas of the first conductivity type of the first MOS element with one of the active areas from doped polysilicon strips connecting the second conductivity type of the second MOS element and at least one low-resistance, the transition bridging, conductive path forming short circuit.
Erfindungsgemäß werden die bei bekannten Verfahren auftretenden Schwierigkeiten dadurch beseitigt, daß als Verbindungsleiter Polysilizium benutzt wird, daß der Poiysilizium-Streifen in beliebiger, gerade in das Verfahren passender Weise dotiert wird und damit gegebenenfalls der unerwUnschte Übergang entsteht und daß der Übergang - eventuell anschließend - mit einem elektrischen Kurzschluß versehen wird, welcher vorzugsweise als Polysilizid-Abschnitt herzustellen ist und den Übergang überbrückt. Es entsteht so also ein vergrabener Kontakt für das komplementäre MOS-Bauelement.According to the invention, the difficulties encountered in known methods are eliminated in that polysilicon is used as the connecting conductor that the Polysilicon strips doped in any way suitable for the process and thus the undesired transition may arise and that the transition - possibly afterwards - is provided with an electrical short circuit, which is preferably to be produced as a polysilicide section and bridges the transition. This creates a buried contact for the complementary MOS component.
Anhand der schematischen Darstellung von Ausführungsbeispielen werden weitere Einzelheiten der Erfindung erläuterm. Es zeigen: Fig. 1 bis 3 Querschnitte eines nach der Silizium-auf-Saphir-Technik herzustelleden CMOS-Halbleiterbauelements im Zustand verschiedener aufeinanderfolgender Verfahrensschritte; und Fig. 4 bis 7 Querschnitte von verschiedenen Ausführungsbeispielen.Based on the schematic representation of exemplary embodiments explain further details of the invention. Show it: Fig. 1 to 3 cross-sections of a CMOS semiconductor component to be produced using the silicon-on-sapphire technology in the state of various successive process steps; and FIGS. 4 to 7 cross-sections of various exemplary embodiments.
Die Beschreibung bezieht sich lediglich der Einfachheit halber auf ein Bauelement mit einem aus Saphir bestehenden isoliereden Substrat. Der Ausdruk Silizium-auf-Saphir (SOS) umfaßt jedoch nicht nur Saphir sondern z.B. auch Spinell oder monokristallines Berylliumoxid. Die Erfindung ist natürlich E3uch bei CMOS-Vorrichtungen mit massivem Halbleiterkörper mit Vorteil anzuwenden.The description refers to for simplicity only a component with an insulating substrate made of sapphire. The expression Silicon-on-sapphire (SOS) does not only include sapphire but also, for example, spinel or monocrystalline beryllium oxide. The invention is of course also applicable to CMOS devices to use with a solid semiconductor body with advantage.
Die Fig. 1 bis 3 zeigen die verschiedenen Ausfüngsbeispielen des erfindungsgemäßen Bauelements gemeinsamen ersten Verfahrensschritte. Auf einem aus Saphir bestehenden Substrat 10 sind die siliziuminseln 12 und 14 angeordnet.1 to 3 show the various exemplary embodiments of the invention Component common first process steps. On one made of sapphire The silicon islands 12 and 14 are arranged on the substrate 10.
Die Inseln 12 und 14 werden nach dem Herstellen einzeln maskiert (die asken sind nicht gezeichnet) und dann nacheinander dotiert. Im gezeichneten Ausführungsbeispiel ist die Insel 14 maskiert, während die Insel 12 mit Phosphor 16 dotiert wird, so daß eine N-leitende Insel 12 entsteht.The islands 12 and 14 are individually masked after manufacture (the asks are not drawn) and then endowed one after the other. In the illustrated embodiment is the island 14 masked while the island 12 is doped with phosphorus 16, so that an N-conductive island 12 is formed.
Nach den Dotieren der Insel 12 wird die Maske der Insel 14 abgetragen und eine andere Maske auf die nunmehr dotierte Insel 12 aufgebracht. Danach wird die Insel 14, z.B. mit Bor 118" unter Anwendung irgendeines bekannten Ionen-Implantations- oder Diffusionsverfahrens dotiert Anschließend wird nach Fig. 2 die Maske von der Insel 12 abgetragen und ein zweites selektives Maskierverfahren ausgeführt. Dabei wird z0B0 die Insel 14 vollständig maskiert, während die Insel 12 eine (schmale) Maske 20 erhält. Daraufhin wird die maskierte Insel 12 einer solchen Bor-lonen-Implantation ausgesetzt, daß die beiden P+-leitenden Zonen 12.1 und 12.3 entstehen, während die unter der Maske 20 befindliche N--leitende Zone 12.2 den ursprünglich implantierten Leitungstyp beibehält. Die Masken beider Inseln werden nun abgetragen, und die Insel 12 wird mit einer auch den implantierten Bereich bedeckenden Maske versehen, während auf die Insel 14 eine Maske 22 aufgebracht wird, die den unter ihr liegenden P-dotierten Bereich in der Zone 14.2 schützt. Die freiliegenden Teile der Insel 14 werden nun z.B. einer Phosphor-Ionen-Implantation oder Diffusion ausgesetzt, so daß die N+-leitenden Bereiche 14.1 und 1403 entstehen.After the island 12 has been doped, the mask of the island 14 is removed and another mask is applied to the now doped island 12. After that, will the island 14, e.g., with boron 118 "using any known ion implantation or diffusion method. The mask is then doped according to FIG Island 12 removed and a second selective masking process executed. The island 14 is completely masked, while the island 12 has a (narrow) Mask 20 receives. The masked island 12 then becomes such a boron ion implantation exposed that the two P + -conducting zones 12.1 and 12.3 arise, while the N-conductive zone 12.2 located under mask 20 corresponds to the originally implanted zone Line type retained. The masks of both islands are now removed, and the island 12 is provided with a mask that also covers the implanted area, while on the island 14 a mask 22 is applied, which is the underlying P-doped Protects area in zone 14.2. The exposed parts of the island 14 are now e.g. subjected to phosphorus ion implantation or diffusion, so that the N + -conducting Areas 14.1 and 1403 are created.
Nachdem auf diese Weise die Drain-, Kanal- und Source-Zonen 12.1, 12.2 bzw. 12.3 in der Insel 12 und die entsprechenden Drain-Kanal- und Source-Zonen 14.1, 14.2 bzw.After the drain, channel and source zones 12.1, 12.2 or 12.3 in the island 12 and the corresponding drain-channel and source zones 14.1, 14.2 or
14.3 in der Insel 14 gebildet worden sind, werden gemäß Fig. 3 alle von vorhergehenden Verfahrensschritten noch vorhandenen Masken von den Inseln abgetragen, und beide Inseln 12 und 14 werden mit Oxid-Schichten 24 bedeckt, nach deren entsprechendem Maskieren darin Kontaktlöcher 26 und 28 geöffnet werden.14.3 have been formed in the island 14, according to FIG. 3, all removed masks from the islands from previous process steps, and both islands 12 and 14 are covered with oxide layers 24, according to their respective Masking contact holes 26 and 28 are opened therein.
Beispiel I Die Fig. 4a und 4b zeigen ein Ausführungsbeispiel des erfindungsgemäßen Bauelements. Hierbei werden,nachdem in den aus Siliziumdioxid bestehenden Isolierschichten 24 Kontaktlöcher 26 und 28 hergestellt worden sind, nur die freigelegten Teile der Drain-Zone 12.1 und der Source-Zone 14.3 siliziert, d.h. einem Verfahrensschritt zum Bilden einer Silizium-Metallverbindung ausgesetzt. Im Ausführungsbeispiel ist ebenso wie in den folgenden Beispielen Platin-Silizid als ohmsches Kontaktmaterial vorgesehen, Selbstverständlich können anstelle von Platin aber auch Metalle wie Palladium, Titan, Zirkon, Kadmium, Vanadium, Niob, Tantal, Chrom, Molybdän, Wolfram oder Nickel verwendet werden. Im Ausführungsbeispiel wird das Bauelement auf einer Temperatur von etwa 2000 C gehalten, während Platin auf die ganze Bauelement-Oberfläche aufgesprüht wird. Bei einem anschließenden Anlassen bzw. Wärmebehandeln reagiert das Platin nur mit dem freigelegten Silizium nicht aber mit der Siliziumdioxid-Schicht 24. Das Anlassen erfolgt in einer inerten Atmosphäre bei einer Temperatur von etwa 7000C. Das in die Kontaktlöwher 26 und 28 gesprühte Platin reagiert nur mit dem Silizium, und derart, daß PtSi-Bereiche 12.4 und 14.4 entstehen, welche fest sind und daher nicht zusammenlaufen oder zu den Rändern der Kontaktlöcher fließen, wie es das flüssige Eutektikum tun würde. Das gesamte auf die Oxid-Schicht 24 aufgesprühte oder unbeabsichtigt dort abgeschiedene Platin wird auf einfache Weise mit Hilfe heißen, konzentrierten Königswassers abgetragen.Example I FIGS. 4a and 4b show an embodiment of the invention Component. Here, after in the insulating layers made of silicon dioxide 24 contact holes 26 and 28 have been made, only the exposed parts of the The drain zone 12.1 and the source zone 14.3 are siliconized, i.e. one process step to form one Exposed silicon-metal compound. In the exemplary embodiment As in the following examples, platinum silicide is used as the ohmic contact material provided, of course, instead of platinum, metals such as Palladium, titanium, zircon, cadmium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten or nickel can be used. In the exemplary embodiment, the component is on a Maintained temperature of about 2000 C, while platinum on the whole component surface is sprayed on. Reacts during subsequent tempering or heat treatment the platinum only with the exposed silicon but not with the silicon dioxide layer 24. Tempering takes place in an inert atmosphere at a temperature of about 7000C. The platinum sprayed into contact louvers 26 and 28 only reacts with the Silicon, and in such a way that PtSi areas 12.4 and 14.4 arise, which are solid and therefore not converge or flow to the edges of the contact holes, like the liquid eutectic would do it. All of it sprayed onto the oxide layer 24 or inadvertently deposited there platinum is in a simple way with the help hot, concentrated aqua regia.
Daraufhin wird ein Polysilizium-Streifen 30 in die Kontaktlöcher hinein und auf der Oxid-Schicht 24 entlang niedergenhlagen, um die Bereiche 1204 und 14.4 zu verbinden und damit einen ohmschen Kontakt zwischen der Drain-Zone 12,1 und der Source-Zone 14.3 zu bilden. Der Hersteller hat nun die Wahl, den Polysilizium-Streifen 30 entweder in Richtung auf P- oder in Richtung auf N-Leitung zu dotieren, da an keinem der silizierten Bereiche 12.4 oder 14.4 ein PN-Übergang entstehen kann.A polysilicon strip 30 is then inserted into the contact holes and deposited along oxide layer 24 to regions 1204 and 14.4 to connect and thus an ohmic contact between the drain zone 12.1 and the Form source zone 14.3. The manufacturer now has the choice, the polysilicon strip 30 to be doped either in the direction of the P or in the direction of the N line, since at a PN junction cannot occur in any of the silicided areas 12.4 or 14.4.
In dem Ausführungsbeispiel gemäß Fig. 4a und 4b sind silizierte Bereiche 12.4 und 14.4 sowohl in der Drain-Zone 12.1 als auch in der Source-Zone 14.3 gebildet.In the exemplary embodiment according to FIGS. 4a and 4b, there are siliconized areas 12.4 and 14.4 formed both in the drain zone 12.1 and in the source zone 14.3.
Es sei daher darauf hingewiesen, daß bei P-dotiertem Polysiliziumstreifen 30 nur der silizierte Bereich 14.4 erforderlich ist, da an der Kontaktfläche zwischen der Drain-Zone 12.1 und dem Polysilizium-Streifen 30 ohnehin kein PN-Übergang entstehen kann, Entsprechend ist bei N-dotiertem Polysilizium-Streifen 30 nur der Silizid-Bereich 12.4 erforderlich, während der silizierte Bereich 14.4 wegfallen kann.It should therefore be noted that in the case of P-doped polysilicon strips 30 only the siliconized area 14.4 is required, since at the contact surface between the drain zone 12.1 and the polysilicon strip 30 in any case no PN junction occurs Correspondingly, only the silicide area is in the case of N-doped polysilicon strips 30 12.4 is required, while the siliconized area 14.4 can be omitted.
Beisiel II Gemäß Fig. 5a und 5b wird das Bauelement nach dem Bilden der Kontaktöffnungen 26 und 28 in den Oxid-Schichten 24 zunächst mit einem Polysilizium-Streifen 30 versehen, um die Drain-Zone 12.1 mit der Source-Zone 14.3 zu verbinden.Example II According to FIGS. 5a and 5b, the component is after forming of the contact openings 26 and 28 in the oxide layers 24 initially with a polysilicon strip 30 provided in order to connect the drain zone 12.1 to the source zone 14.3.
Wenn der Verbindungsstreifen 30 P-dotiert wird, entsteht ein PN-Übergang an der Grenzfläche zwischen der Source-Zone 14.3 und dem Polysilizium-Streifen 30. Erfindungsgemäß wird daher auf die freiliegende Oberfläche des Polysilizium-Streifens 30 Platin aufgesprüht und in einer inerten Atmosphäre solange auf etwa 7000C gehalten, bis das Platin durch den Streifen 30 hindurch in den aktiven Bereich 14.3 eingetrieben ist und der silizierte Bereich 14.5 entsteht. Bei diesem Ausführungsbeispiel schadet es offensichtlich nicht, wenn der Polysilizium-Streifen 30 auf seiner ganzen Länge siliziert wird, denn im Ergebnis wird dadurch lediglich der Ckesamtwiderstand herabgesetzt.When the connection strip 30 becomes P-doped, a PN junction is created at the interface between the source zone 14.3 and the polysilicon strip 30. According to the invention, the exposed surface of the polysilicon strip is therefore applied 30 platinum sprayed on and held in an inert atmosphere at about 7000C, until the platinum is driven through the strip 30 into the active area 14.3 and the siliconized area 14.5 is created. In this embodiment it is harmful it obviously does not, if the polysilicon strip 30 along its entire length is silicized, because as a result only the total resistance is reduced.
Nach dem Silizieren des Streifens 30 oder eines Teiles des letzteren wird jedoch jeder an der Grenzfläche zwischen dem Polysilizium-Streifen 30 und der Source-Zone 14.3 gebildete PN-Übergang mit einem polysilizierten Bereich 14.5 versehen, der den PN-Übergang als Kurzschluß überbrückt.After siliconizing the strip 30 or part of the latter however, each at the interface between the polysilicon strip 30 and the Source zone 14.3 provided the PN junction formed with a polysilicated area 14.5, which bridges the PN junction as a short circuit.
Beispiel III Bei dem Ausführungsbeispiel gemäß Fig, 6a und 6b wird zunächst ein Polysilizium-Streifen 30 auf die Oxid-Schicht 24 aufgebracht, um die Drain-Zone 12.1 mit der Source-Zone 14.3 zu verbinden. Es sei angenommen, daß der Streifen 30 P-dotiert ist.Example III In the embodiment according to FIGS. 6a and 6b first a polysilicon strip 30 is applied to the oxide layer 24 to the To connect the drain zone 12.1 to the source zone 14.3. It is assumed that the Strip 30 is P-doped.
Dieses Ausführungsbeispiel betrifft den Fall, daß der Polysilizium-Streifen 30 nur teilweise in das Kontaktloch 28 oberhalb der Oberfläche des Bereichs 14.3 hineinreicht bzw. das Kontaktloch 28 nur teilweise ausfüllt. Nach dem Herstellen dieser Struktur wird auf das gesamte Bauelement und damit auch in das Kontaktloch 28 oberhalb der Source-Zone 14.3 Platin gesprüht und dann bei etwa 7000C in einer inerten Atmosphäre wärmebehandelt, um den silizierten Bereich 32 zu bilden. Da der silizierte Bereich 32 nur in Silizium oder Polysilizium nicht aber in Siliziumdioxid entsteht, können mit Platin besprühte Oxid-Schichten 24 auf vorbeschriebene Weise leicht entfernt werden, während der gebildete silizierte Bereich 32 als Kurzschluß für jeden Übergang dient, welcher an der Grenzfläche zwischen dem P-dotierten Polysilizium-Streifen 30 und der N-dotierten Drain-Zone 14.3 gebildet sein kann.This embodiment relates to the case that the polysilicon strip 30 only partially into the contact hole 28 above the surface of the area 14.3 extends in or fills the contact hole 28 only partially. After manufacturing this structure is applied to the entire component and thus also to the contact hole 28 above the source zone 14.3 platinum and then sprayed at about 7000C in a heat-treated in an inert atmosphere to form the siliconized region 32. Since the Siliconized area 32 only in silicon or polysilicon but not in silicon dioxide arises, can be sprayed with platinum oxide layers 24 in the manner described above can be easily removed, while the siliconized area 32 formed as a short circuit serves for each junction which is at the interface between the P-doped polysilicon strip 30 and the N-doped drain zone 14.3 can be formed.
Beispiel IV In dem Ausführungsbeispiel gemäß Fig. 7 werden nach dem Bilden der Kontaktlöcher oberhalb der Drain-Zone 12.1 und der Source-Zone 1403 Polysilizium-Streifen 34 und 36 niedergeschlagen, um einen ohmschen Kontakt mit der Source-Zone 14.3 bzw. der Drain-Zone 12.1 herzustellen. Nach einem Maskieren des Streifens 34 wird der Streifen 36 P-dotiert.Example IV In the embodiment according to FIG. 7, according to the Forming the contact holes above the drain zone 12.1 and the source zone 1403 polysilicon strips 34 and 36 are deposited in order to establish an ohmic contact with the source zone 14.3 or to produce the drain zone 12.1. After masking the strip 34, the Strip 36 P-doped.
Nach dem Abtragen der Maske von dem Streifen 34 und dem Maskieren des Streifens 36 wird der Polysilizium-Streifen 34 N-dotiert. Das Ergebnis ist somit ein PN-Übergang 37 an der Stelle, an der die Streifen 34 und 36 aufeinandertreffen. Zum Entfernen dieses unerwünschten PN-Übergangs wird der Bereich zu zonen beiden Seiten siliziert, indem Platin über den Bereich des PN-Übergangs gesprüht und der besprühte Bereich bei etwa 700 0C angelassen bzw. erwärmt wird, bis eine den PN-Übergang 37 als Kurzschluß überbrückende silizierte Zone 38 entsteht.After removing the mask from the strip 34 and the Mask of the strip 36, the polysilicon strip 34 is N-doped. The result is thus a PN junction 37 at the point where the strips 34 and 36 meet. To remove this unwanted PN junction, the area is zoned to both Sides silicided by spraying platinum over the area of the PN junction and the The sprayed area is tempered or heated at around 700 ° C. until one of the PN junction 37 as a short-circuit bridging siliconized zone 38 arises.
Wie die Ausführungsbeispiele zeigen, wird der PN- oder NP-Übergang, der entweder an der Grenzfläche eines P- oder N-dotierten Polysilizium-Streifens und einer N- oder P-dotierten Source- oder Drain-Zone oder an der Grenzfläche von P- und N-dotierten Polysilizium-Streifen entsteht, erfindungsgemäß durch das Herstellen einer niederohmigen, kurz schließenden, silizierten Zone überbrückt bzw. unterdrückt.As the exemplary embodiments show, the PN or NP transition, that at either the interface of a P- or N-doped polysilicon strip and an N- or P-doped source or drain region or at the interface of According to the invention, P- and N-doped polysilicon strips are produced by production a low-resistance, short-circuiting, siliconized zone bridged or suppressed.
Vorstehend wurde die Erfindung am Beispiel des Herstellens des silizierten Bereichs durch Reagieren der beschriebenen Metalle mit Polysilizium erläutert. Der silizierte Bereich kann auch unmittelbar auf bekannte Weise, z.B. durch Aufsprühen, Verdampfen oder chemisches Aufdampfen irgendeines der genannten Silizide hergestellt werden.The invention has been described above using the example of the production of the siliconized Area explained by reacting the metals described with polysilicon. Of the Silicated area can also be used directly in a known manner, e.g. by spraying, Evaporation or chemical vapor deposition of any of the silicides mentioned will.
L e e r s e i t eL e r s e i t e
Claims (6)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US88125578A | 1978-02-27 | 1978-02-27 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE2906249A1 true DE2906249A1 (en) | 1979-08-30 |
| DE2906249B2 DE2906249B2 (en) | 1980-11-13 |
Family
ID=25378092
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE2906249A Ceased DE2906249B2 (en) | 1978-02-27 | 1979-02-19 | Integrated, complementary MOS circuit |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPS592186B2 (en) |
| DE (1) | DE2906249B2 (en) |
| IT (1) | IT1110843B (en) |
| SE (1) | SE438945B (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0043451A2 (en) * | 1980-06-30 | 1982-01-13 | International Business Machines Corporation | Process for selectively forming refractory metal silicide layers on semiconductor devices |
| DE3127996A1 (en) * | 1980-07-15 | 1982-03-04 | Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa | SEMICONDUCTOR DEVICE |
| DE3141195A1 (en) * | 1980-11-07 | 1982-06-24 | Hitachi, Ltd., Tokyo | INTEGRATED SEMICONDUCTOR CIRCUIT AND METHOD FOR THEIR PRODUCTION |
| DE3223858A1 (en) * | 1981-06-26 | 1983-01-13 | Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa | Semiconductor device and method of producing it |
| EP0072522A2 (en) * | 1981-08-19 | 1983-02-23 | Siemens Aktiengesellschaft | Process for manufacturing integrated MOS field effect transistors, particularly circuits having complementary MOS field effect transistors with an additional conductor level comprising metal silicides |
| EP0096734A1 (en) * | 1982-05-31 | 1983-12-28 | Kabushiki Kaisha Toshiba | Stacked complementary metal oxide semiconductor inverter |
| EP0098737A2 (en) * | 1982-06-30 | 1984-01-18 | Fujitsu Limited | Semiconductor device |
| DE3409387A1 (en) * | 1983-03-15 | 1984-09-20 | Canon K.K., Tokio/Tokyo | SEMICONDUCTOR DEVICE |
| DE4121051A1 (en) * | 1991-06-26 | 1993-01-07 | Eurosil Electronic Gmbh | SEMICONDUCTOR ARRANGEMENT AND PRODUCTION METHOD |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57117257A (en) * | 1981-01-13 | 1982-07-21 | Nec Corp | Semiconductor device |
| JPS57199440A (en) * | 1981-06-01 | 1982-12-07 | Mitsubishi Electric Corp | Holder for stator coil |
| JPS5830147A (en) * | 1981-08-18 | 1983-02-22 | Toshiba Corp | Semiconductor device |
| JPS59125640A (en) * | 1982-12-28 | 1984-07-20 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS61150362A (en) * | 1984-12-25 | 1986-07-09 | Toshiba Corp | Manufacture of semiconductor device |
| US4796081A (en) * | 1986-05-02 | 1989-01-03 | Advanced Micro Devices, Inc. | Low resistance metal contact for silicon devices |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE1808926A1 (en) * | 1967-11-14 | 1969-07-17 | Sony Corp | Semiconductor component and method for its manufacture |
| DE1639051B1 (en) * | 1961-12-01 | 1971-06-09 | Western Electric Co | METHOD OF MAKING AN OHM CONTACT ON A SEMICONDUCTOR BODY |
| US3617824A (en) * | 1965-07-12 | 1971-11-02 | Nippon Electric Co | Mos device with a metal-silicide gate |
| US3634929A (en) * | 1968-11-02 | 1972-01-18 | Tokyo Shibaura Electric Co | Method of manufacturing semiconductor integrated circuits |
| DE1764056B1 (en) * | 1967-03-27 | 1972-03-09 | Western Electric Co | METHOD OF MANUFACTURING A SEMICONDUCTOR ARRANGEMENT |
| US3658586A (en) * | 1969-04-11 | 1972-04-25 | Rca Corp | Epitaxial silicon on hydrogen magnesium aluminate spinel single crystals |
| US3753774A (en) * | 1971-04-05 | 1973-08-21 | Rca Corp | Method for making an intermetallic contact to a semiconductor device |
| US4012762A (en) * | 1974-06-24 | 1977-03-15 | Sony Corporation | Semiconductor field effect device having oxygen enriched polycrystalline silicon |
| US4041518A (en) * | 1973-02-24 | 1977-08-09 | Hitachi, Ltd. | MIS semiconductor device and method of manufacturing the same |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5847860B2 (en) * | 1973-06-30 | 1983-10-25 | 株式会社東芝 | Hand tie souchi |
-
1979
- 1979-01-30 IT IT19722/79A patent/IT1110843B/en active
- 1979-02-19 DE DE2906249A patent/DE2906249B2/en not_active Ceased
- 1979-02-21 SE SE7901551A patent/SE438945B/en not_active IP Right Cessation
- 1979-02-23 JP JP54021291A patent/JPS592186B2/en not_active Expired
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE1639051B1 (en) * | 1961-12-01 | 1971-06-09 | Western Electric Co | METHOD OF MAKING AN OHM CONTACT ON A SEMICONDUCTOR BODY |
| US3617824A (en) * | 1965-07-12 | 1971-11-02 | Nippon Electric Co | Mos device with a metal-silicide gate |
| DE1764056B1 (en) * | 1967-03-27 | 1972-03-09 | Western Electric Co | METHOD OF MANUFACTURING A SEMICONDUCTOR ARRANGEMENT |
| DE1808926A1 (en) * | 1967-11-14 | 1969-07-17 | Sony Corp | Semiconductor component and method for its manufacture |
| US3634929A (en) * | 1968-11-02 | 1972-01-18 | Tokyo Shibaura Electric Co | Method of manufacturing semiconductor integrated circuits |
| US3658586A (en) * | 1969-04-11 | 1972-04-25 | Rca Corp | Epitaxial silicon on hydrogen magnesium aluminate spinel single crystals |
| US3753774A (en) * | 1971-04-05 | 1973-08-21 | Rca Corp | Method for making an intermetallic contact to a semiconductor device |
| US4041518A (en) * | 1973-02-24 | 1977-08-09 | Hitachi, Ltd. | MIS semiconductor device and method of manufacturing the same |
| US4012762A (en) * | 1974-06-24 | 1977-03-15 | Sony Corporation | Semiconductor field effect device having oxygen enriched polycrystalline silicon |
Non-Patent Citations (10)
| Title |
|---|
| DE-Z.: Elektronik 1970 H. 1, S. 30 * |
| DE-Z.: Industrie-Elektrik + Elektronik 12. Jhrg. 1967/Nr. B7/8, S. 125-128 * |
| DE-Z.: Philips Technische Rundschau, 32, 1971/72, H. 1, S. 1-12 * |
| DE-Z.: Philips Technische Rundschau, 35, 1975/76, Nr. 7/8, S. 230-239 * |
| US-Z.: IBM Techn. Discl. Bull., Vol. 17, No. 6, Nov. 1974, S. 1831-1833 * |
| US-Z.: J. Electrochemical Soc., Vol. 122, No. 12, Dezember 1975, S. 1714-1718 * |
| US-Z.: SCP and Solid-State Technologie, März 1965,S. 42-44 * |
| US-Z.: Solid State Electronics 1972, Vol. 15, S. 789-799 * |
| US-Z.: Solid State Technology, Bd. 11, 1968, H. 3, S. 36-40 * |
| US-Z.: The Bell System Journal, Bd. XLV, Nr. 2, Februar 1966, S. 233-253 * |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0043451A2 (en) * | 1980-06-30 | 1982-01-13 | International Business Machines Corporation | Process for selectively forming refractory metal silicide layers on semiconductor devices |
| EP0043451A3 (en) * | 1980-06-30 | 1984-07-25 | International Business Machines Corporation | Process for selectively forming refractory metal silicide layers on semiconductor devices |
| DE3127996A1 (en) * | 1980-07-15 | 1982-03-04 | Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa | SEMICONDUCTOR DEVICE |
| US5061983A (en) * | 1980-07-15 | 1991-10-29 | Tokyo Shibaura Denki Kabushiki Kaisha | Semiconductor device having a metal silicide layer connecting two semiconductors |
| DE3141195A1 (en) * | 1980-11-07 | 1982-06-24 | Hitachi, Ltd., Tokyo | INTEGRATED SEMICONDUCTOR CIRCUIT AND METHOD FOR THEIR PRODUCTION |
| US4954871A (en) * | 1981-06-26 | 1990-09-04 | Yoshihisa Mizutani | Semiconductor device with composite electrode |
| DE3223858A1 (en) * | 1981-06-26 | 1983-01-13 | Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa | Semiconductor device and method of producing it |
| EP0072522A2 (en) * | 1981-08-19 | 1983-02-23 | Siemens Aktiengesellschaft | Process for manufacturing integrated MOS field effect transistors, particularly circuits having complementary MOS field effect transistors with an additional conductor level comprising metal silicides |
| EP0072522A3 (en) * | 1981-08-19 | 1983-11-09 | Siemens Aktiengesellschaft | Process for manufacturing integrated mos field effect transistors, particularly circuits having complementary mos field effect transistors with an additional conductor level comprising metal silicides |
| EP0096734A1 (en) * | 1982-05-31 | 1983-12-28 | Kabushiki Kaisha Toshiba | Stacked complementary metal oxide semiconductor inverter |
| EP0098737A3 (en) * | 1982-06-30 | 1985-08-28 | Fujitsu Limited | Semiconductor device |
| EP0098737A2 (en) * | 1982-06-30 | 1984-01-18 | Fujitsu Limited | Semiconductor device |
| DE3409387A1 (en) * | 1983-03-15 | 1984-09-20 | Canon K.K., Tokio/Tokyo | SEMICONDUCTOR DEVICE |
| DE4121051A1 (en) * | 1991-06-26 | 1993-01-07 | Eurosil Electronic Gmbh | SEMICONDUCTOR ARRANGEMENT AND PRODUCTION METHOD |
| US5268323A (en) * | 1991-06-26 | 1993-12-07 | Eurosil Electronic Gmbh | Semiconductor array and method for its manufacture |
Also Published As
| Publication number | Publication date |
|---|---|
| DE2906249B2 (en) | 1980-11-13 |
| SE438945B (en) | 1985-05-13 |
| IT7919722A0 (en) | 1979-01-30 |
| JPS592186B2 (en) | 1984-01-17 |
| SE7901551L (en) | 1979-08-28 |
| IT1110843B (en) | 1986-01-06 |
| JPS54123883A (en) | 1979-09-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE2930630C2 (en) | Semiconductor component and method for its manufacture | |
| DE2640525C2 (en) | Method for manufacturing an MIS semiconductor circuit arrangement | |
| EP0239652B1 (en) | Method of producing a monolithic integrated circuit with at least one bipolar planar transistor | |
| DE69728259T2 (en) | SILICON CARBIDE CMOS AND PRODUCTION METHOD | |
| DE3823270C2 (en) | Transistor, in particular insulating gate bipolar transistor, and method for its production | |
| DE2817430C2 (en) | Process for the production of field effect transistors with an insulated gate electrode | |
| DE2906249A1 (en) | Integrated, complementary MOS circuit - has pairs of active regions of two MOS elements coupled by polycrystalline silicon strip and has short circuit at undesirable junction | |
| DE1944793C3 (en) | Method for manufacturing an integrated semiconductor device | |
| DE19611959C2 (en) | Complementary MOS field effect transistor and manufacturing method therefor | |
| DE3222805A1 (en) | METHOD FOR PRODUCING A MOS CIRCUIT IN INTEGRATED CIRCUIT TECHNOLOGY ON A SILICON SUBSTRATE | |
| DE2718779A1 (en) | MIS SEMICONDUCTOR COMPONENT AND METHOD FOR MANUFACTURING IT | |
| DE2933694A1 (en) | INTEGRATED CIRCUIT | |
| DE2726003A1 (en) | METHOD OF MAKING MIS DEVICES WITH OFFSET GATE | |
| DE19838150A1 (en) | Semiconductor module with series of standard cells | |
| DE3122437A1 (en) | METHOD FOR PRODUCING A MOS COMPONENT | |
| DE2546314A1 (en) | FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD OF MANUFACTURING | |
| DE2422912A1 (en) | INTEGRATED SEMICONDUCTOR CIRCUIT | |
| DE3142448C2 (en) | MOS transistor and process for its manufacture | |
| DE3127996C2 (en) | ||
| DE4121051A1 (en) | SEMICONDUCTOR ARRANGEMENT AND PRODUCTION METHOD | |
| DE3932445C2 (en) | Complementary semiconductor device with an improved isolation area | |
| DE3148323A1 (en) | SEMICONDUCTOR CIRCUIT | |
| DE3103785C2 (en) | ||
| DE1297762B (en) | Junction field effect transistor | |
| DE2044863A1 (en) | Process for the production of Schottky diodes |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| OAP | Request for examination filed | ||
| OD | Request for examination | ||
| 8263 | Opposition against grant of a patent | ||
| 8235 | Patent refused |