DE2930779C2 - Semiconductor device - Google Patents

Semiconductor device

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Publication number
DE2930779C2
DE2930779C2 DE2930779A DE2930779A DE2930779C2 DE 2930779 C2 DE2930779 C2 DE 2930779C2 DE 2930779 A DE2930779 A DE 2930779A DE 2930779 A DE2930779 A DE 2930779A DE 2930779 C2 DE2930779 C2 DE 2930779C2
Authority
DE
Germany
Prior art keywords
gold
germanium
alloy
metal layer
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2930779A
Other languages
German (de)
Other versions
DE2930779A1 (en
Inventor
Masashi Hyogo Awa
Osamu Himeji Hyogo Hattori
Mitsuo Aioi Hyogo Kobayashi
Toshio Tetsuya
Osamu Usuda
Yoshio Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP53091416A external-priority patent/JPS592175B2/en
Priority claimed from JP53091415A external-priority patent/JPS592174B2/en
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Publication of DE2930779A1 publication Critical patent/DE2930779A1/en
Application granted granted Critical
Publication of DE2930779C2 publication Critical patent/DE2930779C2/en
Expired legal-status Critical Current

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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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Description

dadurch gekennzeichnet, daßcharacterized in that

(d) auf einer Oberfläche des Halbleiterelements eine erste Metallschicht (12) aus einem Metall der Gruppe Vanadium, Aluminium, Titan, Chrom, Molybdän und einer Nickel-Chrom-Legierung aufgebracht ist,(d) a first metal layer (12) made of a metal on a surface of the semiconductor element the group vanadium, aluminum, titanium, chromium, molybdenum and a nickel-chromium alloy is upset

(e) auf die erste Metallschicht eine zweite Metallschicht (13) aus einem Metall der Gruppe Kupfer, Legierung auf Kupferbasis, Nickel und Legierung auf Nickelbasis aufgebracht ist und (e) a second metal layer (13) composed of a metal from the group copper, copper-based alloy, nickel and nickel-based alloy is applied to the first metal layer, and

(J) auf die zweite Metallschicht die Gold und Germanium enthaltende Metallschicht als dritte Metallschicht (14) aus einer Gold-Germanium-Legierung oder einer Legierung auf der Basis von Gold-Germanium aufgebracht ist. (J) the metal layer containing gold and germanium is applied to the second metal layer as a third metal layer (14) made of a gold-germanium alloy or an alloy based on gold-germanium.

2. Halbleitervorrichtung nach Anspruch 1, dadurch gekennzeichnet, daß der Germanium-Anteil der Gold-Germanium-Legierung 4 bis 20Gew.-% beträgt2. Semiconductor device according to claim 1, characterized in that the germanium content of the gold-germanium alloy is 4 to 20% by weight

3. Halbleitervorrichtung nach Anspruch 1, dadurch gekennzeichnet, daß die Legierung auf der Basis von Gold-Germanium eine Gold-Germanium-Antimon-Legierung ist, bei der o<;r Germanium-Anteil und der Antimon-Anteil 4 bis 20 Gew.-% bzw. 0,005 bis l,0Gew.-% bezogen auf das Gesamtgewicht von Gold und Germanium betragen.3. A semiconductor device according to claim 1, characterized in that the alloy on the The basis of gold-germanium is a gold-germanium-antimony alloy with a germanium content and the antimony content is 4 to 20% by weight or 0.005 to 1.0% by weight, based on the total weight of gold and germanium.

4. Halbleitervorrichtung nach Anspruch 1, dadurch gekennzeichnet, daß die Legierung auf der Basis von Gold-Germanium eine Gold-Germanium-Gallium-Legierung ist, bei der der Germanium-Anteil und der Gallium-Anteil 4 bis 20 Gew.-% bzw. 0,005 bis l,0Gew.-% bezogen auf das Gesamtgewicht von Gold und Germanium betragen.4. A semiconductor device according to claim 1, characterized in that the alloy on the The basis of gold-germanium is a gold-germanium-gallium alloy in which the germanium content and the gallium content is 4 to 20% by weight or 0.005 to 1.0% by weight, based on the total weight of gold and germanium.

5. Halbleitervorrichtung nach einem der Ansprüche i bis 3, dadurch gekennzeichnet, daß das Halbleiterelement (11) eine auf die dritte Metallschicht (14) aufgelegte vierte Metallschicht (15) aufweist, die aus einem Metall aus der Gruppe Gold, Silber und Platin hergestellt ist.5. Semiconductor device according to one of claims i to 3, characterized in that the Semiconductor element (11) a fourth metal layer (15) placed on the third metal layer (14) which is made from a metal selected from the group consisting of gold, silver and platinum.

6. Halbleitervorrichtung nach Anspruch 1, dadurch gekennzeichnet, daß6. Semiconductor device according to claim 1, characterized in that

die erste Metallschicht (12) eine Dicke von 5 bis 200 nm aufweist,the first metal layer (12) has a thickness of 5 to 200 nm,

die zweite Metallschicht eine Dicke von 30 bis 500 nm undthe second metal layer has a thickness of 30 to 500 nm and

die dritte Metallschicht (14) eine Dicke von 0,8 bis 3,5 μΐη. the third metal layer (14) has a thickness of 0.8 to 3.5 μm.

7. Halbleitervorrichtung nach Anspruch 5, dadurch gekennzeichnet, daß die vierte Metallschicht (15) eine Dicke von 50 bis 500 nm aufweist.7. Semiconductor device according to claim 5, characterized in that the fourth metal layer (15) has a thickness of 50 to 500 nm.

6565

Die Erfindung betrifft eine Halbleitervorrichtung gemäß dem Oberbegriff des Patentanspruchs 1. Eine solche Halbleitervorrichtung ist zum Beispiel aus der DE-AS 14 64 357 bereits bekannt.The invention relates to a semiconductor device according to the preamble of claim 1. A Such a semiconductor device is already known from DE-AS 14 64 357, for example.

Es sind verschiedene Verfahren bekannt, um ein Halbleiterelement aus Silicium (im folgenden »Siliciumchip« genannt) auf einem Träger oder Chipbefestigungsteil zu befestigen.Various methods are known to produce a semiconductor element made of silicon (hereinafter referred to as "silicon chip" called) to be attached to a carrier or chip mounting part.

Aus der DE-AS 16 39 366 ist ein Verfahren zur Herstellung eines Kontakts für Halbleiterbauelemente bekannt Bei diesem wird eine Elektrode Mit einer Goldschicht auf einen Halbleiterkörper aufgelegt, der seinerseits eine Titanschicht und darüber eine Nickelschicht besitzt Die Anordnung wird dann erhitzt, um die drei Schichten zwischen dem Halbleiterkörper und der Elektrode zu verschmelzen. Dabei bildet sich eine einzige einheitliche Schicht aus Gold, Nickel und Titan, und Gold diffundiert durch die Titan- und Nickelschichten in den Halbleiterkörper und bildet ein Eutektikum mit dem Halbleitermaterial. Diese Diffusion ven Gold in Silicium führt zu einer Änderung der Eigenschaften des Halbleiterelements. So verringert das Gold den Widerstand des Siliciums und führt etwa bei Transistoren zur Erhöhung der Kollektor-Emitter-Restspannung. Die Gold-Silicium-Legierung schwächt auch die Stärke der Verbindung und bringt Schwierigkeiten beim Teilen des Chips mit sich.DE-AS 16 39 366 discloses a method for producing a contact for semiconductor components known In this case, an electrode with a gold layer is placed on a semiconductor body, the in turn has a titanium layer and a nickel layer over it. The assembly is then heated to produce the to fuse three layers between the semiconductor body and the electrode. This creates a single uniform layer of gold, nickel and titanium, and gold diffuses through the titanium and nickel layers into the semiconductor body and forms a eutectic with the semiconductor material. This diffusion ven gold in Silicon leads to a change in the properties of the semiconductor element. So the gold reduces that Resistance of silicon and leads to an increase in the residual collector-emitter voltage in transistors, for example. The gold-silicon alloy also weakens the strength the connection and brings difficulties in dividing the chip.

Aus der DE-AS 14 64 357 ist ein Verfahren zur Herstellung eines olanschen Kontaktes zwischen einem Silicium-Halbleiterkörper und einem metallischen Träger bekannt. Dabei wird der mit Germanium beschichtete Halbleiterkörper mit dem mit Gold beschichteten Träger in Berührung gebracht und anschließend zur Bildung einer Gold-Germanium-Legierung erhitzt. Die Stärke einer von einer Gold-Germanium-Legierung hergestellten Verbindung ist jedoch unzureichend. Zwar diffundiert in diesem Fall das Gold in geringerem Ausmaß in den Halbleiterkörper als es bei der Verwendung von elementarem Gold gemäß dem vorerwähnten Stand der Technik der Fall ist, da jedoch die Gold-Germanium-Legieiing w.imittelbar auf dem Halbleiterkörper liegt, kann immerhin soviel Gold in das Silicium diffundieren, daß auch bei diesem Stand der Technik Nachteile auftreten.From DE-AS 14 64 357 a method for producing an Olan contact between a Known silicon semiconductor body and a metallic carrier. The coated with germanium is used Brought semiconductor body with the gold-coated carrier in contact and then to Heated formation of a gold-germanium alloy. The strength of a gold-germanium alloy however, the connection established is insufficient. In this case the gold diffuses to a lesser extent Extent in the semiconductor body than when using elemental gold according to the The aforementioned prior art is the case, however, since the gold-germanium alloy is directly based on the Semiconductor body is, after all, so much gold can diffuse into the silicon that even with this state of the Technology disadvantages occur.

Aufgabe dieser Erfindung ist eine Halbleitervorrichtung, bei der das Halbleiterelement auf dem Chipbefestigungsteil exakt positioniert ist, das mit geringen Kosten hergestellt werden kann und das eine starke Bindung zwischen dem Halbleiterelement und dem Chipbefestigungsteil aufweist.The object of this invention is a semiconductor device in which the semiconductor element is on the die attach part is precisely positioned, which can be produced at low cost and which has a strong bond having between the semiconductor element and the die attach part.

Die Erfindung ist durch die Merkmale des Anspruches 1 gekennzeichnet. Vorteilhafte Ausgestaltungen der Erfindung sind den Unteransprüchen zu entnehmen.The invention is characterized by the features of claim 1. Advantageous configurations the invention can be found in the subclaims.

Als Legierung auf Kupferbasis und als Legierung auf Nickelbasis, d. h. als Material der zweiten Metallschicht, können eine Kupfer-Nickel-Legierung und eine Nickel-Chrom-Legierung verwendet werden. Als Legierung auf Gold-Germanium-Basis, d. h. als Material der dritten Metallschicht, kann eine Gold-Germanium-Antimon-Legierung oder eine Gold-Germanium-Gallium-Legierung verwendet werden. Das Antimon in der Gold-Germanium-Antimon-Legierung dient dazu, die Kollektor-Emitter-Sättigungsspannung V«, der Halbleitervorrichtung herabzusetzen.As a copper-based alloy and a nickel-based alloy, i. H. as the material of the second metal layer, a copper-nickel alloy and a nickel-chromium alloy can be used. As an alloy based on gold-germanium, d. H. A gold-germanium-antimony alloy can be used as the material of the third metal layer or a gold-germanium-gallium alloy can be used. The antimony in the gold-germanium-antimony alloy serves to set the collector-emitter saturation voltage V «, of the semiconductor device to belittle.

Wird eine Gold-Germanium-Antimon-Legierung auf einer Nickelschicht oder einer Legierungsschicht auf der Basis von Nickel abgeschieden, dann wird zuerst Antimon abgeschieden, da der Dampfdruck von Antimon höher als der von Gold oder Germanium ist.A gold-germanium-antimony alloy is based on a nickel layer or an alloy layer the base of nickel is deposited, then antimony is deposited first, as the vapor pressure of Antimony is higher than that of gold or germanium.

Das niedergeschlagene Antimon reagiert mit Nickel in der Weise, daß es eine Erhöhung des thermischen Widerstandes Ra, der Halbleitervorrichtung verursacht Um diese Reaktion zwischen Nickel und Antimon zu vermeiden, kann zwischen der Nickelschicht bzw. der Legierungsschicht auf Nickelbasis und der Gold-Germanium-Antimon-Schicht Gold, Germanium oder eine Gold-Germanium-Legierung gebildet werden.The deposited antimony reacts with nickel in such a way that it causes an increase in the thermal resistance Ra of the semiconductor device. Layer gold, germanium or a gold-germanium alloy can be formed.

Ferner kann zwischerr der dritten und der vierten Metallschicht ebenfalls eine Gold-Germanium-Schicht '" gebildet werden.Furthermore, a gold-germanium layer can also be used between the third and fourth metal layers. are formed.

Vorzugsweise liegt der Germanium-Anteil in der Gold-Germanium-Legierung im Bereich zwischen 4 und 20Gew.-%. Ist der Germanium-Anteil geringer als 4 Gew.-%, dann wird die Legierung so weich, daß das >5 Schneiden in Würfel schwierig wird. Obersteigt der Anteil 20 Gew.-%, dann kann die dritte Metallschicht keine ausreichende Bindung mehr zwischen dem Halbleiterelement und dem Chipbefestigungsteil herstellen. Vorzugsweise sollte der Germanium-Anteil im 2I) Bereich zwischen 6 und 12Gew.-% liegen. Am vorteilhaftesten ist es, wenn er bei Ϊ2 Gew.-°/o liegt, so daß ein Gold-Germanium-Eutektikum gel-ildet wird. Der Antimon-Anteil der Gold-Germanium-Antimon-Legierung liegt vorzugsweise im Bereich zwischen 0,005 und 1,0 Gew.-%, beruhend auf der Menge an Gold-Germanium. Am vorteilhaftesten ist es, wenn der Antimon-Anteil im Bereich zwischen 0,03 bis 0,2Gew.-% liegt Die erste Metallschicht sollte 5 bis 200 nm dick sein, die zweite Metallschicht 30 bis 500 nm, die dritte Metall- »> schicht 0,8 bis 33 μπι und die vierte Metallschicht 50 bis 500 nm.The germanium content in the gold-germanium alloy is preferably in the range between 4 and 20% by weight. If the germanium content is less than 4% by weight, the alloy becomes so soft that it is difficult to cut > 5 into cubes. If the proportion exceeds 20% by weight, the third metal layer can no longer establish a sufficient bond between the semiconductor element and the chip mounting part. The germanium content in the 2I) range should preferably be between 6 and 12% by weight. It is most advantageous if it is Ϊ2% by weight, so that a gold-germanium eutectic is gel-ied. The antimony content of the gold-germanium-antimony alloy is preferably in the range between 0.005 and 1.0% by weight, based on the amount of gold-germanium. On vorteilhaftesten it is when the antimony content in the range 0.03 to 0,2Gew .-%, the first metal layer should be 5 to 200 nm thick, the second metal layer 30 to 500 nm, said third metal "'layer 0.8 to 33 μm and the fourth metal layer 50 to 500 nm.

Die Erfindung wird durch Ausführungsbeispiele anhand von 5 Figuren näher erläutert Es zeigtThe invention is explained in more detail by means of exemplary embodiments with reference to 5 figures

F:g. 1 eine Querschnittsansicht eines Halbleiterele- *> ments gemäß dieser Erfindung:Q: g. 1 is a cross-sectional view of a semiconductor element ments according to this invention:

F i g. 2 eine Querschnittsansicht einer Halbleitervorrichtung gemäß dieser Erfindung, bei der auf einem Chipbefestigungsteil ein Siliciumchip befestigt ist;F i g. 2 is a cross-sectional view of a semiconductor device according to this invention, in which on a Chip mounting part a silicon chip is mounted;

Fig.3 ein Diagramm, das die Verteilung des ·"> thermischen Widerstandes in einer erfindungsgemäßen Halbleitervorrichtung zeigt; und3 is a diagram showing the distribution of the · "> shows thermal resistance in a semiconductor device according to the invention; and

F ig. 4 eine Querschnittsansicht einer weiteren Halbleitervorrichtung.Fig. 4 is a cross-sectional view of another semiconductor device.

Es werden nun anhand der Zeichnung mehrere ·*' Beispiele dieser Erfindung erläutertUsing the drawing, several * ' Examples of this invention illustrated

Beispiel 1example 1

Wie in F i g. 1 dargestellt, wurde eine erste Metallschicht 12 von ungefähr 30 nm Dicke aus Vanadium, und '·" damit geeignet auf einer Siliciumschicht gut befestigt zu werden, auf einer Oberfläche eines Halbleiterelements 11 mit einem Siliciumsubrtrat, in dem PNP-Transistorchips 11a, 116, lic und Umgebildet wurden, aus der Gasphase abgeschieden. Auf der ersten Metallschicht 12 5' wurde eine zweite- Metallschicht 13 aufgedampft, die aus Nickel hergestellt war und eine Dicke von etwa 100 nm hatte. Auf der zweiten Metallschicht 13 wurde eine dritte Metallschicht 14 aufgedampft bzw. aus der Gasphase abgeschieden, die aus einer Gold-Germani- 6n um-Legierung (Gerrnanium-Anteil: 12Gew.-°/o) hergestellt war und eine Dicke von etwa 1 μηι hatte. Das Halbleiterelement 11 wurde dann mittels eines Diamantschneiders auf der anderen Oberfläche angerissen. Danach wurde es in Chips geteilt. Jedes Chip wurde auf ·" einem silberplattierten Leiterrahmen 2 befestigt, wie dies in F ig. 4 dargestellt ist, wobei die dritte Metallschicht 14 als LiM'iHaterial diente. Auf diese Weise wurden Halbleitervorrichtungen, von denen jede ein Halbleiterchip enthielt hergestelltAs in Fig. 1, a first metal layer 12 of about 30 nm thickness of vanadium, and '· "suitable for being well fixed on a silicon layer, was on a surface of a semiconductor element 11 with a silicon substrate in which PNP transistor chips 11a, 116, lic A second metal layer 13, which was made of nickel and had a thickness of about 100 nm, was vapor-deposited on the first metal layer 12 5 '. A third metal layer 14 was vapor-deposited or deposited from the gas phase consisting of a gold-Germanischer to alloy 6n. (Gerrnanium content: 12Gew.- ° / o). was prepared and had μηι a thickness of about 1, the semiconductor element 11 was then purified by a diamond cutter on the Then it was divided into chips. Each chip was mounted on a silver-plated lead frame 2, as shown in FIG. 4 is shown, the third metal layer 14 serving as LiM'i material. In this way, semiconductor devices each including a semiconductor chip were manufactured

Die Ausbeute war größer als bei den nach bekannten Verfahren hergestellten Produkten. Außerdem zeigten die Vorrichtungen eine niedrigere Kollektor-Emitter-Sättigungsspannung Va* und einen niedrigeren thermischen Widerstand Ra, als die nach bekannten Verfahren hergestellten Halbleitervorrichtungen. Genauer gesagi lag Vas der Vorrichtungen zwischen 0,15 und 020 Volt, während Vc0 der nach bekannten Verfahren hergestellten Halbleitervorrichtungen zwischen 0,2 und 03 Volt lag. Fig.3 zeigt die Verteilung des thermischen Widerstandes in den Halbleitervorrichtungen A\ und /4,2, die nach bekannten Verfahren hergestellt worden sind, sowie in der Halbleitervorrichtung B gemäß Beispiel 1.The yield was greater than that of the products made by known processes. In addition, the devices exhibited a lower collector-emitter saturation voltage Va * and a lower thermal resistance Ra than the semiconductor devices manufactured by known methods. More precisely, Vas of the devices was between 0.15 and 020 volts, while Vc 0 of the semiconductor devices manufactured by known methods was between 0.2 and 03 volts. 3 shows the distribution of the thermal resistance in the semiconductor devices A \ and / 4, 2, which have been manufactured by known methods, and in the semiconductor device B according to Example 1.

Beispiel 2Example 2

Es wurden in der gleichen Weise wie bei Beispiel 1 Halbleitervorrichtungen hergestellt mit der Ausnahme, daß in dem Siliciumsubstrat NPN-Transistorchips gebildet wurden und die erste Metallschicht, die zweite Metallschicht und die dritte MertjJschicht aus Titan, Kupfer bzw. einer Gold-Germanium-Antimon-Legierung (Antimon-Anteil: 0,1 Gew.-% beruhend auf der Menge an Gold-Germanium) hergestellt waren.Semiconductor devices were manufactured in the same manner as in Example 1, except that that in the silicon substrate NPN transistor chips were formed and the first metal layer, the second Metal layer and the third layer of titanium, Copper or a gold-germanium-antimony alloy (Antimony content: 0.1% by weight based on the amount of gold-germanium).

Die Ausbeute war höher als bei den nach bekannten Verfahren hergestellten Erzeugnissen. Ähnlich wie bei Beispiel 1 zeigten die Halbleitervorrichtungen eine kleinere Kollektor-Emitter-Sättigungsspannung Vm und einen kleineren thermischen V/iderstand R,h als die nach bekannten Verfahren hergestellten Halbleitervorrichtungen. Der thermische Widerstand Ra, variierte nur ein wenig von Vorrichtung zu Vorrichtung. Zufolge des Antimon-Anteils in der Gold-Germanium-Antimon-Legierung war die Spannung V«j niedriger als bei den Halbleitervorrichtungen nach Beispiel 1.The yield was higher than that of the products made by known processes. Similar to Example 1, the semiconductor devices exhibited a smaller collector-emitter saturation voltage V m and a smaller thermal resistance R, h than the semiconductor devices manufactured by known methods. The thermal resistance Ra varied only a little from device to device. As a result of the antimony content in the gold-germanium-antimony alloy, the voltage V «j was lower than in the case of the semiconductor devices according to Example 1.

Beispiel 3Example 3

Es wurden in der gleichen Weise wie bei Beispiel 1 Halbleitervorrichtungen hergestellt mit der Ausnahme, daß, wie in Fig.5 dargestellt, auf die dritte Metallschicht 14 eine vierte Metallschicht 15 aus Gold, deren Dicke 50 nm betrug, aufgedampft wurde. Die vierte Metallschicht 15 verhinderte eine Oxidation der dritten Metallschicht 14. Die Bindung zwischen der dritten Metallschicht 14 und dem Leiterrahmen 2 wurde deshalb nicht so stark beeinträchtigt.Semiconductor devices were manufactured in the same manner as in Example 1, except that, as shown in Fig. 5, a fourth metal layer 15 made of gold, the thickness of which was 50 nm, was evaporated on the third metal layer 14. The fourth metal layer 15 prevented the third metal layer 14 from being oxidized. The bond between the third metal layer 14 and the lead frame 2 was therefore not so badly impaired.

Die Ausbeute war höher als bei nach bekannten Verfahren hergestellten Erzeugnissen. Ähnlich wie bei Beispiel 1 zeigten die Halbleitervorrichtungen eine niedrigere Kollektor-Emitter-Sättigungsspannung Vc„ und einen niedrigeren thermischen Widerstand Ra, als die nach bekannten Verfahren hergestellten Halbleitervorrichtungen. Der thermische Widerstand Ra, variierte r:ur wenig von Vorrichtung zu Vorrichtung.The yield was higher than that of products made by known processes. Similar to Example 1, the semiconductor devices exhibited a lower collector-emitter saturation voltage V c "and a lower thermal resistance Ra than the semiconductor devices produced by known methods. The thermal resistance Ra varied very little from device to device.

Beispiel 4Example 4

Es wurden in der gleichen Weise wie bei Beispiel 2 Halbleitervorrichtungen hergestellt, mit der Ausnahme, daß. wie in Fig 5 dargestellt, auf die dritte Metallschicht 14 eine vierte Metallschicht 15 aus Gold, die eine Dicke von 50 nm aufwies, aufgedampft wurde. Die vierte Metallschicht 15 verhinderte eine Oxidation der dritten Metallschicht 14. Die Bindung zwischen der dritten Metallschicht 14 und dem Leiterrahmen 2 wurde deshalb nicht ungürstig beeinflußt.Semiconductor devices were manufactured in the same manner as in Example 2, except that that. as shown in Fig. 5, onto the third metal layer 14 a fourth metal layer 15 made of gold, which had a thickness of 50 nm, was vapor-deposited. the fourth metal layer 15 prevented oxidation of the third metal layer 14. The bond between the third metal layer 14 and the lead frame 2 was therefore not adversely affected.

Die Ausbeute war höher als bei den nach bekannten Verfahren hergestellten Erzeugnissen. Wie bei Bei-The yield was higher than that of the products made by known processes. As with

spiel 1 zeigten die Halbleitervorrichtungen eine niedrigere Kollektor-Emitter-Sättigungsspannung V„s und einen niedrigeren thermischen Widerstand /?,/, als die nach bekannten Verfahren hergestellten Halbleitervorrichtungen. Der thermische Widerstand R,h variierte nur etwas von Vorrichtung zu Vorrichtung. Zufolge des Antimon-Anteils in der Gold-Germanium-Antimon-Legierung war die Spannung V^ niedriger als bei den nach den Beispielen 1 und 3 hergestellten Halbleitervorrichtungen. Game 1, the semiconductor devices exhibited a lower collector-emitter saturation voltage V "s and a lower thermal resistance /?, /, than those produced by known processes semiconductor devices. The thermal resistance R, h varied only slightly from device to device. As a result of the antimony content in the gold-germanium-antimony alloy, the voltage V ^ was lower than in the case of the semiconductor devices manufactured according to Examples 1 and 3.

Die beanspruchte Halbleitervorrichtung weist die folgenden Vorteile auf:The claimed semiconductor device has the following advantages:

Da anstelle einer Goldfolie eine extrem kleine Menge an einer Gold-Germanium-Legierung ver- r> wendet wird, um die Siliciumchips auf den Chipbefestigungsteilen zu befestigen, werden die Chips so exakt positioniert, daß beim Anbringen der Drähte keine Schwierigkeiten entstehen.Since, instead of a gold foil, an extremely small amount of a gold-germanium alloy is used is used to mount the silicon chips on the chip mounting parts, the Chips positioned so precisely that no difficulties arise when attaching the wires.

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rensschritt eine Goldfolie auf einem Chipbefestigungsteil zu plazieren oder eine Einrichtung zur Durchführung dieses Vorgangs nicht erforderlich.The step was to place a gold foil on a die attach part or a device for It is not necessary to perform this process.

3. Da die Menge an Gold, das in Form einer Gold-Germanium-Legierung verwendet wird, au- -'"> ßerordentlich gering ist, kann die Vorrichtung mit niedrigen Kosten hergestellt werden.3. Since the amount of gold that is used in the form of a gold-germanium alloy is au- '"> is extremely small, the device can be manufactured at a low cost.

4. Da zwischen ein Siliciumsubstrat und eine Gold-Germanium-Legierungsschicht Metallschichten eingefügt werden, die gut sowohl mit Silicium als auch mit der Gold-Germanium-Legierung verbunden werden können, wird eine ausreichend starke Bindung zwischen dem Siliciumchip und dem Chipbefestigungsteil erzielt, wodurch die Zuverlässigkeit der Vorrichtung verbessert wird.4. As between a silicon substrate and a gold-germanium alloy layer Metal layers are inserted that bond well with both silicon and the gold-germanium alloy a sufficiently strong bond between the silicon chip and the Chip mounting part achieved, thereby improving the reliability of the device.

5. Da als Lötmaterial eine Gold-Germanium-Legierung anstelle einer Gold-Silicium-Legierung verwendet wird, kann das Siliciumsubstrat auf einfache Weise in Chips unterteilt werden und das Siliciumsubstrat kann auf der oberen Fläche längs Würfellinien angerissen werden, nicht auf den Legierungsschichten. Die Verwendung der GoId-Germanium-Legierung erleichtert das Brechen des Siliciumsubstrats in Chips aus dem folgenden Grund. Der Siliciumgehalt in der eutektischen Gold-Silicium-Verbindung beträgt 2,85 Gew.-°/o, während der Germaniumgehalt in der eutektischen Gold-Germanium-Verbindung 12 Gew.-°/o beträgt. Die spezifischen Dichten von Gold, Silicium und Germanium sind 19,3; 2,42 bzw. 5,46. Somit nimmt volumenmäßig Silicium 19% der eutektischen Gold-Silicium-Legierung ein, während Germanium 33% der Gold-Germanium-Legierung einnimmt. Offensichtlich ist damit volumenmäßig der Goldgehalt in der eutektischen Gold-Germanium-Legierung viel kleiner als in der eutektischen Gold-Siliciurn-Legierung. 5. Da uses a gold-germanium alloy instead of a gold-silicon alloy as the soldering material becomes, the silicon substrate can be easily divided into chips and that The silicon substrate can be scribed along cube lines on the upper surface, not on the Alloy layers. The use of the gold germanium alloy makes it easier to break the Silicon substrate in chips for the following reason. The silicon content in the eutectic Gold-silicon compound is 2.85% by weight, while the germanium content in the eutectic Gold-germanium compound is 12% by weight. The specific densities of gold, silicon and Germanium are 19.3; 2.42 and 5.46, respectively. Thus, silicon takes up 19% of the eutectic by volume Gold-silicon alloy, while germanium makes up 33% of the gold-germanium alloy. Obviously, in terms of volume, the gold content in the eutectic gold-germanium alloy is thus much smaller than in the eutectic gold-silicon alloy.

Im allgemeinen wird das Metall aus der Gasphase unter einem Druck von 13,33 bis 1,333 Pa niedergeschlagen bzw. abgeschieden. Die Temperatur, bei der Gold einen derartigen Dampf- bzw. Gasdruck aufweist, ist nahezu gleich der Temperatur, bei der Germanium einen solchen Dampfdruck hat. Mit anderen Worten sind die Dampfdrücke von Gold und Germanium bei einer für die Dampfabsche'.üimg von Gold und Germanium geeigneten Temperatur nahezu gleich groß. Anders als bei Gold-Silicium oder Gold-Antimon kann Gold-Germanium leicht ohne fraktionelles Verdampfen aufgedampft werden. Zum Beispiel hat der Dampfdruck von Gold und Germanium bei 2000 K den Wert 73,33 Pa. Der Dampfdruck von Silicium hat bei 2000 K einen Wert von 3.999 Pa.In general, the metal is released from the gas phase under a pressure of 13.33 to 1.333 Pa dejected or separated. The temperature at which gold generates such a vapor resp. Has gas pressure is almost equal to the temperature at which germanium has such a vapor pressure Has. In other words, the vapor pressures of gold and germanium are at one for vapor separation temperature suitable for gold and germanium is almost the same. Unlike gold-silicon or gold-antimony, gold-germanium can easily vaporized without fractional evaporation. For example, the vapor pressure of gold and germanium is 2000K the value 73.33 Pa. The vapor pressure of silicon at 2000 K has a value of 3,999 Pa.

Hierzu 2 Blatt ZeichnungenFor this purpose 2 sheets of drawings

Claims (1)

Patentansprüche:Patent claims: 1. Halbleitervorrichtung, umfassend:1. A semiconductor device comprising: (a) einen Träger (2),(a) a carrier (2), (b) ein auf diesem angebrachtes Halbleiterelement (11) und(b) a semiconductor element (11) mounted thereon and (c) zwischen dem Halbleiterelement und dem Träger eine Gold und Germanium enthaltende Metallschicht (14),(c) a gold and germanium containing between the semiconductor element and the carrier Metal layer (14),
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