DE2967321D1 - High density memory system - Google Patents

High density memory system

Info

Publication number
DE2967321D1
DE2967321D1 DE7979901181T DE2967321T DE2967321D1 DE 2967321 D1 DE2967321 D1 DE 2967321D1 DE 7979901181 T DE7979901181 T DE 7979901181T DE 2967321 T DE2967321 T DE 2967321T DE 2967321 D1 DE2967321 D1 DE 2967321D1
Authority
DE
Germany
Prior art keywords
high density
memory system
density memory
memory
density
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE7979901181T
Other languages
English (en)
Inventor
William Pearson Ward
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NCR International Inc
Original Assignee
NCR Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NCR Corp filed Critical NCR Corp
Application granted granted Critical
Publication of DE2967321D1 publication Critical patent/DE2967321D1/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
DE7979901181T 1978-09-01 1979-08-28 High density memory system Expired DE2967321D1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/939,297 US4183095A (en) 1978-09-01 1978-09-01 High density memory device
PCT/US1979/000675 WO1980000632A1 (en) 1978-09-01 1979-08-28 High density memory system

Publications (1)

Publication Number Publication Date
DE2967321D1 true DE2967321D1 (en) 1985-01-17

Family

ID=25472902

Family Applications (1)

Application Number Title Priority Date Filing Date
DE7979901181T Expired DE2967321D1 (en) 1978-09-01 1979-08-28 High density memory system

Country Status (5)

Country Link
US (1) US4183095A (de)
EP (1) EP0016827B1 (de)
JP (1) JPS6321280B2 (de)
DE (1) DE2967321D1 (de)
WO (1) WO1980000632A1 (de)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4281398A (en) * 1980-02-12 1981-07-28 Mostek Corporation Block redundancy for memory array
CA1168377A (en) * 1980-04-25 1984-05-29 Michael L. Ziegler Data processing system having a memory system which utilizes a cache memory and unique pipelining techniques for providing access thereto
US4471243A (en) * 1982-07-26 1984-09-11 Rca Corporation Bidirectional interface
US4535428A (en) * 1983-03-10 1985-08-13 International Business Machines Corporation Multi-port register implementations
US4577292A (en) * 1983-05-31 1986-03-18 International Business Machines Corporation Support circuitry for multi-port systems
US4558433A (en) * 1983-05-31 1985-12-10 International Business Machines Corporation Multi-port register implementations
US4616347A (en) * 1983-05-31 1986-10-07 International Business Machines Corporation Multi-port system
US4577293A (en) * 1984-06-01 1986-03-18 International Business Machines Corporation Distributed, on-chip cache
US4823324A (en) * 1985-09-23 1989-04-18 Ncr Corporation Page mode operation of main system memory in a medium scale computer
JPS62287499A (ja) * 1986-06-06 1987-12-14 Fujitsu Ltd 半導体メモリ装置
JPH01100788A (ja) * 1987-10-13 1989-04-19 Hitachi Ltd 半導体集積回路装置
US6112287A (en) 1993-03-01 2000-08-29 Busless Computers Sarl Shared memory multiprocessor system using a set of serial links as processors-memory switch
JP2923786B2 (ja) * 1988-03-18 1999-07-26 日立マクセル株式会社 半導体ファイルメモリ及びそれを用いる記憶システム
US5086388A (en) * 1988-03-18 1992-02-04 Hitachi Maxell, Ltd. Semiconductor serial/parallel-parallel/serial file memory and storage system
US6324120B2 (en) 1990-04-18 2001-11-27 Rambus Inc. Memory device having a variable data output length
US6751696B2 (en) * 1990-04-18 2004-06-15 Rambus Inc. Memory device having a programmable register
IL96808A (en) 1990-04-18 1996-03-31 Rambus Inc Introductory / Origin Circuit Agreed Using High-Performance Brokerage
US5995443A (en) * 1990-04-18 1999-11-30 Rambus Inc. Synchronous memory device
US6810449B1 (en) 1995-10-19 2004-10-26 Rambus, Inc. Protocol for communication with dynamic memory
US6470405B2 (en) * 1995-10-19 2002-10-22 Rambus Inc. Protocol for communication with dynamic memory
US5949254A (en) * 1996-11-26 1999-09-07 Micron Technology, Inc. Adjustable output driver circuit
US5838177A (en) * 1997-01-06 1998-11-17 Micron Technology, Inc. Adjustable output driver circuit having parallel pull-up and pull-down elements
US6266379B1 (en) 1997-06-20 2001-07-24 Massachusetts Institute Of Technology Digital transmitter with equalization
US6401167B1 (en) * 1997-10-10 2002-06-04 Rambus Incorporated High performance cost optimized memory
US6343352B1 (en) * 1997-10-10 2002-01-29 Rambus Inc. Method and apparatus for two step memory write operations
US6178532B1 (en) 1998-06-11 2001-01-23 Micron Technology, Inc. On-chip circuit and method for testing memory devices
US8391039B2 (en) * 2001-04-24 2013-03-05 Rambus Inc. Memory module with termination component
US6675272B2 (en) * 2001-04-24 2004-01-06 Rambus Inc. Method and apparatus for coordinating memory operations among diversely-located memory components
US7301831B2 (en) 2004-09-15 2007-11-27 Rambus Inc. Memory systems with variable delays for write data signals
US9672169B2 (en) * 2010-06-30 2017-06-06 Texas Instruments Incorporated Dual in line memory module with multiple memory interfaces

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3969706A (en) * 1974-10-08 1976-07-13 Mostek Corporation Dynamic random access memory misfet integrated circuit
US4024512A (en) * 1975-06-16 1977-05-17 Fairchild Camera And Instrument Corporation Line-addressable random-access memory
JPS5240035A (en) * 1975-09-25 1977-03-28 Nippon Telegr & Teleph Corp <Ntt> Memory equipment using electric charge transfer element
US4159541A (en) * 1977-07-01 1979-06-26 Ncr Corporation Minimum pin memory device

Also Published As

Publication number Publication date
JPS55500611A (de) 1980-09-04
EP0016827B1 (de) 1984-12-05
US4183095A (en) 1980-01-08
EP0016827A4 (de) 1981-10-27
JPS6321280B2 (de) 1988-05-06
WO1980000632A1 (en) 1980-04-03
EP0016827A1 (de) 1980-10-15

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Legal Events

Date Code Title Description
8320 Willingness to grant licences declared (paragraph 23)
8327 Change in the person/name/address of the patent owner

Owner name: NCR INTERNATIONAL INC., DAYTON, OHIO, US

8328 Change in the person/name/address of the agent

Free format text: KAHLER, K., DIPL.-ING., 8948 MINDELHEIM KAECK, J., DIPL.-ING. DIPL.-WIRTSCH.-ING., 8910 LANDSBERG FIENER, J., PAT.-ANWAELTE, 8948 MINDELHEIM

8327 Change in the person/name/address of the patent owner

Owner name: AT&T GLOBAL INFORMATION SOLUTIONS INTERNATIONAL IN

8327 Change in the person/name/address of the patent owner

Owner name: NCR INTERNATIONAL, INC. (N.D.GES.D.STAATES DELAWAR

8339 Ceased/non-payment of the annual fee