DE3001331A1 - Serial transmission of data from and/or to motor vehicle - using microprocessor connected to interface for vehicle sensors and RAM and ROM - Google Patents

Abstract

The equipment monitors or tests motor vehicles when operating on load. Faults are detected. In the vehicle is a microprocessor unit (15) which is connected to an input/output interface unit (18) with the vehicle sensors, and to a r.a.m. (16) and r.o.m. (17). Connection is by parallel signal bus (20) and control bus (19). Output across the transmitter-receiver interface (22) is by parallel/series converter (21) controlled by the processor (15). The receiver (28) feeds a series/parallel converter (27) which in turn supplies the v.d.u. (26) or other similar appts. Connection is either by one lead, in which case a start bit sequence of each transmitted word is used to synchronise the receiver, or by a two wire system in which the second wire (32) is used for synchronising the read out of the parallel/series converter (21) with the receiver.

Description

Device for the serial transmission of data

in and / cler from a motor vehicle prior art In the course of the ever more extensive data processing of operating parameters of an internal combustion engine It is becoming more and more urgent, individual data, intermediate values or error codes on request to an external signal processing or display unit. For example instantaneous values of the speed, the temperature, the load or error codes in the Be interesting as part of a self-test of the system. This is where the problem arises the simplest possible decoupling of this data from the respective memories the data bus. Such transmission systems are known in principle.

With them, the data word is read into a shift register whose Content is then transmitted serially.

In the known system, the clock frequency of the system corresponds those of the transmission and receiving unit. That there are synchronization problems occur and as a result there are sources of interference, makes sense. task The invention is therefore intended for series use and therefore as possible price to create inexpensive data transmission equipment that is as possible works universally and autonomously. Above all, the aim is to keep it as low as possible Number of lines between the data processing system and the respective receiving system respected. Furthermore, the synchronization problem must be as simple as possible be solved.

Advantages of the invention The proposed device for serial Transmission of data in digital form with the features of the main claim solves this problem in a convincing way.

It has been found to be particularly advantageous if the the transmission controlling clock frequency in the detached from the data processing system external unit is generated, so that the data transmission of the respective secondary Unit can be individually adapted (two-line system).

At least two different systems related to the serial Clock transmissions are conceivable. On the one hand, data and clock are transmitted over two separate lines transmitted and on the other hand the transmission takes place over only one line, whereby then the information for the synchronization of the receiver-side clock frequency must precede the actual data word. This is done in a particularly advantageous manner Via the length of the start bit preceding the data word. The receiving The unit can thus adapt itself to the clock frequency of the sending unit. A particularly advantageous embodiment does not use any logic modules, i.e. no hardware effort required, but rather generates what is to be transmitted through program commands Data telegram at the serial output of an existing computer unit (microprocessor) Further advantages of the invention emerge in connection with the subclaims from the following description and the drawings of exemplary embodiments.

Drawing Examples of the invention are shown in the drawing and are described and explained in more detail below.

FIG. 1 shows a rough and basic block diagram of FIG Transmission device, FIG. 2 shows a more detailed block diagram of a transmission device with two connecting lines, Figure 3 shows the circuit diagram of a simple frequency generator, Figure 4 is a circuit diagram of a device for generating shift clocks, the pulse-wise are shown in Figure 5, Figure 6 is a simple circuit for automatic reset after switching on, FIG. 7a shows an additional blocking circuit on the transmitter side the transmission of data during the loading process of the Parc.llel series converter, FIG. 7b shows an alternative to the object of FIG. 7a, FIG. 7c shows an alternative to the object Pulse diagram belonging to FIG. 7b, FIG. 8 and FIGS. 9a and 9b others Possibilities of an additional circuit, the subject of Figure 9b belonging Pulse diagram is shown in Figure 9c. A circuit option for data transmission by means of a single line is shown in FIG. 10 and the timing diagram is in FIG 11 shown. the circuit arrangement on the receiver side to the transmitter side The arrangement according to FIG. 10 is shown in FIG. 12 together with the associated pulse diagram of Figure 13.

Description of the exemplary embodiments The exemplary embodiments relate to Devices for data transmission between a control device for operating parameters an internal combustion engine and display or diagnostic systems. Besides individual operating parameters such as speed and load signals as well as control parameters like z.E. the dwell angle signal, the injection signal, gear shift signals or however, error codes are transmitted to a diagnostic unit. Just that last The example mentioned illustrates the possible separation between the on-board device in the Motor vehicle and a stationary measuring unit e.g. in a workshop.

A limitation of the amount of data to be transmitted as well as their type is not provided. Serial data transmission is the only important thing of general quantities in digital form.

FIG. 1 shows a control device in a rough overview circuit diagram for operating parameters of an internal combustion engine in a motor vehicle with a signal transmission and display unit. At 15 is the computer unit of the control unit, with 16 the corresponding read-write memory, with 17 the read-only memory and 18 the input / output unit. All four units 15 to 18 are connected to one another via an address bus 19 and a data bus 20. With a parallel-to-serial converter in the form of a shift register is designated, its serial output to a dashed interface 22 is performed.

The parallel-to-serial converter 21 is controlled on the basis of the arithmetic unit 15 via their N and TPB outputs, these outputs becoming one in front of the control input of the converter 21 lying NAND gate 23 are performed. The data transfer is triggered by means of, for example, a manually operated switch 24 at a corresponding control input the arithmetic unit 15 or by program commands.

A seven-segment display unit, for example, has the reference number 26. It is controlled by the output signal of a series-parallel converter 27, which is his Input information from a receiver unit connected downstream of the interface 22 28 receives. This receiver unit 28 is controlled by a clock 29. Closer Details of the control of this clock generator 29 are shown in particular in FIG 12 can be seen.

While the previously listed blocks of signal transmission with only serve a line, a special clock generator 31 is shown in dashed lines for the transmission by means of two lines, then via the additional line 32 a special transmission clock signal is carried.

The first following embodiments relate to two-pole Interfaces, whereby a wet line is additionally required, which however usually exists anyway.

Figure 2 shows the subject of Figure 1 with the separate clock line 32 in a more elaborate manner. While the part in the control unit is only around a Input protection circuit 35 before the clock input of the shift register 21 and a driver stage 36 is added to the series output of the register, the Drawing of the display device in more detail. The serial input of the shift register 27 is preceded by a protection circuit 37 and the reset input is provided with a Start circuit 38 connected. Between the frequency generator 31 and the shift clock input of the shift register 27 is a shift clock generator stage 39, the structure of which in the following Figure 4 is explained in more detail. The output side is the shift clock generation stage 39 additionally via a driver stage 40 with the shift clock line 32 to the control unit connected. The parallel output of the shift register 27 is available via two adjacent ones Memory 41 and 42 with a double arranged seven-segment display 26 in connection. The memories 41 and 42 receive their control signal from the shift clock generation stage 39.

The two-pole connecting line is essential to the subject matter of FIG between control and display device. The external The generated shift clock is transferred to the control unit and the other line leads the individual data. This means that data transmission is completely detached from the clock frequency of the control unit, what with regard to the universal design of the display device is crucial.

The type of data to be transferred, i.e. operational parameters, control variables or e.g. error codes, is dependent on the processing unit 15 or on an external one Signal controlled. They arrive as a word in the shift register 21 and are from there, depending on the control of the display device, read out serially via the interface 22nd and read into the shift register 27 on the receiver side. From there, the output as a word and the corresponding display of the Values dependent on the “data valid signal” from the shift clock generation stage 39.

FIG. 3 shows an example of a frequency generator 31.

Its construction type is known as an RC generator and it consists of two series-connected Inverters 44 and 45, the second inverter 45 being made up of a series connection The junction of the capacitor is bridged by the capacitor 46 and the resistor 47 and resistance via a briderstand 48 to the input of the first inverter 44 communicates. The given feedback causes a natural oscillation of the system with a frequency that depends on the values of the individual components.

Figure 4 shows an embodiment of the shift clock generation stage 39 together with their edge wiring.

The main feature of the shift clock generation stage 39 is a four-digit one Counter 50, the clock input of which is fed by the frequency generator 31. The shift cycle itself is via a NAND gate 51 based on the input frequency signal and from Signal of the Q4 output of the counter 50 formed. The Data-Valid-S, gnal is from the carry output of the counter 50 removed. The counter 50 is reset by means of a positive Signal at the P3 input, this positive signal being provided via a button 52 and represents a general reset signal.

The individual processes relating to the impulse image of the object of FIG. 4 are shown in FIG. Figure 5a shows the input frequency signal from the frequency generator 31, Figure 5b, the reset signal, Figure So the Voltage level at the QL {output of the counter 50 (binary number output), FIG. 5d the output signal of the NAND gate 51 and thus the shift clock signal and finally Figure 5e that Data valid signal as an overflow signal from counter 50.

The numbering of the individual frequency signal pulses makes it clear that the shift clock begins with the eighth input pulse after the reset signal has ended and according to the value of the Q4 output with the fifteenth pulse and finally ends. In this respect, the shift clock generation stage shown only corresponds a frequency Ueilel.

While the counter 50 in Figure 4 by means of a signal from the button 52 is reset, it is advisable to do this for automatic systems Resetting the counter 50 when switching on the power supply to defined output states to obtain. The basic circuit for this is also known and is shown again in FIG shown. It consists of a Schmitt trigger designed as a NAND gate 54, the first input of which is directly linked to a plus line 55 and its second input to the junction of a capacitor 56 and a resistor 57 is performed, which are between the positive line 55 and ground. Here is the Resistor 57 is bridged with a diode 58 polarized in the reverse direction.

The circuit arrangement shown in Figure 6 generated due to their Wiring immediately after the switch-on moment a positive output signal, whose Duration depends on the values of the RC combination. Since after the switch-on process the potential across capacitor 56 is no longer changed, at least until the system is subsequently switched off, results at the output of the NAND gate 54 a one-time pulse following each switch-on process.

The subject of Figure 2 is the retrieval of the signals from the control unit via the interface 22 solely depending on the occurrence of the shift clock on the Gb Line 32.

Depending on the desired value to be retrieved, this changes relatively often, e.g. the speed value, so that precaution must be taken not to during the data transfer and thus during the reading of the values from the shift register 21 new values can be written into this register at the same time. Problematic is this case because then the valency within the data word is not corresponds more to the significance of the individual positions in the shift register.

Figures 7 to 9 therefore show circuitry options, in order to be able to avoid this mentioned error.

The subject of Figure 7a is the shift clock input of the shift register 21 an additional circuit 60 connected upstream, with which during the loading signal for the Sch-eberegister 21 the application of the shift clock to the register is blocked. This means that the loaded data word cannot be shifted in an undefined manner. Disadvantageous is, however, that due to the interrupted transmission of the receiver only part of the information receives, which is therefore faulty.

The additional circuit 60 from FIG. 7a has two inputs 61 and 62 and an output 63. A detailed one Circuit diagram of this Additional circuit 60 is shown in Figure 7b, with the same reference numerals are specified for the inputs and the output. According to the representation of figure 7b, the additional circuit includes a demodulation circuit (e.g. according to documents from RCA ICAN 6267) 65 as well as a flip-flop 68 (e.g. CD 4013).

The loading signal from input 62 becomes the clock input of the flip-flop 68 switched through, the D input of which is acted upon by the supply voltage. The output with the inverse signal of the flip-flop 68 is to one of the output 63 upstream AND gate 69 out, whose time input directly with the Input 51 is connected for the shift clock. The demodulator circuit also receives its input signal from this shift clock input 61 and controls via an inverter 70 the reset input of flip-flop 68.

The pulse diagram belonging to the circuit arrangement of FIG. 7b Figure 7c shows. A shows the shift clock signal at input 61, b shows the load signal at input 62, c the reset signal at the reset input of flip-flop 68, d the output signal at the inverting output of the flip-flop 68 and finally e the signal at the output 63 of the circuit arrangement. The pulse diagram makes it clear that the shift clock is interrupted with the arrival of the loading signal at input 62, so that over the Interface 22 no more data are transmitted.

In the receiving part, however, care must be taken that the already The transmitted part is not interpreted as complete and therefore not free of errors will.

With a view to error-free transmission, this can be done by the sender Shift register only once immediately before data transfer Loading. However, this means a considerable outlay in terms of circuit technology in the control unit, because in this case the control of the computer 15 with the circuit arrangement would have to be synchronized in the display device.

Another and relatively simple option is caching of the signal from the data bus in the control unit. This buffer becomes dependent loaded by a computer signal and the adoption in the farallel-series conversion The shift register serving is then controlled by the shift clock. An example of this Figure 8 shows.

FIG. 8 shows a transmission circuit in the control device with an additional circuit arrangement for uninterrupted transmission. It is between the data bus 20 and the shift register 21 a buffer 72 switched.

The required additional circuit arrangement 73 corresponds essentially that of Figure 7a. It has two inputs 74 and 75 for the shift clock and load signal and is at a first output 76 the shift signal for the shift register 21 and, via a second output 77, the L # esignal for this Shift register 21. Each time at the beginning of the eight shift clocks from the clock line 32, the values are loaded from the buffer 72 into the shift register 21. The load signal for the buffer 72 blocks the transfer of data from the Latch 72 in shift register 21. In this way, the latch 72 can be fed almost independently of the conditions in the receiving device and at the same time are on the shift register 21 as a parallel-to-serial converter at least constant input values for the duration of the data transmission.

Figure 9a corresponds to Figure 8, what the use of a buffer before the shift register.

However, the shift clock in the control unit is used as an alternative solution generated itself, even if under certain circumstances detached from the actual clock signal. The following structure results in detail: A shift clock generation stage is denoted by 80. It has three outputs 81, ~ 82 and 83, with the signal at output 82 together with a computer-controlled load signal from an input 84 is led to an AND gate 85, the output of which is in the loading input of the buffer 72 is linked. The load input of the shift register 21 is directly with it the output 81 of the shift clock generation stage 80 in connection.

In the case of the object according to FIG. 9a, the charge of the intermediate store 72 interrupted during the actual data transfer, i.e. the shift register is only reloaded during the pause. Appropriate coordination between The loading signal and search control then ensure that the latest values are always available are available in the cache.

FIG. 9b shows an exemplary embodiment of the shift clock generation stage 80 of Figure 9a, where the block 9C the.

Subject of Figure 4 corresponds. This block 90 has three outputs 91 (Q4), 92 (Data-Valid) and 93 for the shift cycle. Both exits 91 and 92 lead via an inverter 94 and 95 to a first input of two AND gates 96 and 97, the AND gate 96 additionally from the loading signal of the Point 84 is applied. The AND gate 97 is with via an inverter 98 the output 93 of the block 90 in connection. While now the output of the AND gate 96 supplies the load signal 1 for the buffer store 72, controls the output signal of AND gate 97 as loading signal 2 the loading moment of shift register 21.

FIG. 9c shows the pulse pattern belonging to the subject of FIG. 9b. The individual signal curves are the reference number of the location of their respective Associated with occurrence. It can be seen from this pulse diagram of FIG. 9c that the load signal 1 for the buffer memory the load signal 2 for the shift register lags so that the buffer memory only after the values have been transferred to the shift register is loaded with new values.

The previously discussed possible solutions for the Data transmission that, in addition to a ground line, 2 control lines are available have to. However, the invention also includes data transmission with only one Management. Figures 10 to 13 show the corresponding transmitter and receiver side Circuit arrangement with the associated pulse patterns.

The actual data transmission must include information for the Receiving part are preceded with respect to the required sampling frequency. Therefor a so-called start bit is used, the length of which contains this information.

FIG. 10 shows the transmitter-side circuit arrangement for this type of transmission. With 100 this is a parallel Shift registers acting in series converters denotes, to which data words are fed from the data bus via a buffer 101 will. The series output of the shift register 100 is followed by an OR gate 102 as well subsequently a driver stage for serial data transmission 103. The load signal for the shift register 100 and for the buffer memory 101 comes from a connection point 104, this point being directly connected to the buffer 101 and with the corresponding input at the shift register 100 via an inverter 105 and an AND gate 106. A trigger stage is designated by 108. There are also in FIG. 10 an AND gate 109 with a triple input and an AND gate 110 with two entrances. A clock signal is applied to an input point 112 and controls both the clock input of the flip-flop 108 and one input each of the AND gates 109 and 110. A further frequency signal derived from the clock signal is connected to a Connection point 113 is available and with it the D input of flip-flop 108 and the second input of the AND gate 109th driven. The flip-flop is reset 108 with a signal from connection point 114. During the Q output of this flip-flop 108 is coupled to the second input of AND gate 110, controls the signal from the output Q of the flip-flop 108, the AND gate 109 via its third input. The output of this AND gate 109 is both to the further AND gate 106 and led to the second input of the OR gate 102. Finally there is the exit of AND gate 110 with the clock input of shift register 100 in connection.

The circuit arrangement shown in FIG. 10 is expediently explained using the pulse diagram of Figure 11, the individual pulse trains are marked with the numbers of the respective places of their occurrence.

In Figure 11, a shows the clock frequency at input 112, b shows in the Frequency divided signal, c is the output signal at the Q output of flip-flop 108, d is the output signal of AND gate 109. This signal is also used as the start bit switched through to the OR gate 102 and thus contains information on the used Clock frequency.

Figure lle shows the load signal present at input 104, the time occurs randomly and both the buffer 101 loads with new data, as also blocks the new data transfer into the subsequent shift register 100. figure lif shows the load signal for the shift register 100, it being clear that in each case At the beginning of a data transmission, the last one located in the buffer memory 101 Data word in the shift register 100 is accepted. The clock signal for the shift register 100 is shown in FIG. 11g, its corresponding output signal in FIG. 11h. Finally, FIG. 11 shows the information to be transmitted in its entirety as the sum of the start bit and the serial data word.

The length of the pause following this data word is the present Example determined by the frequency shown in Figure 11b, which is one sixteenth corresponds to the base clock frequency. As a result, the subject of FIG. 10 an information transmission is started with every sixteenth basic clock pulse.

The transmission circuit shown in Figure 10 can be relatively easy on an LSI module for input / output a microcomputer. This enables program-controlled output of data words to display operating data and e.g. enables error codes. The advantage here is that the required auxiliary clocks according to FIGS. 11a and 11b, as a rule, already available in the input / output circuit are.

A serial data telegram can be sent without any hardware effort also by appropriately programming the microcomputer on its serial Generate output Q.

According to Figure 11, the actual data word is preceded by a tart bit, where the duration of the start bit has a fixed connection with the respective point in time the transferred data is available. Basic idea of the invention with the only single pole Transmission line is now the length of this start bit as synchronization information to utilize for the data recipient. The length of the start bit is used on the receiver side for this purpose counted and the required sampling points for the data selected accordingly.

An example of the corresponding receiver circuit is shown in FIG 12 shown.

In the subject of FIG. 12, a first counter 120 is used to determine the length of the start bit. A memory 121, four flip-flops 122, 123, 124 and 125 are provided for this purpose and T'ND gates 126, 127 and 128 in addition to a NOR gate 129 are required. Of the A counter 130 is used to generate the sampling points in the middle of the partial data words and a flip-flop 131. Finally, there is a complex of series-parallel converters for the display in the form of a shift register 132, a storage and driver stage 133 and a Display device 134 required. All will be put on hold Counters and storage devices with one derived from each start bit Reset pulse by means of the reset pulse generator stage 135.

In detail, the following circuit structure of the object results of FIG. 12. The information transmission line comes from interface 22 and leads via an input protection circuit 136 both to the reset pulse control unit 135 as well as to an input of the U '? D gate 126. This is on the output side of the D-input of the flip-flop 122 out, the Q-output with both aen D-input of the subsequent flip-flop 123 as well as one input each of the NOR gate 129 and of AND gate 127 is connected. The other two inputs of these gates are linked to the Q output of flip-flop 123. Both outputs of gates 129 and 127 are each for one of the set or reset inputs of the subsequent multivibrator 124 led. During the # Q output of this flip-flop 124 via AND gate 128 coupled to the CI input of counter 120 controls the signal from the Q output the flip-flop 124 the counting direction of this counter 120. The flip-flops are clocked 122 and 123 as well as the counter 120 based on one applied to the input 138 Clock frequency signal. The numerical output of the counter 120 is linked to the memory 121 and its output in turn determines the respective initial value of counter 120, so that there is a feedback for the counter 120 via this memory 121. The carry output of the counter 120 controls the D input of the flip-flop 125 and its Q output, in turn, the readiness to pay of the counter 120 and the counting frequency of the counter 130. The counting ready signal of the counter 130 comes just like the takeover signal of the memory 121 and the signal at the set input of flip-flop 131 from the output of NOR gate 129. During the Q output of the flip-flop 131 is linked to the two second inputs of AND gates 126 and 128, leads a line 140 from the Q output to an AND gate 141, at its second input the signal 136 coming from the input protection circuit is present and its output is led to the series input of the shift register 132.

The Ta # t frequency of this shift register 132 depends directly on the Signal at the Q1 output of the counter 150.

The over on output of this counter 130 finally controls that Resetting the flip-flop 131 via an inverter 142. This as a series-parallel converter Working shift register 132 indicates the data information transmitted in each case the memory 133 and finally to the display unit 134.

The mode of operation of the object shown in FIG. 12 results can be seen from the pulse pattern according to FIG. 13.

Figure 13a shows the input signal of the receiving circuit, which necessarily corresponds to the output signal Figure lli of the transmission circuit. Figure 13b shows the count progression of the counter 120, the mode of operation of this counter becomes apparent. What is essential is a rupwcrtszählvorgang during the period of the artbits and thus half the period of a data item information. To it a down counting process follows with a decrease gradient corresponding to the increase on, in which case the counter will open again after reaching its zero crossing this previously determined count is reset. Be that way Sampling points obtained according to Figure 13c, each in the middle in comparison to the line of Figure 13a to a data information. The start and stop signal for the initial Counting process in counter 120 is shown in FIGS. 13d and 13e. The reset signal for this counter 120 is shown in FIG. 13f and the shift clock signal derived therefrom in Figure 13g and 13i, respectively. The time signal for the transmission of the entire data word shows Figure 13h.

Essential for the object of FIG. 12 to work correctly is a much higher clock frequency than the dolge frequency of the data because of it the accuracy of the counting of the start bit depends.

Due to the central data query - compare Figure 13a with 7i - minor shifts in the sampling frequency are irrelevant, since they are at the beginning of each information transmission is determined anew and the shift clock at least initially, i.e. at the first data bit, very well approximated in the middle of this data bit lies. After a complete data set has entered the shift register 132 the read data word is transferred to the memory 133 and ultimately to the display unit 134 supplied.

What is essential in the objects of FIGS. 10 and 12 is the serial Information transmission regarding the clock frequency and the data via only one line except for the ground line, as well as the inevitable synchronization of the signal processing in the receiving section to the clock frequency available in the transmitting section. Included In addition to its use in motor vehicles, this system is also suitable for the data transfer between Motor vehicle and e.g. a diagnostic unit. For use in the motor vehicle itself, the connection between some kind of digital control device for operating parameters the internal combustion engine and e.g. display units in the area of the dashboard.

Device for the serial transfer of data in and / or out of a Motor vehicle summary A device for serial Transferring data to and / or from a motor vehicle, such as operating parameters and / or an error code, based on a data bus of a digital one Signal processing system and a parallel-to-serial converter connected to the data bus, where the transmission frequency versus the operating clock frequency of the signal processing system is freely selectable. A first embodiment works with two separate transmission lines for the clock signal and the data signal. In the second embodiment is the the actual data word is preceded by a so-called # s start bit, which is in its Length of information for controlling the clock frequency generator on the receiver side contains.

The proposed solutions are characterized by great insensitivity with respect to disturbances, because in particular in the case of the second proposed solution, the scanning of the signal is re-synchronized in the receiver at the beginning of each data word.

Claims (9)

Claims device for the serial transmission of data in and / or from a motor vehicle, such as operating parameters and / or an error code, starting from a data bus of a digitally operating signal processing system and with a parallel-to-serial converter connected to the data bus, characterized in that the signal transmission clock frequency compared to the operating clock frequency the signal processing system is freely selectable. 2. Device according to claim 1, characterized in that two lines are provided between the transmitting and receiving part, a line (32) of the clock control is used for transmission and the clock signal can be generated in the transmitting or receiving part. 3. Device according to claim 1, characterized in that between Sending and receiving part a single line is provided, the one to be transmitted Signal series with starts with a start bit and the length of the start bit the receiver-side sampling frequency generator (130) controls. 4. Device according to claim 2 or 3, characterized in that the transmission can be blocked during the charging process of the parallel-to-serial converter (21) is. 5. Device according to claim 2 or 3, characterized in that the loading process of the shift register (21) is interrupted during the signal transmission is. 6. Device according to claim 2 or 3, characterized in that a buffer (72, 101) lies. 7. Device according to claim 3, characterized in that; that in the receiving part the length of the start bit or a fraction of it using a counter (120) and the sampling frequency for the individual data bits depends on the counting result is set. 8. Device according to at least one of claims 1 to 7, characterized characterized in that the sampling points are preferably in the middle of the data bits. 9. Device according to at least one of claims 1 to 8, characterized indicated that the data to be transmitted are operating values (e.g. speed, ignition angle, Dwell angle, injection time), (.self) test results or error codes are provided are.