DE3136029A1 - Circuit arrangement for reproducing a television image with lines written alternately in an opposite direction - Google Patents

Abstract

Circuit arrangement for reproducing a television image, in which the received signal is supplied to a storage device, the direction of extraction being reversed with each second line so that the television signal is received and reproduced alternately in the original scanning direction and in the opposite scanning direction. <IMAGE>

Description

Circuit arrangement for reproducing a television picture

with lines alternately written in opposite directions The invention relates to a circuit arrangement for reproducing a television picture, in which successive lines are written in opposite directions.

In known circuit arrangements in which the lines in the same Direction to be written is a faster one between the successive lines Return required. The flyback pulse occurring at the line output transformer used to generate high voltage, there is only a limited degree of efficiency of e.g. 60% possible. However, if the high voltage is separated in the manner of a switching power supply is generated, an efficiency of over 90% can be achieved. It is therefore advisable to successive lines in opposite directions in a manner known per se to write. Then a quick setback is no longer necessary; the distraction runs according to a symmetrical sawtooth, its rising and falling plank are similarly inclined in a corresponding manner. Then there are also one for the kickback pulse Utilized blanking intervals and return blanking are no longer required; the lines can almost immediately adjoin one another, so that practically the full line time of 64 / us can be used for writing a line: As a result, the brightness and / or the point sharpness can be improved, to be precise up to about 20%.

The absence of the kickback pulse also eliminates the high voltage load including the switching elements connected to the line output transformer the deflection coil. The rectangular to be applied to the deflection coil tension then only needed 75 volts in both polarities, i.e. approx. 150 volts from tip to Tip to be. The training of the end-of-line stage can also be integrated Facilitate technology.

The generation of a signal transmitted by the transmitter with a periodic Changing the line direction should only be possible with new systems, e.g. a special Satellite television or a television system with a higher number of lines can be implemented possibly also in closed systems, such as cable systems, monitoring systems and data processing systems.

The invention is based on the object of providing the advantages of image reproduction with periodically changing line direction, can also be used for a standard television system close.

This object is achieved if, according to the invention, a television signal, obtained by scanning line by line in the same direction, a memory device fed, whereby the removal direction is reversed for every second line (Fig. 1).

The television signal is preferably a first.

Line in the pixel sequence supplied to a number of memories and removed again in the same direction, and the television signal from a second Line is fed in one direction and again in the opposite direction taken so that the television signal alternately in the original and in the the opposite scanning direction is obtained.

According to another embodiment, the television signal can be from a storage device are supplied, in which the writing and / or the reading direction of the written Pixel signals is reversed every two lines.

According to another expedient embodiment, the television signal fed to a shift register, the direction of which shifts every two lines is reversed.

According to a preferred embodiment of the invention that can Reading out with a reduced clock speed compared to the clock speed when inputting are done in such a way that the reproduced signal is stretched one line and takes up a larger part of the line duration than when reading in. The read out The television signal can thus be extended to at least almost the full line duration of e.g. 64 will.

The vertical deflection is expediently carried out in a known manner in steps, i.e. with a constant value during a line duration, so that the lines written in parallel.

In the case of an image display device, the current position of the image point be indicated by a response.

This is the case, for example, with an index tube where the perpendicular colored stripes are inserted further stripes, which a signal when the electron beam hits them. This will provide an accurate identification every pixel possible. If then the clock signal of the memory device with the feedback signal is synchronized, is a precise assignment between a Pixel and the associated signal possible. Linearity error in the line deflection direction can thus be avoided.

In a circuit arrangement according to the invention, analog or digital television signals are processed, the memory unit accordingly must be trained.

The invention is illustrated below with reference to the drawing, for example explained in more detail in the in 1 to 3 embodiments of the invention are shown in the block diagram, while in Fig. 4 schematically the sequence of pixels are shown in a shift register in different phases, Fig. 5 shows a reversible shift register in detail.

In Fig. 1, a shift register 1 is shown, which is one of the number of pixels has a number of storage locations corresponding to a television picture line of e.g. 650. The shift register 1 is fed from the terminal 2 clock signals with a Frequency of 10 MHz switched forward.

The television signal with from line to line in the same scanning direction running image point sequence is fed from an input terminal 3 to the changeover contact 4 a changeover switch 5 supplied. The output signal is taken from terminal 6, which is connected to the changeover contact 7 of a switch 8. The one in the drawing The output contact of the switch 5 shown above is connected to the left end of the Shift register 1 and connected to the contact of the switch 8 shown below. The lower output contact of the switch 5 is with the right end of the shift register 1 and connected to the upper contact of the changeover switch 8.

A control part 10 are horizontal frequencies from a terminal n Signals, e.g. the line sync pulses, and from a terminal 12 vertical frequency signals, derived e.g. from the vertical sync pulse. The tax bracket 10 contains, for example, a 2-bit counter for the line pulses such that the signal at its output 13 changes its state every two lines. In addition, the mentioned counter by the vertical frequency signal supplied by terminal 12 is set in an initial state such that at the beginning of each field the required Switching status for correct line jump is present at output 13.

The signal sent from output 13 to terminal 14 is continued via switching stages not shown, which are indicated by dashed lines, the switches 5 and 8 and the shift register 1 supplied. This causes that the switches 5 and 8 are brought into the other position after every second line so that they are back in the starting position after every four lines. aside from that the shift direction is switched in shift register 1 every two lines.

The keying in and removal of the pixel signals obtained thereby is explained with reference to FIG. 4, in the left the sequence of the stored pixel signals after the second pixel, one comprising six pixels for the sake of simplicity Line is shown, while on the right the pixels in the shift register at the end of the relevant line are shown.

According to FIG. 4a, the first pixel is 1.1 and the second pixel 1.2 of the first line inscribed from the left; through the thickened line the beginning of the first line is marked. When you continue to register, the Image points, led by point 1.1, continue to the right until the end of the Line the position shown on the right in Fig. 4a is reached. After that the second Line, beginning with the first pixel 2.1, inscribed from the left; simultaneously are the pixel signals of the first line written in on the right according to FIG. 4a are output at the right end of the shift register and arrive at a line duration delayed, according to FIG. 1 via the switch 8 to the output terminal 6. At the end of the The second line is then the pixels thereof in accordance with FIG. 4b in the shift register 1 enrolled.

Now are from the starting point 16 of the control unit 10 over the dashed lines the switches 5 and 8 put down and the Direction of movement of register 1 reversed. The signals supplied by terminal 3 the third line is now fed to the right end of shift register 1, while the pixel signals present at the left end of the shift register 1 above the thrown changeover switch 8 are transmitted to the output terminal 6, like the one from Fig. 4c can be seen on the left. The signals in the second line are thus reversed Direction read out while the signals of the third line are stored at the same time are such that they finally have the distribution shown on the right in Fig. 4c to have.

The position of the switches and the scanning direction remain in the next line equal, so that the signals of the third line in the same direction to the left end are transmitted back as they were stored from the right end while at the same time the signals of the fourth line are written in until they reach the position have reached according to Fig. 4d.

After that, the control unit 10, after in the meantime two line times have passed, the switches 5 and 8 thrown again; and the direction of movement in register 1 is changed again. The fifth line is thus written Fig. 4e measured again according to the first line in Fig. 4a, while at the same time the signals of the fourth line are output to output terminal 6 in the opposite direction will. At the end of this period, the signals of the fifth line according to Fig. 4e inscribed on the right in the same way as the signals of the first line according to FIG 4a on the right.

In Fig. 2, an embodiment is shown as it is also with a Speicherennchtung can be realized in which not as in Fig. 1 signals simultaneously can be written in and read out. The in- output terminal 3 and the output terminal 6 are again connected to the tongues of changeover switches 15 and 16. The input of a memory device is connected to the upper contact of the changeover switch 15 17 connected, which is able to successively record the pixels of a line and then, controlled by a clock signal from a terminal 18, at their output can give up again.

The lower output contact of the switch 15 is connected to a memory device 19, which can also record the pixel signals of a television line, and the it then, controlled by a clock signal from a terminal 20, at its output 21 can return in reverse order.

In the position shown in Fig. 2, the switch 15 and 16 is the signal of one line from the terminal 3 is written into the memory device 17. At the same time, those in the previous line time are saved in the memory device 19 inscribed pixel signals with reverse direction from output 21 via the upper contact of the changeover switch 16 is fed to the output terminal 6; on this terminal so occurs in the position shown, a signal that is opposite to the original Input signal has the opposite pixel sequence.

According to the dashed lines, as shown in Fig. 1, from a control unit 10 via a terminal 14 at the beginning of the following line the changeover switches 15 and 16 are switched over, and the memory device 19 is again switched to writing in the normal direction, with the input signals from terminal 3. In the same interval, the Memory device 17 written in signals in unchanged sequential direction the lower contact of the changeover switch 16 is fed to the output terminal 6.

In Fig. 3, one is made up of five point memories for the sake of simplicity 21 to 25 existing memory unit shown, which is used for reading in reverse Direction can be switched. For storing and reading out under action a clock signal, not shown, the point memories 21 to 25 are between the input terminal 26 and the output terminal 27 by the pulled-out connections connected in series. If the reading direction is reversed compared to this writing direction should be, the connections are separated according to the indicated crosses, and it is by not shown, preferably electronic, switches that connections shown in dashed lines. As you can easily see the point signal from the memory 21 that was last written in then arrives first, to output terminal 27. The previously written point signals passed from the memories 22 to 25 to the output 27 in reverse order.

It is of course also possible to use the point memories 21, 22, 23, 24 and 25 in the manner of a multi-stage switch or

to be controlled directly one after the other according to a switching program and then retrieve them directly to the exit in the desired order.

Fig. 5 shows an embodiment of a switchable shift register corresponding to FIG. 3, this by applying clock signals in the desired shifting direction is switchable.

The input signals are sent from a terminal 3 via the main current path a first switch transistor 31 of a storage capacitance which is on the other hand grounded 41 supplied to the control electrode of a first amplifier transistor 51 connected is. The main current path of this amplifier transistor 51 is on the one hand in bulk and is on the other hand via a second switch transistor 32 connected to the supply terminal V. The connection of transistors 51 and 32 is further via the main current path of a third switch transistor 33 to a second, on the other hand connected to ground storage capacity 42, with the the control electrode of a second amplifier transistor 52 is also connected. the The main current path of the amplifier transistor 52 is on the one hand to ground and on the other hand connected to the supply source V via a fourth switch transistor 34. the Connection of the transistors 52 and 34 is further via the main current path fifth switch transistor 35 connected to the output terminal 6.

The circuit described so far represents a known shift register Art. The switch or. Amplifier transistors are preferred Field effect transistors that can be controlled practically without current. The control electrodes the switch transistors 31, 34 and 35 are connected to a clock signal Tv which causes a current permeability at every second pixel. The switch transistors 32 and 33 are connected to a clock signal rv, the current permeability at the pixels in which the clock signal Tv does not occur. The clock signal Tv is thus information from the input terminal 3 via the switch transistor 31 of the first Storage capacity 41 supplied. At the next pixel, the switch transistor 32 voltage is applied to the transistor 51, so that at its output electrode a the voltage on the capacitor 41 corresponding, inverted signal occurs and via the simultaneously conductive third switch transistor 33 of the second storage capacitance 42 is supplied. In the following interval the signal is then from the capacitance 42 removed, amplified inverted in the amplifier transistor 52 and via the switch transistor 35 of output terminal 6 fed. So it becomes a sequence of Transfer point signals step by step from terminal 3 to terminal 6, with a Storage and delay takes place according to the intervals of the clock signals.

For a circuit arrangement according to the invention, the delay device operated with the storage capacities 41 and 42 in the opposite direction. In addition the signal value appearing at output terminal 6 is transmitted via the main current path a switch transistor 36 is supplied to the second storage capacitor 42. The fourth Switch transistor 34 is the main current path of a seventh switch transistor 37 in parallel, and between the junction of transistors 37 and 52 and the first Storage capacitor 41 is the main current path of an eighth switch transistor 38 switched on. The second switch transistor 32 has the main current path a ninth switch transistor 39 in parallel, and the connection of the transistors 39 and 51 is via the main current path of a tenth switch transistor 40 with connected to input terminal 3. The control electrodes of transistors 36, 39 and 40 are connected to a clock signal input Tr, and a clock signal Tr becomes the Control electrodes of the transistors 37 and 38 are supplied.

When the clock signal Tr occurs, it is at the output terminal 6 existing signal via the sixth switch transistor 36 of the second storage capacitance 42 supplied.

Thereafter, the transistors 37 and 38 are turned on by the clock signal Tr, so that the inverted signal appearing at the output of transistor 52 from the second capacity 42 of capacity 41 is supplied. If then again the clock signal Tr occurs, the switch transistors 39 and 40 are current-permeable, the transistor 51 acts as an inverting amplifier, and the inverted signal obtained becomes transmitted via switch 40 to input terminal 5.

The delay circuit shown in Fig. 5 has only one with two storage capacities 41 and 42 equipped stage, their input side and their Output side is indicated by the dashed lines 45 and 66. It is ersichtlidX that the stage existing between these two lines in any number one after the other can be switched, resulting in a correspondingly longer delay and storage a correspondingly higher number of points can be achieved.

The parallel transistors 32 and 39 or 34 and 37 can also by a single load transistor that is not keyed or a simple one Resistance to be replaced, which is merely the working impedance for the transistor 51 and 52 respectively.

When operating in the forward direction, the clock signals Tv and Tv occur alternately, while the terminals Tr and Tr are signals through which the thereby controlled switch transistors are kept in the blocked state. Correspondingly, when operating in the opposite direction, from terminal 6 to Terminal 3, the clock signals T r and Tr alternate for operation in the reverse direction while they are set at the other clock signal inputs Tv and so, that the transistors connected to it with their control electrodes are impermeable to current are.

The signals Tv and tv on the one hand and Tr and on the other hand occur so alternatively on; they can therefore be taken from the same pulse source if necessary. However, it is also possible to carry out pulse scanning in one direction, which corresponds to the line length recorded in the receiver and determined by the sender standard, while sampling takes place at a frequency 10 to 20% lower, see above that the content of the line is wider or wider when it is displayed on the screen. is played back more slowly and the kicking Intervals that were previously caused by the return line are now reduced become and be omitted. At different clock frequencies in different directions are then, approximately in accordance with FIG. 2, two delay lines to be provided which read in with a changing clock frequency and then, if necessary in the opposite direction, can be read out again.

A circuit according to Fig. 5 can be operated with analog signals, if the transistors used provide a sufficiently linear transmission of analog signals enable.

The circuit arrangement according to FIG. 5 is preferably for digital Uses signals that have only two alternately switched on amplitude values, which amplitude values are brought back to the nominal value in each subsequent stage can be. In the case of digital signal transmission, the number of digits corresponds (Bits) to use a plurality of the arrangements according to FIG. 5 in parallel. In particular separate storage capacitors 41 and 42 are not required for digital signals; the input capacitance of the downstream transistor 51 or 52 are exploited.

As a storage device in which the read-out takes place in the opposite direction can be used for input, a CCD line with 3-phase control can also be used, in which the charges are transported step by step according to the control. Such a line is known from the magazine FERNSEH- und KINO-TECHNIK 31, 1977, 3, pages 82 to 86. It then only needs the mutual phase position, so to speak the direction of rotation of the three clock signals shifted by 1200 against each other changed to become, e.g.

by swapping two of the clock signals: Then is the transport direction of the charges reversed.

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Claims (8)

PATENT CLAIMS: Circuit arrangement for reproducing a television picture, in which successive lines are written in opposite directions, characterized in that a television signal obtained by scanning line by line was obtained in the same direction, fed to a storage device (1), wherein the removal direction is reversed for every second line (FIG. 1). 2. Circuit arrangement according to claim 1, characterized in that the television signal of a first line corresponding to the pixel sequence of a number is fed from stores and removed again in the same subsequent direction and that the television signal of the following line a number of memories in one direction is supplied and removed again in the opposite direction (Fig. 2). 3. Circuit arrangement according to claim 1, characterized in that the television signal is fed to a storage device (1, 4, 7) in which the Input and / or readout direction of the written pixel signals all two lines is reversed. 4. Circuit arrangement according to claim 3, characterized in that after every second line the outputs of the individual storage elements (21 to 25) not with the entrance of the originally following, but with the entrance of the preceding Memory element are connected and that after the fourth line of the original Subsequent state is restored (Fig. 3). 5. Circuit arrangement according to claim 3, characterized in that the television signal is fed to a shift register whose shift direction is reversed every two lines (Fig. 5). 6. Circuit arrangement according to one of the preceding claims, characterized characterized in that the readout is compared with a reduced clock speed the clock speed when entering is such that the reproduced signal one line is stretched and takes up a larger part of the line duration than with Reading in. 7. Circuit arrangement according to claim 6, characterized in that the read television signal to at least almost the full line duration of e.g. 64 / us is expanded. 8. Circuit arrangement according to one of the preceding claims, characterized characterized in that the clock for reading out the signals from the memory device (1; 17, 18) is synchronized with a signal that contains information that indicates the position of the electron beam on the screen.