DE3149240A1 - ELECTRICALLY CHANGEABLE FIXED VALUE STORAGE AND METHOD FOR THE PRODUCTION THEREOF - Google Patents

Description

GEYER, ΗΑ & ΕΜΑΉΝ & »PARTNER · ··

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and Zo% Pat 187 / 3-81E GM 187 / 4-81E

Munich , December 11th, 1981 VS / 6 / nb

GENERAL INSTRUMENT CORPORATION

West John Street
Hicksville, New York 11802

V.StoÄ =

ELECTRICALLY MODIFICATION OF FIXED VALUE STORAGE AND METHOD FOR MANUFACTURING IT

Claimed priority ;

Date; December 12, 1980 land; V.St.A. Az .; 215.224

GEYER, HAGEMANN & PARTNER:

H92 4 O PATENT LAWYERS

PROFESSIONAL REPRESENTATIVES BEFORE THE EUROPEAN PATENT OFFICE

lsmaninger Strasse 108 8 (KX) Munich 80 Telephone O 089 / 980731-34 -Telex 5-216136 hage d -Telegram hageypatent -TelckoniertT 089.-98073I

Postal address: P.O. Box 860329 8000 Munich 86

General Instrument Corporation Munich / den

Hicksville, New York 11802 December 11, 1981

V. St.A. VS / 6 / nb

uZ: Pat 187 / 3-81E
GM 187 / 4-81E

Electrically changeable read-only memory and process for its production

The invention relates to an electrically variable semiconductor read-only memory as described in the preamble of claim 1 specified genus.

An electrically changeable read-only memory (Electrically Alterable Read Only Memory - EAROM) is called a programmable non-volatile semiconductor memory used. Such memories are made up of individual memory cells made of metal-nitride-oxide semiconductor arrangements (Metal Nitride-Oxide Semiconductor - MNOS). The memory cells each have source and drain regions and a memory gate area. The memory gate area in turn essentially has an interface between Isolatormatoriale, for example between a silicon dioxide and a silicon nitride layer. EAROM memories can be manufactured inexpensively in integrated circuits (ICs) according to a predetermined pattern with high density will.

The ICs also contain circuits for performing logical operations, for addressing and decoding, by means of which the memory cells can be selected in groups or individually. In general, one word is implemented by means of a memory cell group. EAROM ¹ s have a low power consumption and can be achieved by applying suitable voltages to the gate

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The electrodes of the memory cells are relatively easy to erase and write on. «They have a wide range of applications , for example found in radio and television tuners, program storage units or the like «

In such EÄROM memories, each memory cell is from of its neighboring memory cell isolated so that one any memory cell selected and read, written

£ 0 or can be deleted without affecting the neighboring Affecting the cell o Such isolations are common implemented by so-called channel delimitation between adjacent memory cell groups «Under a channel delimitation one understands a region arranged on the semiconductor substrate between adjacent memory cells with high threshold voltage to prevent undesired flow of information between not assigned Source and drain diffusion regions. Such a channel limitation can, for example, by a thick insulating layer over a heavily doped substrate region between some source-drain diffusion regions that are not assigned to one another be realized. In the case of an N-channel EÄROM, for example, the channel limits exist made of P material with a thick field insulation. Despite such channel limitations, it is not always ensured that the memory cells (bits) adjacent to a memory cell (bit) subjected to a write operation of are shielded from this write operation «,

in EAROM memories is a channel shielding defined as the ability to convert selected memory cells from the erased state in the written state _r without affecting the other erased memory cells are affected. In other words, the channel shielding is understood to mean the ability

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ability to shield erased memory cells from being written to, when writing to adjacent memory cells. For large storage structures with high density Channel shielding is not only desirable but also necessary. Good duct shielding is required here for as many erase-write cycles as possible, there this improves the usability of the read-only memory.

In the channel shielding mode, the source and drain areas (columns) of the unselected erased bits (bits that are to be shielded from the neighboring Bits.kanalabshielded) are biased with a write voltage. For example, the bias is about 25 volts for N-channel EAROM ¹ S. The gate (word line) is also raised to the write voltage. The substrate is at mass potential. Accordingly, the source, drain and gate are at the same potential, with the sources and drain connections being reverse biased. The gate electrode current, which otherwise has to be used to write the bit or the memory cell in question, is here essentially shunted by the bias of the source and drain in the reverse direction. If one ignores the effect of a possibly existing residual current from the gate to the substrate, then the bit in question is not written. The smaller the size of this residual gate current, the better the channel shielding. Repeating the erase-write operation results This residual current accumulates until the bit or the memory cell finally loses its originally erased state. Accordingly, the time and the number of erase and write cycles impair the channel shielding. The aim is now to reduce this residual gate current in the channel shielding mode and thereby the number of Lösch-Pat 187 / 3-81E, GM 187 / 4-81% - 8 -

GENERAL INSTRUMENT CORPORATION

OO

Increase write cycles with effective channel shielding.

The invention now has for its object to further develop the generic electrically veränderbaren.FestwertrHalbleiterspeicher such that its channel shielding is increased while substantially maintaining its previous advantages.

This task is achieved through the characteristic features of the claim solved"

The specified solution has the advantage that the channel shield even with a larger number of erase-write cycles remains effective than with comparable EAROM = read-only memories known up to now "

The invention relates to a method for producing an electrically variable semiconductor read-only memory according to the preamble of claim 13 specified type ».
The invention is also based on the object of further developing the generic method while largely retaining its previous advantages in such a way that an electrically changeable semiconductor read-only memory is provided through a comparatively simple process management

improved channel shielding can be produced. 25th

This object is achieved by the characterizing features of claim 13.

The specified solution enables a particularly well controllable build-up of a foreign matter surface concentration H tion profile in the storage area.

As a result of the solution according to the invention, the memory gate field is created by suitable construction of an impurity concentration profile reduced below the memory gate channel »

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In detail, the foreign matter concentration profile is built up in this way or the foreign matter doping is so led that the impurity concentration on the surface is relatively low and thereby the gate field reduced, the threshold voltage of the memory cell on the other hand is left essentially unchanged.

Further preferred exemplary embodiments of the invention are given in claims 2-12.

With an N-channel EAROM, the gate threshold ' voltage, i.e. the voltage at which the EAROM switches from one state to the other, determined by that a first suitable foreign substance, for example wise boron, is implanted in the fission gate areas. In addition, a second foreign substance with the opposite conductivity type is implanted. With an N-channel EAROM is this foreign substance, for example phosphorus. This is the effect caused by the first foreign matter Surface concentration is reduced and, as a consequence, so is the field under the gate. The required threshold voltage on the other hand, this second foreign matter makes it practical unaffected. The reduced gate field increases the channel shielding by reducing the charge carrier mobility in the gate dielectric region and, as a result, the electric current from the gate to the Substrate is reduced. However, the latter is the main cause of inadequate duct shielding.

The invention is illustrated below with the aid of exemplary embodiments with reference to the attached schematic = üeh'en drawings.

In the drawings show:

·

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1i shows a side view of a cross section through a complete gap gate EAROM memory cell?
Fig. 2; a graph to explain the effect on the surface concentration of the

first foreign matter as a result of the additional

Doping with the second impurity;

r \ C \ chif. Fig. 3a to 3 ^ s individual process stages for the production (\ Q (\ n d. "■

^{ü development of} an EAROM fixed value spexcher.

10

In Fig = 1 is a cross section through an embodiment a complete EAROM gap gate memory cell according to the invention 10 shown »The memory cell 10 is greatly enlarged and not to scale.

give »In the following, only one memory cell 10 is described. However, as is customary in the manufacture of semiconductor components, several can of course such memory cells are produced at the same time, possibly together with other other semiconductor circuits, which are designed for performing logical operations, for decoding and / or addressing. the The latter semiconductor components are not shown below, since they are not part of the invention Doctrine are «Incidentally, several storage cells are common arranged in groups or words «

The illustrated EÄROM memory cell 10 is an N-MNOS memory cell Instead, the memory cell can also be constructed as a P-MNOS memory cell »The memory

30th

cell 10 comprises a suitable substrate 12, made for example of silicon and having an N-type impurity such as arsenic is doped "The substrate 12 serves as a support for a grown thereon epitaxial layer 14 with a P-type impurity", for example,

or

Boron, is doped »The dopant level in the epi-

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Taxie layer 14 can, for example, be on the order of about 1 × 10 atoms / cm to 1 × 10 atoms / cm. The memory cell 10 is delimited, for example ¹ by diffusion insulation regions 16 arranged on both sides. The diffusion insulation regions 16 are formed by a through the epitaxial layer 14 to 14. in '·:. the substrate 12 is built up leading diffusion and have an N-impurity doping.

A pair of connection regions 20 and 22 serving as source and drain is, for example, by diffusion in of the epitaxial layer 14 is formed. The source and drain regions 20 and 22 are doped with an N-type impurity. The production of such source and drain regions 20 and 22 by diffusion is known per se, so that in this regard common methods can be used, for example ion implantation. By Channels or zones generated by diffusion for the source and drain regions can, for example, by implantation of arsenic / phosphorus ions with a level of impurities in the

19 3 21 order of magnitude of about 10 atoms / cm to 10 atoms / cm.

An area made up of a thick insulator material, hereinafter referred to as field oxide region 26, is, for example, made of a silicon dioxide layer several thousand angstroms thick built on the top surface of the epitaxial layer 14. The field oxide region 26 extends to to the outer edges of the source and drain regions 20 and 22. The field oxide region 26 insulates the memory cell 10 of adjacent memory cells and forms the channel blocking areas mentioned in the introduction. Electrodes 50 and 52 for an electrical connection to the source region 20 and the drain region 22 are via openings through the field oxide region 26 guided. The electrodes 50 and 52 are

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. are made of aluminum, for example,

The memory cell 10 xtfe is a memory gate area 30, which is arranged between two vertical insulating webs 29 of the field oxide area 26 «on each side A gap gate region 32, which is also called gate oxide in the following, is arranged in the memory gate region 30 and consists of an insulator several hundred angstroms thick, such as silicon dioxide. Between the two gap gate areas 32 is a tunnel area 34 with a tunnel gate layer arranged thereon 36 = The tunnel gate layer 36 in turn consists of an insulator, for example silicon dioxide (SiC ^). The gap gate areas 32 are the areas in which none Tunneling takes place “They are thicker than the gate tunnel! .36 J For example, the fission gate areas 32 are approximately 400-600 Angstroms thick, the gate tunnel.1-layer 36 on the other hand only about 10-40 angstroms. The aforementioned DiGken determine the switching properties and the memory qualityi. i.e. the ability to hold stored information, the memory cell »

Another insulating layer 40 , which is made up of silicon nitride (Si ^ N ^), for example, is arranged on the surface of the field oxide region 26, namely under the. Electrodes 50 and 52 for the source and drain regions 20 and 22 and in the memory gate region 30 above the gap gate regions 32 and the tunnel region.

called layer 40, is about 300-600 angstroms thick. As a result of the crystal structures of SiO ₂ and Si ₃ N ₄ , a charge storage area is located at the interface 46 between the tunnel gate layer 36 and the nitride layer 40. This charge storage area extends a little into the

Nitride layer 40 into it. To complete the

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-ΜΙ Memory cell 10 becomes a gate electrode 54, for example made of aluminum, arranged on the nitride layer 40 in the area of the memory gate area 30.

In the memory gate region 30 there are in the epitaxial layer 14 between the source and drain regions 20 and 22 Foreign matter of opposite conductivity type and a given concentration. In an N-channel memory cell, for example, the one foreign substance is Boron and the other phosphorus or arsenic. The implantation dose and energy of boron determine the threshold voltage in an N-channel memory cell. The implantation of phosphorus or arsenic, on the other hand, is used to reduce the Improve duct shielding. The double implantation of these foreign substances reduces the field in the salivary gate area 30 and thereby improves the channel shielding. This effect will be described later.

To explain the mode of operation of the EAROM gap-gate memory cell 10 shown in FIG. 1, it is initially assumed that the drain region 22 and the source region 20 are at ground potential. If a voltage of a suitable magnitude and polarity is now applied to the gate electrode 54, charges of the opposite ² ^ polarity are attracted from the epitaxial layer 14. If, for example, a negative voltage is applied to the gate electrode 54, then positive charge carriers (holes) are attracted from the epitaxial layer and tunnel out through it. Tunnel gate layer 36 and are built up silicon dioxide

captured at the boundary layer 46. The charge carriers also tunnel into the nitride layer 40 in and are held there. Since silicon dioxide silicon nitride insulators are excellent quality, the cargoes remain at their trapping points for an extremely long time.

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-ΜΙ The N-channel EAROM split gate memory cell 10 is thus "written" in a low conductivity state (or OFF state), that a positive voltage of about 25 volts to the gate electrode 54 is applied. As a result, negative charges are stored at the silicon dioxide-silicon nitride interface 46. These negative charges raise the threshold voltage to a higher positive level. In "written" state, the EAROM memory cell 10 is operating in the enrichment condition, ie., That a positive voltage must be applied to the gate electrode 54, in order to make the channel between the source region 20 and the drain region 22 conductive. A threshold voltage typical of the "written" state for a

N-channel EAROM memory cell 10 is approximately 6 volts. 15th

The memory cell is thereby "erased" to a low threshold voltage (or a highly conductive state) a negative voltage of, for example, -25 volts is applied to the gate electrode 54. This negative tension attracts positive charge carriers (holes) to the interface 4 6. The positive charge in turn leads to a conductive one Channel under the tunnel gate layer 36. In the erased state is working . the area under the tunnel gate layer 36 is a depletion mode = accordingly

^ 5 the two not intended for storage and Fission gate regions 32 acting as enrichment arrangements are connected in series.

The threshold voltage for the deleted state is therefore

in accordance with the thickness of the gate in the gap gate areas 32 of the memory cell not provided for storage purposes 10 set. The threshold voltage for the deleted State is in the order of magnitude of, for example, 1j5 volts, the comparatively large difference or that Window between the threshold voltages for the

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written and erased states allow reliable data decoding.

It is known that the threshold voltage V_ ,, at which the memory cell switches from one state (ON / OFF) to the other state (OFF / ON) by implantation suitable foreign matter in the underlying the memory gate area 30 silicon to control. For example becomes an n-channel memory cell through increased implantation shifted more to the enrichment state of boron ions. I.e./ that the threshold voltage is more positive will. Such a memory cell leads to a P-channel memory cell Implantation of boron ions has the opposite effect, i.e. a higher boron dose a P-channel memory cell from the enrichment type to the depletion type shifts (the threshold voltage becomes less positive and eventually negative).

In FIG. 2, the concentration of foreign matter indicated on the vertical axis is a function of its depth of penetration recorded in the epitaxial layer 14 or the substrate. The vertical line shown in FIG represents the interface 60 between the tunnel gate layer 36 made of silicon dioxide and the epitaxial layer 14 made of silicon arranged on the substrate.

The solid curve 62 gives the impurity concentration achieved by implantation of boron ions under the tunnel gate layer 36 of the N-channel EAROM memory cell 10

° again. From Fig. 2, the peak of the boron impurity concentration lies slightly below the interface.

The gate and drain are in the channel shielding state

of the erased memory transistor with a write chip

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voltage of approximately +25 volts for N-EAROM memory cells biased. The source is kept "floating" so that it floats. Since the deleted, as an N channel serving tunnel gate layer 36 is a depletion arrangement and the (enrichmentr) gap gate regions not intended for storage functions 32 are switched on because of the +25 volts, the source 20 also floats +25 volts when the gate and drain are biased at 25 volts. That is, the source and drain with respect to the substrate are reverse biased and the source, gate and drain are at the same potential.

Up until now it was assumed that the erased state would be retained because the source, gate and drain are at the same potential. However, this has been found to end at the inversion layer in the silicon electric field in the memory gate area leads to a back shift of the charges in the nitride layer. Since the gate is positively biased with respect to the silicon, those in the silicon dioxide-silicon nitride boundary layer captured holes (this is a reminder that the memory cell is in the erased State) into the silicon and the electrons from the inversion layer are injected into the storage interface will.

As a result of such charge movements, the memory cell can finally reach the written state after a long period of time. This fact poses the problem of ^duct shielding. The problem of channel shielding could be addressed by keeping the electric field that leads to a charge shift in the storage state as low as possible. This could be achieved by reducing the surface concentration of impurities in the silicon. However, if this surface concentration is arbitrarily reduced, then for Pat 187 / 3-81E, GM 187 / 4-81E - 17 -

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Split gate storage cells also use the erase / write window mentioned above narrower. This in turn raises potential problems with regard to writing and erasing the Memory cell on. However, these potential problems are just as undesirable as the channel shielding problems. Accordingly would provide a solution that simultaneously overcomes the potential problems and the duct shielding problems will lead to considerable progress.

In general, the channel shielding depends on the thickness of the nitride layer 40 and the surface concentration of impurities in the silicon epitaxial layer 14. The higher the concentration of impurities on the surface of the epitaxial layer 14, the greater the field strength and the easier it is for charges to migrate away from the nitride layer 40 and to reverse the erased state. On the application side, the aim was therefore to shift the maximum of the foreign matter concentration away from the interface 60 more downwards (into the epitaxial layer 14). To this end, a foreign matter was opposed. Conductivity type, for example phosphorus implanted in the immediate vicinity of the Si-SiO ₂ interface 60. In terms of electrical conductivity, phosphorus counteracts boron. The result of this is that the peak of the surface concentration is shifted more to the right (in FIG. 2), that is to say more into the epitaxial layer 14 - with the result that the surface concentration of impurities at the surface or boundary layer 60 is reduced. Since the two impurity concentrations (not additive purposes) overlap each other in the subtractive sense is obtained as a result, instead of the ursprüngliehen boron concentration profile 62 a concentration profile corresponding to the curve 66. As a result, the \ effective impurity surface concentration therefore is reduced at the interface 60th

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This additional shallow implantation of phosphorus does not result in a greater change in the width of the depletion layer, which is illustrated by the dashed area 68 in FIG. Accordingly, the threshold _{voltage V T is} practically not changed and the aforementioned threshold voltage window remains essentially constant.

In other words, the phosphorus compensates for the boron on the surface. The electric field between the gate and the silicon depends on the surface concentration of impurities. As the surface concentration has been decreased, the electric field also becomes weaker. As explained above, this leads to an improvement in Kanalab- ¹ ^ shielding.

The steps for producing an EAROM gap-gate memory cell according to the invention are explained with reference to FIGS. 3A to 3F. An N-type substrate 12 serves as a mechanical ² ^ carrier sufficient strength for a grown on the substrate 12. P-type epitaxial layer 14 by diffusion is allowed serving as channel stopper, N-type diffusion isolation regions 16 in the epitaxial layer 14 grow. A silicon dioxide layer 19 is applied to the entire surface of the epitaxial layer 14, for example by known oxidation techniques.

Then the N-conducting layers are in the epitaxial layer Source and drain regions 20 and 22 formed by diffusion. The formation of the N-conductive Source and drain regions 20 and 22 made up of material occur in the usual manner through the silicon dioxide layer 19 through.

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According to FIG. 3C, a further oxide layer is deposited on the upper surface of the preceding silicon dioxide layer 19 applied to produce the field oxide layer 26 by a conventional pyrolytic reaction.

The field oxide layer 26 is sufficiently thick, for example 1-2μπι.

According to FIG. 3D, the field oxide layer 26 is partially etched in such a way that the vertical insulating webs 29 for delimitation of the memory gate area 30 can be formed. The silicon oxide gap gate regions are then formed in the etched memory gate region 30 32 thermally grown to a thickness of about 400-600 angstroms. The one for storage purposes The tunnel region 34 serving is then defined by photolithographic processes.

The foreign matter implantation takes place in the memory gate area and the tunnel area 34. The implantation in the tunnel area 34 plays a particularly important role here Role as it controls the storage characteristics and channel shielding. When the foreign matter is implanted The following parameters are preferably adhered to by means of ion implantation:

Boron 5.5 χ 10 ¹² cm ² at 35 KeV typical

12-2

Phosphorus 1.7 χ 10 cm at 80 KeV typical

The tunnel area 34 is now up to the surface of the epitaxial layer 14 etched away in order to be able to form the tunnel area in the memory gate area 30. In the tunnel

The silicon dioxide tunnel gate 30 then becomes rich 34

layer 36 with. grown to a thickness of about 10-40 angstroms. The growth takes place through thermal reaction of oxygen with the silicon substrate or the Epitaxial layer 14. The growth of the tunnel gate layer 36 can be carried out at atmospheric pressure. However, if the storage properties of the EAROM storage

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cell will be improved, then the growing up of the Silicon oxide tunnel gate layer 36 carried out by means of an oxidation reaction taking place at low pressure = This type of growing up is in the German patent application P 31 04892 «7 of the applicant or in his U.S. Patent Application 120,791 filed February 12, 1980 been »

Following this, the silicon nitride layer 40 is applied to the entire memory cell? preferably by means of a chemical vapor separation technique. Ammonia gas (WH ^) is preferably introduced into a furnace _{at low speed and low pressure together with another gas, for example dichlorosilane (SiH 9} Cl ₉₎

as long as maintained, until the silicon nitride layer has reached the desired thickness. This thickness is, for example, 300-600 angstroms »the ratio of Ammonia to dichlorosilane is in the range of 50: 1. 20th

The application of the silicon nitride layer 40 results in the interface 46 in the memory channel between the tunnel gate layer 36 and the silicon nitride layer 40. The tunneling through the thin tunnel gate layer 36 to the demand ² ^ following charge storage at the interface 46 results in the previously described storage characteristics of the memory cell 10th

The Pig = 1 already described finally shows the

Fully manufactured EAROM gap gate = memory cell The intermediate steps for manufacturing contact holes ι which lead through the nitride and oxide layers 40 and 26 to the source and drain regions 20 and 22, have not been shown in detail »To complete the memory cell i-jerden who have favourited electrodes

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50 and 52 for the source and drain regions 20 and 22 and the gate electrode 54 for the Turinel area 34 attached / for example by suitable evaporation techniques. The exact location of the electrodes 50 to 54 is determined by means of photolithographic processes.

The use of double implantation of foreign matter increases the ability of channel shielding in the EAROM memory cell compared to such EAROM memory cells, in which only a single comparable foreign matter implantation has been carried out.

In the present case, the invention was carried out on the basis of an EAROM Split gate memory cell (also split gate memory cell

! 5). The teaching of the invention is but not limited to such memory cells. Rather, it is also on memory cells with a flat or planar gate can be used, that is to say with a gate without the gap gate regions 32 the storage channel between the IsolierStegen 29 over the • entire memory gate area 30.

The teaching according to the invention can also be implemented on a P-channel rEAROM memory cell. In this case, phosphorus or arsenic, for example, is used as a foreign substance, by means of whose concentration the threshold voltage V _{T is controlled.} In this case, for example, is used to shift the concentration peak

Boron.
30th

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Claims (1)

Expectations Electrically changeable semiconductor read-only memory with a) a substrate (12, 14) made of a material of a first conductivity type, b) source and drain regions formed in the substrate (12, 14) (20,22) of a second conductivity type, and c) a memory gate region (30) which is arranged between the source region and the drain region (20, 22) and has: Co1) two within the memory gate area (30) on the Substrate (12,14) stacked Isolator ™ layers (35,40), c “2) at the interface (45) between the two insulator layers (36,40) storable electrical charges and Co3) connection electrodes (50,52,54) for the source and the Drain area (20,22) and the upper insulator layer (40) in the memory gate area (30), characterized in that d) the substrate (12, 14) in the memory gate area (30) in this way is doped with foreign substances that the maximum of the profile (66) of the effective surface concentration of a'ersten Foreign matter of a first conductivity type from the substrate surface (60) moved away in the direction of the substrate interior is ο 2ο read-only memory according to claim 1, characterized in that to develop the surface concentration profile of the foreign - 0 - substances in the substrate (12,14) in the memory gate area (30) In addition, impurities of a second conductivity type are doped, and in this case the first and the second conductivity type opposite: show leadership behavior. 3. Read-only memory according to claim 1 or. 2, characterized in that that the superposed insulator layers (36, 40) essentially consist of one on the substrate surface arranged silicon dioxide layer (36) and arranged on the silicon dioxide layer (36) Silicon nitride layer (40) exist. 4. Read-only memory according to at least one of the claims 1-3, characterized in that the substrate (12,14) in the memory gate area (30) with the foreign matter (62) of the first conductivity type is doped in such a way that a predetermined threshold voltage V ™ for transferring the read-only memory is achieved in the enrolled state. 5. Read-only memory according to at least one of claims 1-4, characterized in that the foreign substance (62) of the first conductivity type is opposite to the conductivity type of the source and drain regions (20, 22) Has line type. 6. Read-only memory according to claim 5, characterized in that the foreign matter with the second conductivity type is the same Conduction type like the source and drain regions (20,22). 7. Read-only memory according to at least one of the claims 1-6, characterized in that the substrate (12,14) made of a P-conductive material and the source as well the drain region (20, 22) are constructed from an N-conductive material. Pat 187 / 3-81E, GM 187 / 4-81E - 3 - GENERAL INSTRUMENT CORPORATION 8 »Read-only memory according to claim T _0, characterized in that the foreign substance with the first conductivity type is boron. "Read-only memory according to claim 7 or 8, characterized in that that the impurity of the second conductivity type is an impurity composed of phosphorus and arsenic Group is » 1Oo read-only memory according to at least one of the claims 4-9 j, characterized by an ion implantation received boron endowment. 11. Read-only memory according to claim 10, characterized by ip _3 ίο -3 one with about 5 × 10 cm to 7x10 cm boron ions with an energy of 30-40 KeV into the substrate (12,14) implanted doping. 12. Read-only memory according to at least one of the claims 7-11 ρ characterized by a foreign substance doping, which by ion implantation of phosphorus in the substrate (12,14) in the memory gate area (30) with about 1x10 ¹² 12th
Atoms / dm ³ to 2x10 atoms / cm ³ and an energy of 70-80 KeV is available » ο method of making an electrically modifiable Semiconductor read-only memory, in which a) a substrate (12, 14) made of a material of a first Line type is established, b) source and drain regions (20,22) of a second conductivity type are formed in the substrate (12,14) and c) a memory gate region (30) through between the source and drain regions (20, 22) c, 1) superimpose two insulator layers (36, 40) the substrate (12, 14) in the memory gate area (30), 35 Pat 187 / 3-81E, GM 187 / 4-81E - 4 - GENERAL INSTRUMENT CORPORATION c.2) Provision of storable at the interface (46) between the two insulator layers (36, 40) electrical charges and c.3) Terminating electrodes (50,52,54) on the Source region (20), the drain region (22) and the upper insulator layer (40) in the memory gate area (30)
is built, characterized in that the like) ^as s in the memory gate region (30) having a first impurity (62) of a first conductivity type and a second impurity of an opposite first conductivity type said second conductivity type is doped in such a substrate (12,14), that a desired impurity concentration profile in the upper * surface area (60) of the substrate (12,14) in Memory gate area (30) is created. Pat 187 / 3-81E, GM 187 / 4-81E - 5 - GENERAL INSTRUMENT CORPORATION