DE3177048D1 - Method for making fine deep dielectric isolation - Google Patents
Method for making fine deep dielectric isolationInfo
- Publication number
- DE3177048D1 DE3177048D1 DE8181101365T DE3177048T DE3177048D1 DE 3177048 D1 DE3177048 D1 DE 3177048D1 DE 8181101365 T DE8181101365 T DE 8181101365T DE 3177048 T DE3177048 T DE 3177048T DE 3177048 D1 DE3177048 D1 DE 3177048D1
- Authority
- DE
- Germany
- Prior art keywords
- dielectric isolation
- making fine
- deep dielectric
- fine deep
- making
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3088—Process specially adapted to improve the resolution of the mask
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/051—Etching
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/085—Isolated-integrated
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/117—Oxidation, selective
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/131—Reactive ion etching rie
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
- Y10S438/947—Subphotolithographic processing
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/130,882 US4274909A (en) | 1980-03-17 | 1980-03-17 | Method for forming ultra fine deep dielectric isolation |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3177048D1 true DE3177048D1 (en) | 1989-06-08 |
Family
ID=22446794
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8181101365T Expired DE3177048D1 (en) | 1980-03-17 | 1981-02-25 | Method for making fine deep dielectric isolation |
Country Status (4)
Country | Link |
---|---|
US (1) | US4274909A (de) |
EP (1) | EP0036111B1 (de) |
JP (1) | JPS56137651A (de) |
DE (1) | DE3177048D1 (de) |
Families Citing this family (42)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4394196A (en) * | 1980-07-16 | 1983-07-19 | Tokyo Shibaura Denki Kabushiki Kaisha | Method of etching, refilling and etching dielectric grooves for isolating micron size device regions |
US4325182A (en) * | 1980-08-25 | 1982-04-20 | General Electric Company | Fast isolation diffusion |
JPS5864044A (ja) * | 1981-10-14 | 1983-04-16 | Toshiba Corp | 半導体装置の製造方法 |
US4390393A (en) * | 1981-11-12 | 1983-06-28 | General Electric Company | Method of forming an isolation trench in a semiconductor substrate |
NL8105559A (nl) * | 1981-12-10 | 1983-07-01 | Philips Nv | Werkwijze voor het aanbrengen van een smalle groef in een substraatgebied, in het bijzonder een halfgeleidersubstraatgebied. |
JPS58100441A (ja) * | 1981-12-10 | 1983-06-15 | Toshiba Corp | 半導体装置の製造方法 |
US4419809A (en) * | 1981-12-30 | 1983-12-13 | International Business Machines Corporation | Fabrication process of sub-micrometer channel length MOSFETs |
JPS5935445A (ja) * | 1982-08-24 | 1984-02-27 | Nippon Telegr & Teleph Corp <Ntt> | 半導体装置の製造方法 |
US4444605A (en) * | 1982-08-27 | 1984-04-24 | Texas Instruments Incorporated | Planar field oxide for semiconductor devices |
JPS5978542A (ja) * | 1982-10-27 | 1984-05-07 | Nippon Telegr & Teleph Corp <Ntt> | 半導体装置の製造方法 |
DE3242113A1 (de) * | 1982-11-13 | 1984-05-24 | Ibm Deutschland Gmbh, 7000 Stuttgart | Verfahren zur herstellung einer duennen dielektrischen isolation in einem siliciumhalbleiterkoerper |
JPS60207339A (ja) * | 1984-03-30 | 1985-10-18 | Matsushita Electronics Corp | パタ−ン形成方法 |
NL8402859A (nl) * | 1984-09-18 | 1986-04-16 | Philips Nv | Werkwijze voor het vervaardigen van submicrongroeven in bijvoorbeeld halfgeleidermateriaal en met deze werkwijze verkregen inrichtingen. |
US4982262A (en) * | 1985-01-15 | 1991-01-01 | At&T Bell Laboratories | Inverted groove isolation technique for merging dielectrically isolated semiconductor devices |
JPS61198780A (ja) * | 1985-02-28 | 1986-09-03 | Toshiba Corp | 半導体装置の製造方法 |
US4753901A (en) * | 1985-11-15 | 1988-06-28 | Ncr Corporation | Two mask technique for planarized trench oxide isolation of integrated devices |
US4654119A (en) * | 1985-11-18 | 1987-03-31 | International Business Machines Corporation | Method for making submicron mask openings using sidewall and lift-off techniques |
US4826781A (en) * | 1986-03-04 | 1989-05-02 | Seiko Epson Corporation | Semiconductor device and method of preparation |
JPS6318673A (ja) * | 1986-07-11 | 1988-01-26 | Yamaha Corp | 半導体装置の製法 |
JPS6377122A (ja) * | 1986-09-19 | 1988-04-07 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
FR2610141B1 (fr) * | 1987-01-26 | 1990-01-19 | Commissariat Energie Atomique | Circuit integre cmos et procede de fabrication de zones d'isolation electrique dans ce circuit |
JPH0727974B2 (ja) * | 1988-04-26 | 1995-03-29 | 三菱電機株式会社 | 半導体記憶装置の製造方法 |
US5008210A (en) * | 1989-02-07 | 1991-04-16 | Hewlett-Packard Company | Process of making a bipolar transistor with a trench-isolated emitter |
JP2870054B2 (ja) * | 1989-10-25 | 1999-03-10 | ソニー株式会社 | 半導体装置の製造方法 |
US5124775A (en) * | 1990-07-23 | 1992-06-23 | National Semiconductor Corporation | Semiconductor device with oxide sidewall |
JPH0568822U (ja) * | 1991-11-11 | 1993-09-17 | 株式会社日本ばし大増 | 弁当箱包装用の紙ケース |
KR0120572B1 (ko) * | 1994-05-04 | 1997-10-20 | 김주용 | 반도체 소자 및 그 제조방법 |
US5426059A (en) * | 1994-05-26 | 1995-06-20 | Queyssac; Daniel G. | Method of making vertically stacked bipolar semiconductor structure |
US5904539A (en) * | 1996-03-21 | 1999-05-18 | Advanced Micro Devices, Inc. | Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties |
WO1997038442A1 (en) * | 1996-04-10 | 1997-10-16 | Advanced Micro Devices, Inc. | Semiconductor trench isolation with improved planarization methodology |
US5926713A (en) * | 1996-04-17 | 1999-07-20 | Advanced Micro Devices, Inc. | Method for achieving global planarization by forming minimum mesas in large field areas |
US5899727A (en) * | 1996-05-02 | 1999-05-04 | Advanced Micro Devices, Inc. | Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization |
US5929368A (en) * | 1996-12-09 | 1999-07-27 | The Ensign-Bickford Company | Hybrid electronic detonator delay circuit assembly |
SE519975C2 (sv) * | 1999-06-23 | 2003-05-06 | Ericsson Telefon Ab L M | Halvledarstruktur för högspänningshalvledarkomponenter |
WO2001048814A1 (en) * | 1999-12-24 | 2001-07-05 | Koninklijke Philips Electronics N.V. | Method of manufacturing a semiconductor device comprising semiconductor elements formed in a top layer of a silicon wafer situated on a buried insulating layer |
DE102004034572B4 (de) * | 2004-07-17 | 2008-02-28 | Infineon Technologies Ag | Verfahren zum Herstellen einer Struktur auf der Oberfläche eines Substrats |
US20070001267A1 (en) * | 2004-11-22 | 2007-01-04 | Farrokh Ayazi | Methods of forming oxide masks with submicron openings and microstructures formed thereby |
US20080001213A1 (en) * | 2006-06-29 | 2008-01-03 | International Business Machines Corporation | Structures and methods for manufacturing high density narrow width mosfets |
KR100822592B1 (ko) * | 2007-03-23 | 2008-04-16 | 주식회사 하이닉스반도체 | 반도체 소자의 미세 패턴 형성방법 |
US8084347B2 (en) | 2008-12-31 | 2011-12-27 | Sandisk 3D Llc | Resist feature and removable spacer pitch doubling patterning method for pillar structures |
US8114765B2 (en) | 2008-12-31 | 2012-02-14 | Sandisk 3D Llc | Methods for increased array feature density |
US11887945B2 (en) * | 2020-09-30 | 2024-01-30 | Wolfspeed, Inc. | Semiconductor device with isolation and/or protection structures |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL153374B (nl) * | 1966-10-05 | 1977-05-16 | Philips Nv | Werkwijze ter vervaardiging van een halfgeleiderinrichting voorzien van een oxydelaag en halfgeleiderinrichting vervaardigd volgens de werkwijze. |
US3534234A (en) * | 1966-12-15 | 1970-10-13 | Texas Instruments Inc | Modified planar process for making semiconductor devices having ultrafine mesa type geometry |
US3725160A (en) * | 1970-12-30 | 1973-04-03 | Texas Instruments Inc | High density integrated circuits |
US3648125A (en) * | 1971-02-02 | 1972-03-07 | Fairchild Camera Instr Co | Method of fabricating integrated circuits with oxidized isolation and the resulting structure |
US3979237A (en) * | 1972-04-24 | 1976-09-07 | Harris Corporation | Device isolation in integrated circuits |
US3966577A (en) * | 1973-08-27 | 1976-06-29 | Trw Inc. | Dielectrically isolated semiconductor devices |
US3956033A (en) * | 1974-01-03 | 1976-05-11 | Motorola, Inc. | Method of fabricating an integrated semiconductor transistor structure with epitaxial contact to the buried sub-collector |
US3892608A (en) * | 1974-02-28 | 1975-07-01 | Motorola Inc | Method for filling grooves and moats used on semiconductor devices |
US3969168A (en) * | 1974-02-28 | 1976-07-13 | Motorola, Inc. | Method for filling grooves and moats used on semiconductor devices |
US3979765A (en) * | 1974-03-07 | 1976-09-07 | Signetics Corporation | Silicon gate MOS device and method |
JPS5131186A (de) * | 1974-09-11 | 1976-03-17 | Hitachi Ltd | |
JPS5146083A (en) * | 1974-10-18 | 1976-04-20 | Hitachi Ltd | Handotaisochino seizohoho |
DE2547792C3 (de) * | 1974-10-25 | 1978-08-31 | Hitachi, Ltd., Tokio | Verfahren zur Herstellung eines Halbleiterbauelementes |
US3920483A (en) * | 1974-11-25 | 1975-11-18 | Ibm | Method of ion implantation through a photoresist mask |
US4037307A (en) * | 1975-03-21 | 1977-07-26 | Bell Telephone Laboratories, Incorporated | Methods for making transistor structures |
GB1527894A (en) * | 1975-10-15 | 1978-10-11 | Mullard Ltd | Methods of manufacturing electronic devices |
GB1535086A (en) * | 1976-03-22 | 1978-12-06 | Western Electric Co | Manufacture of transistors |
US4093503A (en) * | 1977-03-07 | 1978-06-06 | International Business Machines Corporation | Method for fabricating ultra-narrow metallic lines |
US4104086A (en) * | 1977-08-15 | 1978-08-01 | International Business Machines Corporation | Method for forming isolated regions of silicon utilizing reactive ion etching |
US4209349A (en) * | 1978-11-03 | 1980-06-24 | International Business Machines Corporation | Method for forming a narrow dimensioned mask opening on a silicon body utilizing reactive ion etching |
US4209350A (en) * | 1978-11-03 | 1980-06-24 | International Business Machines Corporation | Method for forming diffusions having narrow dimensions utilizing reactive ion etching |
US4211582A (en) * | 1979-06-28 | 1980-07-08 | International Business Machines Corporation | Process for making large area isolation trenches utilizing a two-step selective etching technique |
JPS5789226A (en) * | 1980-11-19 | 1982-06-03 | Ibm | Method of etching silicon nitride layer |
-
1980
- 1980-03-17 US US06/130,882 patent/US4274909A/en not_active Expired - Lifetime
-
1981
- 1981-02-04 JP JP1447181A patent/JPS56137651A/ja active Granted
- 1981-02-25 EP EP81101365A patent/EP0036111B1/de not_active Expired
- 1981-02-25 DE DE8181101365T patent/DE3177048D1/de not_active Expired
Also Published As
Publication number | Publication date |
---|---|
EP0036111A2 (de) | 1981-09-23 |
JPS6145382B2 (de) | 1986-10-07 |
EP0036111B1 (de) | 1989-05-03 |
EP0036111A3 (en) | 1986-01-02 |
US4274909A (en) | 1981-06-23 |
JPS56137651A (en) | 1981-10-27 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |