DE3274910D1 - Device for loading and reading different chains of bistable circuits in a data processing system - Google Patents

Device for loading and reading different chains of bistable circuits in a data processing system

Info

Publication number
DE3274910D1
DE3274910D1 DE8282430028T DE3274910T DE3274910D1 DE 3274910 D1 DE3274910 D1 DE 3274910D1 DE 8282430028 T DE8282430028 T DE 8282430028T DE 3274910 T DE3274910 T DE 3274910T DE 3274910 D1 DE3274910 D1 DE 3274910D1
Authority
DE
Germany
Prior art keywords
loading
data processing
processing system
bistable circuits
different chains
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8282430028T
Other languages
English (en)
Inventor
D Angeac Didier Dupuy
Michel Andre Lechaczynski
Andre Pauporte
Pierre Thery
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Compagnie IBM France SAS
International Business Machines Corp
Original Assignee
Compagnie IBM France SAS
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Compagnie IBM France SAS, International Business Machines Corp filed Critical Compagnie IBM France SAS
Application granted granted Critical
Publication of DE3274910D1 publication Critical patent/DE3274910D1/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
DE8282430028T 1982-09-28 1982-09-28 Device for loading and reading different chains of bistable circuits in a data processing system Expired DE3274910D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP82430028A EP0104293B1 (de) 1982-09-28 1982-09-28 Anordnung zum Laden und Lesen verschiedener Kippschaltungsketten in einem Datenverarbeitungssystem

Publications (1)

Publication Number Publication Date
DE3274910D1 true DE3274910D1 (en) 1987-02-05

Family

ID=8189984

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8282430028T Expired DE3274910D1 (en) 1982-09-28 1982-09-28 Device for loading and reading different chains of bistable circuits in a data processing system

Country Status (4)

Country Link
US (1) US4597042A (de)
EP (1) EP0104293B1 (de)
JP (1) JPS5975346A (de)
DE (1) DE3274910D1 (de)

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0151653B1 (de) * 1983-12-15 1987-09-16 International Business Machines Corporation Vorrichtung zur Parallel-Serien/Serien-Parallelwandlung von aus variabler Länge bestehenden Bitkonfigurationen
JPH0772744B2 (ja) * 1984-09-04 1995-08-02 株式会社日立製作所 半導体集積回路装置
JPH0668732B2 (ja) * 1984-11-21 1994-08-31 株式会社日立製作所 情報処理装置のスキヤン方式
GB8518860D0 (en) * 1985-07-25 1985-08-29 Int Computers Ltd Digital integrated circuits
NL8502476A (nl) * 1985-09-11 1987-04-01 Philips Nv Werkwijze voor het testen van dragers met meerdere digitaal-werkende geintegreerde schakelingen, drager voorzien van zulke schakelingen, geintegreerde schakeling geschikt voor het aanbrengen op zo'n drager, en testinrichting voor het testen van zulke dragers.
DE3687407T2 (de) * 1985-10-15 1993-06-24 Sony Corp Logische schaltung mit zusammengeschalteten mehrtorflip-flops.
US4701921A (en) * 1985-10-23 1987-10-20 Texas Instruments Incorporated Modularized scan path for serially tested logic circuit
US5032783A (en) * 1985-10-23 1991-07-16 Texas Instruments Incorporated Test circuit and scan tested logic device with isolated data lines during testing
US4710931A (en) * 1985-10-23 1987-12-01 Texas Instruments Incorporated Partitioned scan-testing system
JPH0690260B2 (ja) * 1986-05-30 1994-11-14 三菱電機株式会社 論理回路試験装置
JPH0691140B2 (ja) * 1986-07-11 1994-11-14 日本電気株式会社 半導体集積回路
US4710927A (en) * 1986-07-24 1987-12-01 Integrated Device Technology, Inc. Diagnostic circuit
US4872169A (en) * 1987-03-06 1989-10-03 Texas Instruments Incorporated Hierarchical scan selection
US4876501A (en) * 1987-04-13 1989-10-24 Prime Computer, Inc. Method and apparatus for high accuracy measurment of VLSI components
JPS63256877A (ja) * 1987-04-14 1988-10-24 Mitsubishi Electric Corp テスト回路
US4860290A (en) * 1987-06-02 1989-08-22 Texas Instruments Incorporated Logic circuit having individually testable logic modules
US5535331A (en) * 1987-09-04 1996-07-09 Texas Instruments Incorporated Processor condition sensing circuits, systems and methods
JPH01132980A (ja) * 1987-11-17 1989-05-25 Mitsubishi Electric Corp テスト機能付電子回路装置
JPH01132979A (ja) * 1987-11-17 1989-05-25 Mitsubishi Electric Corp テスト機能付電子回路
DE68928837T2 (de) * 1988-09-07 1999-05-12 Texas Instruments Inc Prüf-Puffer/Register
US6304987B1 (en) * 1995-06-07 2001-10-16 Texas Instruments Incorporated Integrated test circuit
DE68928613T2 (de) * 1988-09-07 1998-09-24 Texas Instruments Inc Bidirektionale-Boundary-Scan-Testzelle
US5483518A (en) 1992-06-17 1996-01-09 Texas Instruments Incorporated Addressable shadow port and protocol for serial bus networks
JP3005250B2 (ja) 1989-06-30 2000-01-31 テキサス インスツルメンツ インコーポレイテツド バスモニター集積回路
US5805792A (en) * 1989-07-31 1998-09-08 Texas Instruments Incorporated Emulation devices, systems, and methods
JP2632731B2 (ja) * 1989-08-02 1997-07-23 三菱電機株式会社 集積回路装置
US5079725A (en) * 1989-11-17 1992-01-07 Ibm Corporation Chip identification method for use with scan design systems and scan testing techniques
US5274648A (en) * 1990-01-24 1993-12-28 International Business Machines Corporation Memory card resident diagnostic testing
US6675333B1 (en) * 1990-03-30 2004-01-06 Texas Instruments Incorporated Integrated circuit with serial I/O controller
US5581564A (en) * 1990-12-18 1996-12-03 Integrated Device Technology, Inc. Diagnostic circuit
US5271019A (en) * 1991-03-15 1993-12-14 Amdahl Corporation Scannable system with addressable scan reset groups
US5701309A (en) * 1992-12-02 1997-12-23 At&T Global Information Solutions Company Automated test equipment digital tester expansion apparatus
US5463338A (en) * 1993-06-07 1995-10-31 Vlsi Technology, Inc. Dual latch clocked LSSD and method
US5530706A (en) * 1993-10-15 1996-06-25 Hewlett-Packard Company Non-destructive sampling of internal states while operating at normal frequency
US5448525A (en) * 1994-03-10 1995-09-05 Intel Corporation Apparatus for configuring a subset of an integrated circuit having boundary scan circuitry connected in series and a method thereof
US5821773A (en) * 1995-09-06 1998-10-13 Altera Corporation Look-up table based logic element with complete permutability of the inputs to the secondary signals
US5969538A (en) 1996-10-31 1999-10-19 Texas Instruments Incorporated Semiconductor wafer with interconnect between dies for testing and a process of testing
US5869979A (en) 1996-04-05 1999-02-09 Altera Corporation Technique for preconditioning I/Os during reconfiguration
US6028983A (en) * 1996-09-19 2000-02-22 International Business Machines Corporation Apparatus and methods for testing a microprocessor chip using dedicated scan strings
US6408413B1 (en) 1998-02-18 2002-06-18 Texas Instruments Incorporated Hierarchical access of test access ports in embedded core integrated circuits
US6405335B1 (en) 1998-02-25 2002-06-11 Texas Instruments Incorporated Position independent testing of circuits
US6184707B1 (en) 1998-10-07 2001-02-06 Altera Corporation Look-up table based logic element with complete permutability of the inputs to the secondary signals
US7058862B2 (en) 2000-05-26 2006-06-06 Texas Instruments Incorporated Selecting different 1149.1 TAP domains from update-IR state
US6728915B2 (en) 2000-01-10 2004-04-27 Texas Instruments Incorporated IC with shared scan cells selectively connected in scan path
US6769080B2 (en) 2000-03-09 2004-07-27 Texas Instruments Incorporated Scan circuit low power adapter with counter

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1927549A1 (de) * 1969-05-30 1970-12-03 Ibm Deutschland Fehlerpruefeinrichtung in elektronischen Datenverarbeitungsanlagen
FR2256706A5 (de) * 1973-12-27 1975-07-25 Cii
US4030072A (en) * 1974-12-18 1977-06-14 Xerox Corporation Computer system operation and control
US4041471A (en) * 1975-04-14 1977-08-09 Scientific Micro Systems, Inc. Data processing system including a plurality of programmed machines and particularly including a supervisor machine and an object machine
US4023142A (en) * 1975-04-14 1977-05-10 International Business Machines Corporation Common diagnostic bus for computer systems to enable testing concurrently with normal system operation
JPS5833576B2 (ja) * 1977-03-14 1983-07-20 株式会社東芝 計算機システムの故障診断装置
US4167041A (en) * 1977-04-05 1979-09-04 International Business Machines Corporation Status reporting
DE2842750A1 (de) * 1978-09-30 1980-04-10 Ibm Deutschland Verfahren und anordnung zur pruefung von durch monolithisch integrierten halbleiterschaltungen dargestellten sequentiellen schaltungen
US4268902A (en) * 1978-10-23 1981-05-19 International Business Machines Corporation Maintenance interface for a service processor-central processing unit computer system
US4326266A (en) * 1979-10-16 1982-04-20 Burroughs Corporation Monitoring system for a modular digital data processor
DE3029883A1 (de) * 1980-08-07 1982-03-11 Ibm Deutschland Gmbh, 7000 Stuttgart Schieberegister fuer pruef- und test-zwecke

Also Published As

Publication number Publication date
EP0104293A1 (de) 1984-04-04
JPS5975346A (ja) 1984-04-28
EP0104293B1 (de) 1986-12-30
JPS6338728B2 (de) 1988-08-02
US4597042A (en) 1986-06-24

Similar Documents

Publication Publication Date Title
DE3274910D1 (en) Device for loading and reading different chains of bistable circuits in a data processing system
DE3480134D1 (en) Device for reading and writing ic-external storage card
JPS56145456A (en) Improvement in electronic multiprocessor system for logic and digital data processing
DE3278650D1 (en) Memory module selection and reconfiguration apparatus in a data processing system
EP0149451A3 (en) Apparatus and method for reconfiguring a memory in a data processing system
GB2108277B (en) Tester for lsi devices and memory devices
IL86161A (en) Digital computer memory test method and apparatus
EP0268419A3 (en) Memory cartridge and data processing apparatus
EP0106056A3 (en) Device for the loading and in particular unloading of processing machines
EP0115609A3 (en) Addressing method and device for the storage of several data processing units in a bus system
EP0114190A3 (en) Method and apparatus for peripheral data handling hierarchies
KR910007408B1 (en) Semiconductor memory device which inspects errors and modifies them in output data
GB2182794B (en) Ic card for a processing device
JPS5332630A (en) Method and device for transferring information between information memory and computer
DE2966362D1 (en) Method and device for self-adaptive load association in a data processing system
EP0124799A3 (en) Memory access arrangement in a data processing system
JPS52112238A (en) Method and device for loading and reading data in computer random access main memory
DE3369018D1 (en) Apparatus and method of electromagnetically reading coordinate data
EP0121071A3 (en) Concurrent multi-lingual use in data processing systems
DE3175912D1 (en) Information transfer between a main storage and a cyclic bulk memory in a data processing system
DE3377821D1 (en) Apparatus and method for buffering data in a data processing system
GB2040521B (en) Method and apparatus for enhancing i/o transfers in a named data processing system
EP0100011A3 (en) Semiconductor memory device having data transmission and detection means
GB8307500D0 (en) Ensuring integrity of data in electronic memory
PH19476A (en) Method and apparatus for comparing data signals in a container inspection device

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee