DE3278868D1 - Memory device - Google Patents

Memory device

Info

Publication number
DE3278868D1
DE3278868D1 DE8282301773T DE3278868T DE3278868D1 DE 3278868 D1 DE3278868 D1 DE 3278868D1 DE 8282301773 T DE8282301773 T DE 8282301773T DE 3278868 T DE3278868 T DE 3278868T DE 3278868 D1 DE3278868 D1 DE 3278868D1
Authority
DE
Germany
Prior art keywords
memory device
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8282301773T
Other languages
English (en)
Inventor
Toshinori C O Nippon E Ohtsuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE3278868D1 publication Critical patent/DE3278868D1/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
DE8282301773T 1981-04-02 1982-04-02 Memory device Expired DE3278868D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56049756A JPS57164331A (en) 1981-04-02 1981-04-02 Buffer controller

Publications (1)

Publication Number Publication Date
DE3278868D1 true DE3278868D1 (en) 1988-09-08

Family

ID=12840026

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8282301773T Expired DE3278868D1 (en) 1981-04-02 1982-04-02 Memory device

Country Status (4)

Country Link
US (1) US4459681A (de)
EP (1) EP0062521B1 (de)
JP (1) JPS57164331A (de)
DE (1) DE3278868D1 (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4592019A (en) * 1983-08-31 1986-05-27 At&T Bell Laboratories Bus oriented LIFO/FIFO memory
EP0206743A3 (de) * 1985-06-20 1990-04-25 Texas Instruments Incorporated Asynchroner FIFO-Puffer mit Null-Durchfallzeit und eindeutiger Leer/Voll-Angabe
US4803654A (en) * 1985-06-20 1989-02-07 General Datacomm Industries, Inc. Circular first-in, first out buffer system for generating input and output addresses for read/write memory independently
US4694426A (en) * 1985-12-20 1987-09-15 Ncr Corporation Asynchronous FIFO status circuit
US5195056A (en) * 1987-05-21 1993-03-16 Texas Instruments, Incorporated Read/write memory having an on-chip input data register, having pointer circuits between a serial data register and input/output buffer circuits
JP2764908B2 (ja) * 1988-02-04 1998-06-11 日本電気株式会社 カスケード・バッファ回路
JPH0283899A (ja) * 1988-09-20 1990-03-23 Fujitsu Ltd 半導体記憶装置
US5267191A (en) * 1989-04-03 1993-11-30 Ncr Corporation FIFO memory system
JPH04301290A (ja) * 1991-03-28 1992-10-23 Nec Corp 先入れ先出しメモリ回路
US6374313B1 (en) * 1994-09-30 2002-04-16 Cirrus Logic, Inc. FIFO and method of operating same which inhibits output transitions when the last cell is read or when the FIFO is erased
US5740406A (en) * 1995-05-15 1998-04-14 Nvidia Corporation Method and apparatus for providing fifo buffer input to an input/output device used in a computer system
US5732011A (en) * 1996-07-03 1998-03-24 General Signal Corporation Digital system having high speed buffering
US6097655A (en) * 1998-04-03 2000-08-01 International Business Machines Corporation Pull through FIFO memory device
US20030140351A1 (en) * 1998-04-17 2003-07-24 Hoarty W. Leo Cable television system compatible bandwidth upgrade using embedded digital channels
US6433835B1 (en) * 1998-04-17 2002-08-13 Encamera Sciences Corporation Expanded information capacity for existing communication transmission systems
US20030112370A1 (en) * 2001-12-18 2003-06-19 Chris Long Adaptive expanded information capacity for communications systems
US7180942B2 (en) 2001-12-18 2007-02-20 Dotcast, Inc. Joint adaptive optimization of soft decision device and feedback equalizer
US20030219085A1 (en) * 2001-12-18 2003-11-27 Endres Thomas J. Self-initializing decision feedback equalizer with automatic gain control
US20030221086A1 (en) * 2002-02-13 2003-11-27 Simovich Slobodan A. Configurable stream processor apparatus and methods
WO2004075469A2 (en) * 2003-02-19 2004-09-02 Dotcast Inc. Joint, adaptive control of equalization, synchronization, and gain in a digital communications receiver
US6956775B1 (en) * 2003-12-31 2005-10-18 Intel Corporation Write pointer error recovery
EP2515226A1 (de) * 2011-04-21 2012-10-24 STMicroelectronics SA Anordnung

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7105512A (de) * 1971-04-23 1972-10-25
US3893088A (en) * 1971-07-19 1975-07-01 Texas Instruments Inc Random access memory shift register system
JPS5710516B2 (de) * 1972-12-13 1982-02-26
US4151609A (en) * 1977-10-11 1979-04-24 Monolithic Memories, Inc. First in first out (FIFO) memory
NL7713707A (nl) * 1977-12-12 1979-06-14 Philips Nv Informatiebuffergeheugen van het "eerst-in, eerst-uit" type met variabele ingang en vaste uitgang.

Also Published As

Publication number Publication date
JPS6155688B2 (de) 1986-11-28
EP0062521A2 (de) 1982-10-13
JPS57164331A (en) 1982-10-08
US4459681A (en) 1984-07-10
EP0062521B1 (de) 1988-08-03
EP0062521A3 (en) 1985-07-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition