DE3363515D1 - Integrated logic circuit incorporating fast sample control - Google Patents

Integrated logic circuit incorporating fast sample control

Info

Publication number
DE3363515D1
DE3363515D1 DE8383201122T DE3363515T DE3363515D1 DE 3363515 D1 DE3363515 D1 DE 3363515D1 DE 8383201122 T DE8383201122 T DE 8383201122T DE 3363515 T DE3363515 T DE 3363515T DE 3363515 D1 DE3363515 D1 DE 3363515D1
Authority
DE
Germany
Prior art keywords
logic circuit
integrated logic
circuit incorporating
sample control
fast sample
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8383201122T
Other languages
English (en)
Inventor
Nico Frits Benschop
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Application granted granted Critical
Publication of DE3363515D1 publication Critical patent/DE3363515D1/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5306—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with row wise addition of partial products
    • G06F7/5312—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with row wise addition of partial products using carry save adders
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3876—Alternation of true and inverted stages
DE8383201122T 1982-08-10 1983-07-29 Integrated logic circuit incorporating fast sample control Expired DE3363515D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL8203148A NL8203148A (nl) 1982-08-10 1982-08-10 Geintegreerde logische schakeling met snelle aftastbesturing.

Publications (1)

Publication Number Publication Date
DE3363515D1 true DE3363515D1 (en) 1986-06-19

Family

ID=19840124

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383201122T Expired DE3363515D1 (en) 1982-08-10 1983-07-29 Integrated logic circuit incorporating fast sample control

Country Status (5)

Country Link
US (1) US4567386A (de)
EP (1) EP0101123B1 (de)
JP (1) JPS5949021A (de)
DE (1) DE3363515D1 (de)
NL (1) NL8203148A (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6114215A (ja) * 1984-06-30 1986-01-22 Toyo Soda Mfg Co Ltd ブロック共重合体の製造方法
EP0225960B1 (de) * 1985-12-07 1991-03-20 Deutsche ITT Industries GmbH CMOS-Inverterkette
JP2664927B2 (ja) * 1988-04-25 1997-10-22 日本電気株式会社 信号発生回路
JP2639207B2 (ja) * 1989-12-08 1997-08-06 日本電気株式会社 出力回路
US5367691A (en) * 1991-04-15 1994-11-22 Motorola, Inc. Pipe-staggered apparatus and method utilizing carry look-ahead signal processing
US5506520A (en) * 1995-01-11 1996-04-09 International Business Machines Corporation Energy conserving clock pulse generating circuits
US5740094A (en) * 1995-08-21 1998-04-14 International Business Machines Corporation Self-timed multiplier array
US6917221B2 (en) * 2003-04-28 2005-07-12 International Business Machines Corporation Method and apparatus for enhancing the soft error rate immunity of dynamic logic circuits
EP2141585A1 (de) * 2008-06-27 2010-01-06 Panasonic Corporation Kombiniertes Addiererschaltungsarray und und/oder Fläche

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3518451A (en) * 1967-03-10 1970-06-30 North American Rockwell Gating system for reducing the effects of negative feedback noise in multiphase gating devices
US3497715A (en) * 1967-06-09 1970-02-24 Ncr Co Three-phase metal-oxide-semiconductor logic circuit
US3617767A (en) * 1970-02-11 1971-11-02 North American Rockwell Field effect transistor logic gate with isolation device for reducing power dissipation
US3601627A (en) * 1970-07-13 1971-08-24 North American Rockwell Multiple phase logic gates for shift register stages
US3740576A (en) * 1970-08-04 1973-06-19 Licentia Gmbh Dynamic logic interconnection
FR2105704A5 (de) * 1970-09-17 1972-04-28 Thomson Csf
US3747064A (en) * 1971-06-30 1973-07-17 Ibm Fet dynamic logic circuit and layout
US3965369A (en) * 1972-08-25 1976-06-22 Hitachi, Ltd. MISFET (Metal-insulator-semiconductor field-effect transistor) logical circuit having depletion type load transistor
JPS5738996B2 (de) * 1973-03-20 1982-08-18
US3883802A (en) * 1973-12-14 1975-05-13 Ibm Process for stress testing FET gates without the use of test patterns
US4291247A (en) * 1977-12-14 1981-09-22 Bell Telephone Laboratories, Incorporated Multistage logic circuit arrangement

Also Published As

Publication number Publication date
US4567386A (en) 1986-01-28
NL8203148A (nl) 1984-03-01
EP0101123A1 (de) 1984-02-22
JPS5949021A (ja) 1984-03-21
EP0101123B1 (de) 1986-05-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee