DE3369428D1 - Process for encapsulating semi-conductor components and encapsulated components so obtained - Google Patents

Process for encapsulating semi-conductor components and encapsulated components so obtained

Info

Publication number
DE3369428D1
DE3369428D1 DE8383103114T DE3369428T DE3369428D1 DE 3369428 D1 DE3369428 D1 DE 3369428D1 DE 8383103114 T DE8383103114 T DE 8383103114T DE 3369428 T DE3369428 T DE 3369428T DE 3369428 D1 DE3369428 D1 DE 3369428D1
Authority
DE
Germany
Prior art keywords
components
encapsulated
conductor
encapsulating
semi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8383103114T
Other languages
English (en)
Inventor
Georges Roche
Jacques Lantaires
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel CIT SA
Alcatel Lucent SAS
Original Assignee
Alcatel CIT SA
Alcatel SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel CIT SA, Alcatel SA filed Critical Alcatel CIT SA
Application granted granted Critical
Publication of DE3369428D1 publication Critical patent/DE3369428D1/de
Expired legal-status Critical Current

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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L2924/181—Encapsulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
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    • Y10S148/00—Metal treatment
    • Y10S148/135—Removal of substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor
    • Y10T156/1089—Methods of surface bonding and/or assembly therefor of discrete laminae to single face of additional lamina
    • Y10T156/1092—All laminae planar and face to face
    • Y10T156/1093—All laminae planar and face to face with covering of discrete laminae with additional lamina
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49169—Assembling electrical component directly to terminal or elongated conductor
    • Y10T29/49171—Assembling electrical component directly to terminal or elongated conductor with encapsulating
    • Y10T29/49172—Assembling electrical component directly to terminal or elongated conductor with encapsulating by molding of insulating material
DE8383103114T 1982-04-01 1983-03-29 Process for encapsulating semi-conductor components and encapsulated components so obtained Expired DE3369428D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8205624A FR2524707B1 (fr) 1982-04-01 1982-04-01 Procede d'encapsulation de composants semi-conducteurs, et composants encapsules obtenus

Publications (1)

Publication Number Publication Date
DE3369428D1 true DE3369428D1 (en) 1987-02-26

Family

ID=9272637

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383103114T Expired DE3369428D1 (en) 1982-04-01 1983-03-29 Process for encapsulating semi-conductor components and encapsulated components so obtained

Country Status (5)

Country Link
US (1) US4530152A (de)
EP (1) EP0091072B1 (de)
JP (1) JPS58182853A (de)
DE (1) DE3369428D1 (de)
FR (1) FR2524707B1 (de)

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IT1202657B (it) * 1987-03-09 1989-02-09 Sgs Microelettronica Spa Procedimento di fabbricazione di un dispositivo modulare di potenza a semiconduttore e dispositivo con esso ottenento
US5032543A (en) * 1988-06-17 1991-07-16 Massachusetts Institute Of Technology Coplanar packaging techniques for multichip circuits
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US5475920A (en) * 1990-08-01 1995-12-19 Burns; Carmen D. Method of assembling ultra high density integrated circuit packages
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FR2666173A1 (fr) * 1990-08-21 1992-02-28 Thomson Csf Structure hybride d'interconnexion de circuits integres et procede de fabrication.
DE4141775A1 (de) * 1991-12-18 1993-06-24 Manfred Band Verfahren zur herstellung einer elektronischen schaltung
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US5497032A (en) * 1993-03-17 1996-03-05 Fujitsu Limited Semiconductor device and lead frame therefore
US5801437A (en) * 1993-03-29 1998-09-01 Staktek Corporation Three-dimensional warp-resistant integrated circuit module method and apparatus
US5644161A (en) * 1993-03-29 1997-07-01 Staktek Corporation Ultra-high density warp-resistant memory module
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JPS58182853A (ja) 1983-10-25
US4530152A (en) 1985-07-23
EP0091072B1 (de) 1987-01-21
FR2524707B1 (fr) 1985-05-31
EP0091072A1 (de) 1983-10-12
FR2524707A1 (fr) 1983-10-07

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