DE3371565D1 - Self-testing method for logic circuitry - Google Patents

Self-testing method for logic circuitry

Info

Publication number
DE3371565D1
DE3371565D1 DE8383109950T DE3371565T DE3371565D1 DE 3371565 D1 DE3371565 D1 DE 3371565D1 DE 8383109950 T DE8383109950 T DE 8383109950T DE 3371565 T DE3371565 T DE 3371565T DE 3371565 D1 DE3371565 D1 DE 3371565D1
Authority
DE
Germany
Prior art keywords
self
logic circuitry
testing method
testing
circuitry
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8383109950T
Other languages
English (en)
Inventor
Paul Harold Bardell
William Howard Mcanney
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3371565D1 publication Critical patent/DE3371565D1/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G01R31/318547—Data generators or compressors
DE8383109950T 1982-11-08 1983-10-05 Self-testing method for logic circuitry Expired DE3371565D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/440,070 US4513418A (en) 1982-11-08 1982-11-08 Simultaneous self-testing system

Publications (1)

Publication Number Publication Date
DE3371565D1 true DE3371565D1 (en) 1987-06-19

Family

ID=23747301

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383109950T Expired DE3371565D1 (en) 1982-11-08 1983-10-05 Self-testing method for logic circuitry

Country Status (4)

Country Link
US (1) US4513418A (de)
EP (1) EP0108256B1 (de)
JP (1) JPS5988663A (de)
DE (1) DE3371565D1 (de)

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Also Published As

Publication number Publication date
US4513418A (en) 1985-04-23
JPS5988663A (ja) 1984-05-22
EP0108256A1 (de) 1984-05-16
EP0108256B1 (de) 1987-05-13
JPH0150873B2 (de) 1989-10-31

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