DE3373730D1 - Series-parallel/parallel-series device for variable bit length configuration - Google Patents

Series-parallel/parallel-series device for variable bit length configuration

Info

Publication number
DE3373730D1
DE3373730D1 DE8383430040T DE3373730T DE3373730D1 DE 3373730 D1 DE3373730 D1 DE 3373730D1 DE 8383430040 T DE8383430040 T DE 8383430040T DE 3373730 T DE3373730 T DE 3373730T DE 3373730 D1 DE3373730 D1 DE 3373730D1
Authority
DE
Germany
Prior art keywords
bits
parallel
register
series
latches
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8383430040T
Other languages
English (en)
Inventor
Guy Gaston Duforestel
Michel Andre Lechaczynski
Clement Yvon Poiraud
Paul Pierre Viallon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Compagnie IBM France SAS
International Business Machines Corp
Original Assignee
Compagnie IBM France SAS
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Compagnie IBM France SAS, International Business Machines Corp filed Critical Compagnie IBM France SAS
Application granted granted Critical
Publication of DE3373730D1 publication Critical patent/DE3373730D1/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31715—Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31919—Storing and outputting test patterns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa
DE8383430040T 1983-12-15 1983-12-15 Series-parallel/parallel-series device for variable bit length configuration Expired DE3373730D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP83430040A EP0151653B1 (de) 1983-12-15 1983-12-15 Vorrichtung zur Parallel-Serien/Serien-Parallelwandlung von aus variabler Länge bestehenden Bitkonfigurationen

Publications (1)

Publication Number Publication Date
DE3373730D1 true DE3373730D1 (en) 1987-10-22

Family

ID=8191508

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383430040T Expired DE3373730D1 (en) 1983-12-15 1983-12-15 Series-parallel/parallel-series device for variable bit length configuration

Country Status (4)

Country Link
US (1) US4680733A (de)
EP (1) EP0151653B1 (de)
JP (1) JPS60129847A (de)
DE (1) DE3373730D1 (de)

Families Citing this family (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5097442A (en) * 1985-06-20 1992-03-17 Texas Instruments Incorporated Programmable depth first-in, first-out memory
US5032783A (en) * 1985-10-23 1991-07-16 Texas Instruments Incorporated Test circuit and scan tested logic device with isolated data lines during testing
US4710927A (en) * 1986-07-24 1987-12-01 Integrated Device Technology, Inc. Diagnostic circuit
US4872169A (en) * 1987-03-06 1989-10-03 Texas Instruments Incorporated Hierarchical scan selection
JPS63256877A (ja) * 1987-04-14 1988-10-24 Mitsubishi Electric Corp テスト回路
US6085336A (en) * 1987-06-02 2000-07-04 Texas Instruments Incorporated Data processing devices, systems and methods with mode driven stops
US6522985B1 (en) 1989-07-31 2003-02-18 Texas Instruments Incorporated Emulation devices, systems and methods utilizing state machines
US5329471A (en) * 1987-06-02 1994-07-12 Texas Instruments Incorporated Emulation devices, systems and methods utilizing state machines
US5684721A (en) * 1987-09-04 1997-11-04 Texas Instruments Incorporated Electronic systems and emulation and testing devices, cables, systems and methods
US5535331A (en) * 1987-09-04 1996-07-09 Texas Instruments Incorporated Processor condition sensing circuits, systems and methods
JPH0782423B2 (ja) * 1987-09-16 1995-09-06 三洋電機株式会社 データ入出力回路
US4901076A (en) * 1987-10-29 1990-02-13 International Business Machines Corporation Circuit for converting between serial and parallel data streams by high speed addressing
JPH01132980A (ja) * 1987-11-17 1989-05-25 Mitsubishi Electric Corp テスト機能付電子回路装置
JPH01132979A (ja) * 1987-11-17 1989-05-25 Mitsubishi Electric Corp テスト機能付電子回路
US6304987B1 (en) * 1995-06-07 2001-10-16 Texas Instruments Incorporated Integrated test circuit
DE68921269T2 (de) * 1988-09-07 1995-06-22 Texas Instruments Inc Integrierte Prüfschaltung.
EP0358365B1 (de) * 1988-09-07 1998-10-21 Texas Instruments Incorporated Prüf-Puffer/Register
US5483518A (en) 1992-06-17 1996-01-09 Texas Instruments Incorporated Addressable shadow port and protocol for serial bus networks
US5138641A (en) * 1989-04-27 1992-08-11 Advanced Micro Devices, Inc. Bit residue correction in a dlc receiver
JP3005250B2 (ja) 1989-06-30 2000-01-31 テキサス インスツルメンツ インコーポレイテツド バスモニター集積回路
US5805792A (en) * 1989-07-31 1998-09-08 Texas Instruments Incorporated Emulation devices, systems, and methods
JPH03252569A (ja) * 1990-02-26 1991-11-11 Advanced Micro Devicds Inc スキャンパス用レジスタ回路
US6675333B1 (en) 1990-03-30 2004-01-06 Texas Instruments Incorporated Integrated circuit with serial I/O controller
JPH03296658A (ja) * 1990-04-16 1991-12-27 Tokimec Inc 超音波探触子
US5448525A (en) * 1994-03-10 1995-09-05 Intel Corporation Apparatus for configuring a subset of an integrated circuit having boundary scan circuitry connected in series and a method thereof
US5969538A (en) 1996-10-31 1999-10-19 Texas Instruments Incorporated Semiconductor wafer with interconnect between dies for testing and a process of testing
US5869979A (en) 1996-04-05 1999-02-09 Altera Corporation Technique for preconditioning I/Os during reconfiguration
US6408413B1 (en) 1998-02-18 2002-06-18 Texas Instruments Incorporated Hierarchical access of test access ports in embedded core integrated circuits
US6405335B1 (en) 1998-02-25 2002-06-11 Texas Instruments Incorporated Position independent testing of circuits
US7058862B2 (en) 2000-05-26 2006-06-06 Texas Instruments Incorporated Selecting different 1149.1 TAP domains from update-IR state
WO2000065753A2 (en) * 1999-04-23 2000-11-02 General Instrument Corporation Hfc return path system using digital conversion and transport
US6405150B1 (en) * 1999-08-31 2002-06-11 Unisys Corporation Program storage device containing instructions that are spaced apart by unused bits that end on word boundaries and which generate chip testing bit streams of any length
US6728915B2 (en) 2000-01-10 2004-04-27 Texas Instruments Incorporated IC with shared scan cells selectively connected in scan path
US6769080B2 (en) 2000-03-09 2004-07-27 Texas Instruments Incorporated Scan circuit low power adapter with counter
US7343535B2 (en) * 2002-02-06 2008-03-11 Avago Technologies General Ip Dte Ltd Embedded testing capability for integrated serializer/deserializers
US6953990B2 (en) * 2003-09-19 2005-10-11 Agilent Technologies, Inc. Wafer-level packaging of optoelectronic devices
US20050063648A1 (en) * 2003-09-19 2005-03-24 Wilson Robert Edward Alignment post for optical subassemblies made with cylindrical rods, tubes, spheres, or similar features
US6982437B2 (en) * 2003-09-19 2006-01-03 Agilent Technologies, Inc. Surface emitting laser package having integrated optical element and alignment post
US7520679B2 (en) * 2003-09-19 2009-04-21 Avago Technologies Fiber Ip (Singapore) Pte. Ltd. Optical device package with turning mirror and alignment post
US20050063431A1 (en) * 2003-09-19 2005-03-24 Gallup Kendra J. Integrated optics and electronics
US20050219083A1 (en) * 2004-03-16 2005-10-06 Boomer James B Architecture for bidirectional serializers and deserializer
US20050207280A1 (en) * 2004-03-16 2005-09-22 Fowler Michael L Bit clock with embedded word clock boundary
US20050213995A1 (en) * 2004-03-26 2005-09-29 Myunghee Lee Low power and low jitter optical receiver for fiber optic communication link
US7587537B1 (en) 2007-11-30 2009-09-08 Altera Corporation Serializer-deserializer circuits formed from input-output circuit registers
US7064690B2 (en) * 2004-04-15 2006-06-20 Fairchild Semiconductor Corporation Sending and/or receiving serial data with bit timing and parallel data conversion
US7328299B2 (en) * 2004-11-23 2008-02-05 Atmel Corporation Interface for compressed data transfer between host system and parallel data processing system
US7248122B2 (en) * 2005-09-14 2007-07-24 Fairchild Semiconductor Corporation Method and apparatus for generating a serial clock without a PLL
CN109977059B (zh) * 2019-03-28 2020-10-27 清华大学 一种用于串行接口的并行数据位宽变换电路

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3582902A (en) * 1968-12-30 1971-06-01 Honeywell Inc Data processing system having auxiliary register storage
JPS5137853B2 (de) * 1971-09-11 1976-10-18
US3972031A (en) * 1974-08-15 1976-07-27 Zonic Technical Laboratories, Inc. Variable length shift register alternately operable to store and recirculate data and addressing circuit therefor
GB1536147A (en) * 1975-07-02 1978-12-20 Int Computers Ltd Data processing systems
NL7512834A (nl) * 1975-11-03 1977-05-05 Philips Nv Geheugen met vluchtige informatie opslag en willekeurige toegankelijkheid.
JPS55141823A (en) * 1979-04-24 1980-11-06 Fujitsu Ltd Data read-out circuit
DE2839950B1 (de) * 1978-09-14 1979-10-25 Ibm Deutschland Einrichtung zur Feststellung der Laenge beliebiger Schieberegister
US4326290A (en) * 1979-10-16 1982-04-20 Burroughs Corporation Means and methods for monitoring the storage states of a memory and other storage devices in a digital data processor
US4312066A (en) * 1979-12-28 1982-01-19 International Business Machines Corporation Diagnostic/debug machine architecture
DE3029883A1 (de) * 1980-08-07 1982-03-11 Ibm Deutschland Gmbh, 7000 Stuttgart Schieberegister fuer pruef- und test-zwecke
DE3274910D1 (en) * 1982-09-28 1987-02-05 Ibm Device for loading and reading different chains of bistable circuits in a data processing system

Also Published As

Publication number Publication date
US4680733A (en) 1987-07-14
JPS60129847A (ja) 1985-07-11
EP0151653A1 (de) 1985-08-21
JPH0225208B2 (de) 1990-06-01
EP0151653B1 (de) 1987-09-16

Similar Documents

Publication Publication Date Title
DE3373730D1 (en) Series-parallel/parallel-series device for variable bit length configuration
US3665417A (en) Flexible computer accessed telemetry
KR870008454A (ko) 패킷발생용 장치
KR910008587A (ko) 데이타 항목 전송 방법 및 장치
GB1413340A (en) Data compression methods and apparatus
EP0286356A3 (de) Stapelspeicher mit unär codiertem Zeiger
NO941059L (no) Pakeanordning for kodeord med variabel lengde
CA2019821A1 (en) Signal conversion circuit
US4404677A (en) Detecting redundant digital codewords using a variable criterion
DE3878464D1 (de) Messverfahren und messeinrichtung zur stoerungsanalyse digitaler uebertragungswege.
US20010015923A1 (en) Data transfer technique
US5195055A (en) Serial data input circuit for the shifting-in of variable length data
EP0297581A3 (de) Pseudozufallsfolgegenerator
EP0158311A3 (de) Gerät zur Wiederauffindung von Zeichenketten
EP0460603A2 (de) Schaltkreis und Verfahren zur Festlegung von Verzögerungsdaten
JPS5696552A (en) Erastic storage
JPS6442770A (en) Language analyzing device
KR900005313A (ko) 16비트 데이타 버스에 바이트폭 uart 전송을 이행하는 방법 및 장치
JPS5799083A (en) Coding method
JPS5757080A (en) Picture processing device
KR920002745Y1 (ko) 고속 시프트 및 로테이트 시스템
JPS573471A (en) Decoder
JPS6466699A (en) Fast vector quantum differentiation method and apparatus
KR920000407Y1 (ko) Dat시스템에서의 샘플링 데이타 변환회로
JPH03108928A (ja) データリンク制御装置

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee