DE3373964D1 - Circuit for speeding up transfers of charges in programmable logic array structures - Google Patents

Circuit for speeding up transfers of charges in programmable logic array structures

Info

Publication number
DE3373964D1
DE3373964D1 DE8383105931T DE3373964T DE3373964D1 DE 3373964 D1 DE3373964 D1 DE 3373964D1 DE 8383105931 T DE8383105931 T DE 8383105931T DE 3373964 T DE3373964 T DE 3373964T DE 3373964 D1 DE3373964 D1 DE 3373964D1
Authority
DE
Germany
Prior art keywords
speeding
charges
transfers
circuit
programmable logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8383105931T
Other languages
English (en)
Inventor
Moises Cases
Wayne Richard Kraft
William Leonard Stahl
Nandor Gyorgy Thoma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3373964D1 publication Critical patent/DE3373964D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
    • H03K19/1772—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register with synchronous operation of at least one of the logical matrixes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
DE8383105931T 1982-08-30 1983-06-16 Circuit for speeding up transfers of charges in programmable logic array structures Expired DE3373964D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/413,043 US4500800A (en) 1982-08-30 1982-08-30 Logic performing cell for use in array structures

Publications (1)

Publication Number Publication Date
DE3373964D1 true DE3373964D1 (en) 1987-11-05

Family

ID=23635576

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383105931T Expired DE3373964D1 (en) 1982-08-30 1983-06-16 Circuit for speeding up transfers of charges in programmable logic array structures

Country Status (4)

Country Link
US (1) US4500800A (de)
EP (1) EP0105088B1 (de)
JP (1) JPS5945723A (de)
DE (1) DE3373964D1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5028817A (en) * 1990-06-14 1991-07-02 Zoran Corporation Tristable output buffer with state transition control
JP5269335B2 (ja) * 2007-03-30 2013-08-21 東京エレクトロン株式会社 プラズマ処理装置
US7932552B2 (en) * 2007-08-03 2011-04-26 International Business Machines Corporation Multiple source-single drain field effect semiconductor device and circuit
US20090033389A1 (en) * 2007-08-03 2009-02-05 Abadeer Wagdi W Micro-phase adjusting and micro-phase adjusting mixer circuits designed with standard field effect transistor structures
US7814449B2 (en) * 2007-10-17 2010-10-12 International Business Machines Corporation Design structure for multiple source-single drain field effect semiconductor device and circuit
US8661394B1 (en) 2008-09-24 2014-02-25 Iowa State University Research Foundation, Inc. Depth-optimal mapping of logic chains in reconfigurable fabrics
US8438522B1 (en) 2008-09-24 2013-05-07 Iowa State University Research Foundation, Inc. Logic element architecture for generic logic chains in programmable devices

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3761902A (en) * 1971-12-30 1973-09-25 Ibm Functional memory using multi-state associative cells
US4183093A (en) * 1975-09-04 1980-01-08 Hitachi, Ltd. Semiconductor integrated circuit device composed of insulated gate field-effect transistor
IT1075851B (it) * 1975-11-17 1985-04-22 Ibm Circuito perfezionato a trasferimento di carica
US4140921A (en) * 1977-08-31 1979-02-20 International Business Machines Corporation Generalized performance power optimized PLA circuits
US4123669A (en) * 1977-09-08 1978-10-31 International Business Machines Corporation Logical OR circuit for programmed logic arrays
JPS5493335A (en) * 1977-12-30 1979-07-24 Fujitsu Ltd Decoder circuit
US4295064A (en) * 1978-06-30 1981-10-13 International Business Machines Corporation Logic and array logic driving circuits
US4208728A (en) * 1978-12-21 1980-06-17 Bell Telephone Laboratories, Incorporated Programable logic array
JPS55163694A (en) * 1979-06-01 1980-12-19 Fujitsu Ltd Sample holding circuit
US4295065A (en) * 1979-08-13 1981-10-13 Rca Corporation Level shift circuit
US4395646A (en) * 1980-11-03 1983-07-26 International Business Machines Corp. Logic performing cell for use in array structures

Also Published As

Publication number Publication date
EP0105088A3 (en) 1985-03-13
EP0105088B1 (de) 1987-09-30
EP0105088A2 (de) 1984-04-11
JPS5945723A (ja) 1984-03-14
JPH027210B2 (de) 1990-02-16
US4500800A (en) 1985-02-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee