DE3377178D1 - A method of manufacturing a semiconductor device comprising an interconnection layer - Google Patents

A method of manufacturing a semiconductor device comprising an interconnection layer

Info

Publication number
DE3377178D1
DE3377178D1 DE8383301920T DE3377178T DE3377178D1 DE 3377178 D1 DE3377178 D1 DE 3377178D1 DE 8383301920 T DE8383301920 T DE 8383301920T DE 3377178 T DE3377178 T DE 3377178T DE 3377178 D1 DE3377178 D1 DE 3377178D1
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor device
interconnection layer
interconnection
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8383301920T
Other languages
English (en)
Inventor
Tadashi Shibata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3377178D1 publication Critical patent/DE3377178D1/de
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895Local interconnects; Local pads, as exemplified by patent document EP0896365
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53271Conductive materials containing semiconductor material, e.g. polysilicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/98Utilizing process equivalents or options
DE8383301920T 1982-04-08 1983-04-06 A method of manufacturing a semiconductor device comprising an interconnection layer Expired DE3377178D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57057240A JPS58175846A (ja) 1982-04-08 1982-04-08 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
DE3377178D1 true DE3377178D1 (en) 1988-07-28

Family

ID=13050004

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383301920T Expired DE3377178D1 (en) 1982-04-08 1983-04-06 A method of manufacturing a semiconductor device comprising an interconnection layer

Country Status (4)

Country Link
US (1) US4528744A (de)
EP (1) EP0091775B1 (de)
JP (1) JPS58175846A (de)
DE (1) DE3377178D1 (de)

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Publication number Priority date Publication date Assignee Title
JPH0618213B2 (ja) * 1982-06-25 1994-03-09 松下電子工業株式会社 半導体装置の製造方法
US4488348A (en) * 1983-06-15 1984-12-18 Hewlett-Packard Company Method for making a self-aligned vertically stacked gate MOS device
IT1213120B (it) * 1984-01-10 1989-12-14 Ates Componenti Elettron Processo per la fabbricazione di transistori mos complementari a basse tensioni di soglia in circuiti integrati ad alta densita' e struttura da esso risultante.
US4727038A (en) * 1984-08-22 1988-02-23 Mitsubishi Denki Kabushiki Kaisha Method of fabricating semiconductor device
GB2164491B (en) * 1984-09-14 1988-04-07 Stc Plc Semiconductor devices
US5190886A (en) * 1984-12-11 1993-03-02 Seiko Epson Corporation Semiconductor device and method of production
JPS61139058A (ja) * 1984-12-11 1986-06-26 Seiko Epson Corp 半導体製造装置
US4743564A (en) * 1984-12-28 1988-05-10 Kabushiki Kaisha Toshiba Method for manufacturing a complementary MOS type semiconductor device
US4635347A (en) * 1985-03-29 1987-01-13 Advanced Micro Devices, Inc. Method of fabricating titanium silicide gate electrodes and interconnections
DE3683679D1 (de) * 1985-04-26 1992-03-12 Fujitsu Ltd Verfahren zur herstellung einer kontaktanordnung fuer eine halbleiteranordnung.
JPS61263137A (ja) * 1985-05-07 1986-11-21 Hitachi Ltd 半導体装置
CA1235824A (en) * 1985-06-28 1988-04-26 Vu Q. Ho Vlsi mosfet circuits using refractory metal and/or refractory metal silicide
US4630357A (en) * 1985-08-02 1986-12-23 Ncr Corporation Method for forming improved contacts between interconnect layers of an integrated circuit
US4703551A (en) * 1986-01-24 1987-11-03 Ncr Corporation Process for forming LDD MOS/CMOS structures
US4753897A (en) * 1986-03-14 1988-06-28 Motorola Inc. Method for providing contact separation in silicided devices using false gate
US4908688A (en) * 1986-03-14 1990-03-13 Motorola, Inc. Means and method for providing contact separation in silicided devices
DE3767431D1 (de) * 1986-04-23 1991-02-21 American Telephone & Telegraph Verfahren zur herstellung von halbleiterbauelementen.
US4825271A (en) * 1986-05-20 1989-04-25 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory
JPS632535U (de) * 1986-06-20 1988-01-09
GB2199694A (en) * 1986-12-23 1988-07-13 Philips Electronic Associated A method of manufacturing a semiconductor device
US4735680A (en) * 1986-11-17 1988-04-05 Yen Yung Chau Method for the self-aligned silicide formation in IC fabrication
US4855247A (en) * 1988-01-19 1989-08-08 Standard Microsystems Corporation Process for fabricating self-aligned silicide lightly doped drain MOS devices
GB2214708A (en) * 1988-01-20 1989-09-06 Philips Nv A method of manufacturing a semiconductor device
US4902379A (en) * 1988-02-08 1990-02-20 Eastman Kodak Company UHV compatible lift-off method for patterning nobel metal silicide
JPH03141645A (ja) * 1989-07-10 1991-06-17 Texas Instr Inc <Ti> ポリサイドによる局所的相互接続方法とその方法により製造された半導体素子
US5041394A (en) * 1989-09-11 1991-08-20 Texas Instruments Incorporated Method for forming protective barrier on silicided regions
US4988643A (en) * 1989-10-10 1991-01-29 Vlsi Technology, Inc. Self-aligning metal interconnect fabrication
US5010030A (en) * 1989-10-30 1991-04-23 Motorola, Inc. Semiconductor process using selective deposition
US5070029A (en) * 1989-10-30 1991-12-03 Motorola, Inc. Semiconductor process using selective deposition
JP2757927B2 (ja) * 1990-06-28 1998-05-25 インターナショナル・ビジネス・マシーンズ・コーポレイション 半導体基板上の隔置されたシリコン領域の相互接続方法
JP2632620B2 (ja) * 1992-01-14 1997-07-23 大岡技研株式会社 歯車製品
US5306951A (en) * 1992-05-14 1994-04-26 Micron Technology, Inc. Sidewall silicidation for improved reliability and conductivity
US5529941A (en) * 1994-03-28 1996-06-25 Vlsi Technology, Inc. Method for making an integrated circuit structure
US5585299A (en) * 1996-03-19 1996-12-17 United Microelectronics Corporation Process for fabricating a semiconductor electrostatic discharge (ESD) protective device
JPH10112531A (ja) * 1996-08-13 1998-04-28 Hitachi Ltd 半導体集積回路装置の製造方法
US6335280B1 (en) * 1997-01-13 2002-01-01 Asm America, Inc. Tungsten silicide deposition process
TW396646B (en) * 1997-09-11 2000-07-01 Lg Semicon Co Ltd Manufacturing method of semiconductor devices
KR100344818B1 (ko) * 1997-09-24 2002-11-18 주식회사 하이닉스반도체 반도체소자및그의제조방법
US6208004B1 (en) * 1998-08-19 2001-03-27 Philips Semiconductor, Inc. Semiconductor device with high-temperature-stable gate electrode for sub-micron applications and fabrication thereof
US20050060933A1 (en) * 2003-08-22 2005-03-24 Henson David Lee Horticultural container lining for enhancing contained soil's water absorption
US7504329B2 (en) * 2005-05-11 2009-03-17 Interuniversitair Microelektronica Centrum (Imec) Method of forming a Yb-doped Ni full silicidation low work function gate electrode for n-MOSFET

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4102733A (en) * 1977-04-29 1978-07-25 International Business Machines Corporation Two and three mask process for IGFET fabrication
US4141022A (en) * 1977-09-12 1979-02-20 Signetics Corporation Refractory metal contacts for IGFETS
US4277881A (en) * 1978-05-26 1981-07-14 Rockwell International Corporation Process for fabrication of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines
JPS55134962A (en) * 1979-04-09 1980-10-21 Toshiba Corp Semiconductor device
DE2926874A1 (de) * 1979-07-03 1981-01-22 Siemens Ag Verfahren zum herstellen von niederohmigen, diffundierten bereichen bei der silizium-gate-technologie
US4305200A (en) * 1979-11-06 1981-12-15 Hewlett-Packard Company Method of forming self-registering source, drain, and gate contacts for FET transistor structures
JPS5748246A (en) * 1980-08-13 1982-03-19 Fujitsu Ltd Manufacture of semiconductor device
US4419809A (en) * 1981-12-30 1983-12-13 International Business Machines Corporation Fabrication process of sub-micrometer channel length MOSFETs

Also Published As

Publication number Publication date
JPS58175846A (ja) 1983-10-15
EP0091775B1 (de) 1988-06-22
US4528744A (en) 1985-07-16
JPH0343778B2 (de) 1991-07-03
EP0091775A2 (de) 1983-10-19
EP0091775A3 (en) 1985-07-03

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee