DE3379858D1 - Dynamic gate array whereby an assembly of gates is simulated by logic operations on variables selected according to the gates - Google Patents

Dynamic gate array whereby an assembly of gates is simulated by logic operations on variables selected according to the gates

Info

Publication number
DE3379858D1
DE3379858D1 DE8383107041T DE3379858T DE3379858D1 DE 3379858 D1 DE3379858 D1 DE 3379858D1 DE 8383107041 T DE8383107041 T DE 8383107041T DE 3379858 T DE3379858 T DE 3379858T DE 3379858 D1 DE3379858 D1 DE 3379858D1
Authority
DE
Germany
Prior art keywords
gates
simulated
assembly
selected according
gate array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8383107041T
Other languages
English (en)
Inventor
Kenji Ohmori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE3379858D1 publication Critical patent/DE3379858D1/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
DE8383107041T 1982-07-16 1983-07-18 Dynamic gate array whereby an assembly of gates is simulated by logic operations on variables selected according to the gates Expired DE3379858D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57123870A JPS5916050A (ja) 1982-07-16 1982-07-16 ダイナミツクゲ−トアレイ

Publications (1)

Publication Number Publication Date
DE3379858D1 true DE3379858D1 (en) 1989-06-15

Family

ID=14871412

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383107041T Expired DE3379858D1 (en) 1982-07-16 1983-07-18 Dynamic gate array whereby an assembly of gates is simulated by logic operations on variables selected according to the gates

Country Status (4)

Country Link
US (1) US4541071A (de)
EP (1) EP0099135B1 (de)
JP (1) JPS5916050A (de)
DE (1) DE3379858D1 (de)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4551815A (en) * 1983-12-12 1985-11-05 Aerojet-General Corporation Functionally redundant logic network architectures with logic selection means
JPS6142040A (ja) * 1984-08-03 1986-02-28 Nec Corp 論理シミユレ−タ
US4937770A (en) * 1986-02-07 1990-06-26 Teradyne, Inc. Simulation system
JPH07120359B2 (ja) * 1986-10-21 1995-12-20 日本電気株式会社 ハードウェアシミュレータにおけるシミュレーション方法
JPS63153672A (ja) * 1986-12-17 1988-06-27 Nec Corp ハ−ドウエアシミユレ−タ
US4956767A (en) * 1988-02-23 1990-09-11 Stellar Computer, Inc. Data processing system with model for status accumulating operation by simulating sequence of arithmetic steps performed by arithmetic processor
US5253363A (en) * 1988-03-15 1993-10-12 Edward Hyman Method and apparatus for compiling and implementing state-machine states and outputs for a universal cellular sequential local array
US5377123A (en) * 1992-06-08 1994-12-27 Hyman; Edward Programmable logic device
US5452231A (en) * 1988-10-05 1995-09-19 Quickturn Design Systems, Inc. Hierarchically connected reconfigurable logic assembly
US5329470A (en) * 1988-12-02 1994-07-12 Quickturn Systems, Inc. Reconfigurable hardware emulation system
US5109353A (en) 1988-12-02 1992-04-28 Quickturn Systems, Incorporated Apparatus for emulation of electronic hardware system
US5572708A (en) * 1989-02-28 1996-11-05 Nec Corporation Hardware simulator capable of dealing with a description of a functional level
US5369593A (en) * 1989-05-31 1994-11-29 Synopsys Inc. System for and method of connecting a hardware modeling element to a hardware modeling system
US5353243A (en) * 1989-05-31 1994-10-04 Synopsys Inc. Hardware modeling system and method of use
US5446742A (en) * 1990-08-01 1995-08-29 Zilog, Inc. Techniques for developing integrated circuit test programs and their use in testing actual circuits
US5680583A (en) * 1994-02-16 1997-10-21 Arkos Design, Inc. Method and apparatus for a trace buffer in an emulation system
GB9403030D0 (en) * 1994-02-17 1994-04-06 Austin Kenneth Re-configurable application specific device
GB9413127D0 (en) * 1994-06-30 1994-08-24 Philips Electronics Uk Ltd Data processing apparatus
US5777489A (en) * 1995-10-13 1998-07-07 Mentor Graphics Corporation Field programmable gate array with integrated debugging facilities
US5841967A (en) * 1996-10-17 1998-11-24 Quickturn Design Systems, Inc. Method and apparatus for design verification using emulation and simulation
US6026230A (en) * 1997-05-02 2000-02-15 Axis Systems, Inc. Memory simulation system and method
US6421251B1 (en) 1997-05-02 2002-07-16 Axis Systems Inc Array board interconnect system and method
US6321366B1 (en) 1997-05-02 2001-11-20 Axis Systems, Inc. Timing-insensitive glitch-free logic system and method
US6389379B1 (en) 1997-05-02 2002-05-14 Axis Systems, Inc. Converification system and method
US6134516A (en) * 1997-05-02 2000-10-17 Axis Systems, Inc. Simulation server system and method
US5960191A (en) * 1997-05-30 1999-09-28 Quickturn Design Systems, Inc. Emulation system with time-multiplexed interconnect
US5970240A (en) * 1997-06-25 1999-10-19 Quickturn Design Systems, Inc. Method and apparatus for configurable memory emulation
US6034538A (en) * 1998-01-21 2000-03-07 Lucent Technologies Inc. Virtual logic system for reconfigurable hardware
US6292916B1 (en) 1998-12-10 2001-09-18 Lucent Technologies Inc. Parallel backtracing for satisfiability on reconfigurable hardware
US6442732B1 (en) 1999-04-21 2002-08-27 Lucent Technologies, Inc. Virtual logic system for solving satisfiability problems using reconfigurable hardware
WO2023220537A1 (en) * 2022-05-11 2023-11-16 Juan Pablo Ramirez Simple and linear fast adder

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1475932A (fr) * 1966-02-24 1967-04-07 Telefunken Patent Réseau logique
US3983541A (en) * 1969-05-19 1976-09-28 Burroughs Corporation Polymorphic programmable units employing plural levels of phased sub-instruction sets
US3700868A (en) * 1970-12-16 1972-10-24 Nasa Logical function generator
US4011547A (en) * 1972-07-17 1977-03-08 International Business Machines Corporation Data processor for pattern recognition and the like
US4001787A (en) * 1972-07-17 1977-01-04 International Business Machines Corporation Data processor for pattern recognition and the like
JPS5434581B2 (de) * 1974-07-12 1979-10-27
JPS55131850A (en) * 1979-04-03 1980-10-14 Nec Corp Microprogram controller
US4472780A (en) * 1981-09-28 1984-09-18 The Boeing Company Fly-by-wire lateral control system

Also Published As

Publication number Publication date
JPH0230056B2 (de) 1990-07-04
US4541071A (en) 1985-09-10
EP0099135A2 (de) 1984-01-25
JPS5916050A (ja) 1984-01-27
EP0099135B1 (de) 1989-05-10
EP0099135A3 (en) 1985-10-23

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition