DE3381605D1 - Verfahren zum herstellen von emitter- und intrinsic-basisgebieten eines bipolaren transistors. - Google Patents
Verfahren zum herstellen von emitter- und intrinsic-basisgebieten eines bipolaren transistors.Info
- Publication number
- DE3381605D1 DE3381605D1 DE8383101761T DE3381605T DE3381605D1 DE 3381605 D1 DE3381605 D1 DE 3381605D1 DE 8383101761 T DE8383101761 T DE 8383101761T DE 3381605 T DE3381605 T DE 3381605T DE 3381605 D1 DE3381605 D1 DE 3381605D1
- Authority
- DE
- Germany
- Prior art keywords
- bipolar transistor
- intrinsic base
- base areas
- producing emitter
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66272—Silicon vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3215—Doping the layers
- H01L21/32155—Doping polycristalline - or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1004—Base region of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66272—Silicon vertical transistors
- H01L29/66287—Silicon vertical transistors with a single crystalline emitter, collector or base including extrinsic, link or graft base formed on the silicon substrate, e.g. by epitaxy, recrystallisation, after insulating device isolation
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/355,633 US4431460A (en) | 1982-03-08 | 1982-03-08 | Method of producing shallow, narrow base bipolar transistor structures via dual implantations of selected polycrystalline layer |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3381605D1 true DE3381605D1 (de) | 1990-06-28 |
Family
ID=23398190
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8383101761T Expired - Fee Related DE3381605D1 (de) | 1982-03-08 | 1983-02-23 | Verfahren zum herstellen von emitter- und intrinsic-basisgebieten eines bipolaren transistors. |
Country Status (4)
Country | Link |
---|---|
US (1) | US4431460A (de) |
EP (1) | EP0090940B1 (de) |
JP (1) | JPS58154267A (de) |
DE (1) | DE3381605D1 (de) |
Families Citing this family (45)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4467519A (en) * | 1982-04-01 | 1984-08-28 | International Business Machines Corporation | Process for fabricating polycrystalline silicon film resistors |
JPS58202525A (ja) * | 1982-05-21 | 1983-11-25 | Toshiba Corp | 半導体装置の製造方法 |
US4575923A (en) * | 1983-04-06 | 1986-03-18 | North American Philips Corporation | Method of manufacturing a high resistance layer having a low temperature coefficient of resistance and semiconductor device having such high resistance layer |
US4510676A (en) * | 1983-12-06 | 1985-04-16 | International Business Machines, Corporation | Method of fabricating a lateral PNP transistor |
US4569701A (en) * | 1984-04-05 | 1986-02-11 | At&T Bell Laboratories | Technique for doping from a polysilicon transfer layer |
US4549914A (en) * | 1984-04-09 | 1985-10-29 | At&T Bell Laboratories | Integrated circuit contact technique |
US4640721A (en) * | 1984-06-06 | 1987-02-03 | Hitachi, Ltd. | Method of forming bipolar transistors with graft base regions |
JPH0658912B2 (ja) * | 1985-05-07 | 1994-08-03 | 日本電信電話株式会社 | バイポーラトランジスタの製造方法 |
US4795679A (en) * | 1985-05-22 | 1989-01-03 | North American Philips Corporation | Monocrystalline silicon layers on substrates |
JPH07101677B2 (ja) * | 1985-12-02 | 1995-11-01 | 株式会社東芝 | 半導体装置の製造方法 |
US4682407A (en) * | 1986-01-21 | 1987-07-28 | Motorola, Inc. | Means and method for stabilizing polycrystalline semiconductor layers |
US4799099A (en) * | 1986-01-30 | 1989-01-17 | Texas Instruments Incorporated | Bipolar transistor in isolation well with angled corners |
US5104816A (en) * | 1986-01-30 | 1992-04-14 | Texas Instruments Incorporated | Polysilicon self-aligned bipolar device including trench isolation and process of manufacturing same |
JP2557840B2 (ja) * | 1986-03-13 | 1996-11-27 | 富士通株式会社 | 半導体装置の製造法 |
JPS62224968A (ja) * | 1986-03-27 | 1987-10-02 | Matsushita Electronics Corp | 半導体装置の製造方法 |
US4839302A (en) * | 1986-10-13 | 1989-06-13 | Matsushita Electric Industrial Co., Ltd. | Method for fabricating bipolar semiconductor device |
JPS63107167A (ja) * | 1986-10-24 | 1988-05-12 | Oki Electric Ind Co Ltd | 半導体集積回路装置の製造方法 |
JPS63182860A (ja) * | 1987-01-26 | 1988-07-28 | Toshiba Corp | 半導体装置とその製造方法 |
JPS63184364A (ja) * | 1987-01-27 | 1988-07-29 | Toshiba Corp | 半導体装置の製造方法 |
US4902640A (en) * | 1987-04-17 | 1990-02-20 | Tektronix, Inc. | High speed double polycide bipolar/CMOS integrated circuit process |
US4933295A (en) * | 1987-05-08 | 1990-06-12 | Raytheon Company | Method of forming a bipolar transistor having closely spaced device regions |
JPH0783025B2 (ja) * | 1987-05-21 | 1995-09-06 | 松下電器産業株式会社 | 半導体装置およびその製造方法 |
US4871684A (en) * | 1987-10-29 | 1989-10-03 | International Business Machines Corporation | Self-aligned polysilicon emitter and contact structure for high performance bipolar transistors |
US5093711A (en) * | 1988-10-14 | 1992-03-03 | Seiko Epson Corporation | Semiconductor device |
EP0383712A3 (de) * | 1989-02-13 | 1991-10-30 | International Business Machines Corporation | Verfahren zum Herstellen von Hochleistungstransistoren mit Polysilizium-Kontakten |
EP0395358B1 (de) * | 1989-04-25 | 2001-03-14 | Matsushita Electronics Corporation | Verfahren zur Herstellung eines bipolaren Transistors |
US4927773A (en) * | 1989-06-05 | 1990-05-22 | Santa Barbara Research Center | Method of minimizing implant-related damage to a group II-VI semiconductor material |
US5028973A (en) * | 1989-06-19 | 1991-07-02 | Harris Corporation | Bipolar transistor with high efficient emitter |
US5017990A (en) * | 1989-12-01 | 1991-05-21 | International Business Machines Corporation | Raised base bipolar transistor structure and its method of fabrication |
US5296388A (en) * | 1990-07-13 | 1994-03-22 | Matsushita Electric Industrial Co., Ltd. | Fabrication method for semiconductor devices |
US5385850A (en) * | 1991-02-07 | 1995-01-31 | International Business Machines Corporation | Method of forming a doped region in a semiconductor substrate utilizing a sacrificial epitaxial silicon layer |
US5138256A (en) * | 1991-04-23 | 1992-08-11 | International Business Machines Corp. | Method and apparatus for determining the thickness of an interfacial polysilicon/silicon oxide film |
GB2255226B (en) * | 1991-04-23 | 1995-03-01 | Intel Corp | Bicmos process for counter doped collector |
US5629547A (en) * | 1991-04-23 | 1997-05-13 | Intel Corporation | BICMOS process for counter doped collector |
US5695819A (en) * | 1991-08-09 | 1997-12-09 | Applied Materials, Inc. | Method of enhancing step coverage of polysilicon deposits |
US5229322A (en) * | 1991-12-05 | 1993-07-20 | International Business Machines Corporation | Method of making low resistance substrate or buried layer contact |
EP0622832B1 (de) * | 1993-03-17 | 2000-05-31 | Canon Kabushiki Kaisha | Verbindungsverfahren einer Verdrahtung mit einem Halbleitergebiet und durch dieses Verfahren hergestellte Halbleitervorrichtung |
US5520785A (en) * | 1994-01-04 | 1996-05-28 | Motorola, Inc. | Method for enhancing aluminum nitride |
JP2865045B2 (ja) * | 1996-02-28 | 1999-03-08 | 日本電気株式会社 | 半導体装置の製造方法 |
DE19815869C1 (de) * | 1998-04-08 | 1999-06-02 | Siemens Ag | Verfahren zum Herstellen eines Stapelkondensators in einer Halbleiteranordnung |
US9997619B1 (en) | 2017-05-24 | 2018-06-12 | International Business Machines Corporation | Bipolar junction transistors and methods forming same |
RU2659328C1 (ru) * | 2017-10-02 | 2018-06-29 | Федеральное государственное бюджетное образовательное учреждение высшего образования "Чеченский государственный университет" | Способ изготовления полупроводникового прибора |
US11355585B2 (en) | 2019-10-01 | 2022-06-07 | Analog Devices International Unlimited Company | Bipolar junction transistor, and a method of forming a charge control structure for a bipolar junction transistor |
US11404540B2 (en) | 2019-10-01 | 2022-08-02 | Analog Devices International Unlimited Company | Bipolar junction transistor, and a method of forming a collector for a bipolar junction transistor |
US11563084B2 (en) | 2019-10-01 | 2023-01-24 | Analog Devices International Unlimited Company | Bipolar junction transistor, and a method of forming an emitter for a bipolar junction transistor |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3460007A (en) * | 1967-07-03 | 1969-08-05 | Rca Corp | Semiconductor junction device |
JPS51146174A (en) * | 1975-06-11 | 1976-12-15 | Mitsubishi Electric Corp | Diode device fabrication method |
JPS5914898B2 (ja) * | 1975-08-29 | 1984-04-06 | 三菱電機株式会社 | 半導体装置の製造方法 |
JPS5950113B2 (ja) * | 1975-11-05 | 1984-12-06 | 株式会社東芝 | 半導体装置 |
JPS543479A (en) * | 1977-06-09 | 1979-01-11 | Toshiba Corp | Semiconductor device and its manufacture |
US4190466A (en) * | 1977-12-22 | 1980-02-26 | International Business Machines Corporation | Method for making a bipolar transistor structure utilizing self-passivating diffusion sources |
JPS5939906B2 (ja) * | 1978-05-04 | 1984-09-27 | 超エル・エス・アイ技術研究組合 | 半導体装置の製造方法 |
US4157269A (en) * | 1978-06-06 | 1979-06-05 | International Business Machines Corporation | Utilizing polysilicon diffusion sources and special masking techniques |
JPS5586151A (en) * | 1978-12-23 | 1980-06-28 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Manufacture of semiconductor integrated circuit |
US4357622A (en) * | 1980-01-18 | 1982-11-02 | International Business Machines Corporation | Complementary transistor structure |
US4259680A (en) * | 1980-04-17 | 1981-03-31 | Bell Telephone Laboratories, Incorporated | High speed lateral bipolar transistor |
-
1982
- 1982-03-08 US US06/355,633 patent/US4431460A/en not_active Expired - Lifetime
-
1983
- 1983-01-14 JP JP58003621A patent/JPS58154267A/ja active Granted
- 1983-02-23 EP EP83101761A patent/EP0090940B1/de not_active Expired
- 1983-02-23 DE DE8383101761T patent/DE3381605D1/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0090940B1 (de) | 1990-05-23 |
JPH0376575B2 (de) | 1991-12-05 |
JPS58154267A (ja) | 1983-09-13 |
EP0090940A3 (en) | 1986-10-01 |
EP0090940A2 (de) | 1983-10-12 |
US4431460A (en) | 1984-02-14 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |