DE3485487D1 - Steuerungssystem fuer pufferspeicher. - Google Patents

Steuerungssystem fuer pufferspeicher.

Info

Publication number: DE3485487D1
Authority: DE; Germany
Prior art keywords: control system; buffer storage; buffer; storage; control
Prior art date: 1983-05-16
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Fee Related

Application number

DE8484303047T

Other languages

English (en)

Inventor

Hirosada Tone

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Fujitsu Ltd

Original Assignee

Fujitsu Ltd

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1983-05-16

Filing date

1984-05-04

Publication date

1992-03-12

1984-05-04 Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd

1992-03-12 Application granted granted Critical

1992-03-12 Publication of DE3485487D1 publication Critical patent/DE3485487D1/de

2004-05-05 Anticipated expiration legal-status Critical

Status Expired - Fee Related legal-status Critical Current

Links

Classifications

- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing

DE8484303047T 1983-05-16 1984-05-04 Steuerungssystem fuer pufferspeicher. Expired - Fee Related DE3485487D1 (de)

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
JP58085351A JPS59213084A (ja)	1983-05-16	1983-05-16	バッファ記憶装置のアクセス制御方式

Publications (1)

Publication Number	Publication Date
DE3485487D1 true DE3485487D1 (de)	1992-03-12

Family

ID=13856259

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
DE8484303047T Expired - Fee Related DE3485487D1 (de)	1983-05-16	1984-05-04	Steuerungssystem fuer pufferspeicher.

Country Status (9)

Country	Link
US (1)	US5097414A (de)
EP (1)	EP0125855B1 (de)
JP (1)	JPS59213084A (de)
KR (1)	KR890003688B1 (de)
AU (1)	AU551435B2 (de)
BR (1)	BR8402299A (de)
CA (1)	CA1218753A (de)
DE (1)	DE3485487D1 (de)
ES (1)	ES532492A0 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
DE3687739T2 (de) *	1985-12-02	1993-08-19	Ibm	Speicheranordnung mit mehrfachem lese-schreibzugriff.
JPS63257853A (ja) *	1987-04-03	1988-10-25	インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン	キヤツシユ・メモリ・システム
JPH0727492B2 (ja) *	1988-01-21	1995-03-29	三菱電機株式会社	緩衝記憶装置
US5247649A (en) *	1988-05-06	1993-09-21	Hitachi, Ltd.	Multi-processor system having a multi-port cache memory
JPH01280860A (ja) *	1988-05-06	1989-11-13	Hitachi Ltd	マルチポートキヤツシユメモリを有するマルチプロセツサシステム
US5214777A (en) *	1989-03-27	1993-05-25	Ncr Corporation	High speed read/modify/write memory system and method
JPH077356B2 (ja) *	1989-05-19	1995-01-30	株式会社東芝	パイプライン方式のマイクロプロセッサ
JPH0740247B2 (ja) *	1989-06-20	1995-05-01	松下電器産業株式会社	キャッシュメモリ装置
US5442769A (en) *	1990-03-13	1995-08-15	At&T Corp.	Processor having general registers with subdivisions addressable in instructions by register number and subdivision type
JP2636485B2 (ja) *	1990-09-21	1997-07-30	日本電気株式会社	キャッシュ記憶装置
JPH04145552A (ja) *	1990-10-05	1992-05-19	Nec Corp	キャッシュ記憶装置
JPH04199243A (ja) *	1990-11-26	1992-07-20	Nec Corp	キャッシュ記憶装置
JPH04199242A (ja) *	1990-11-26	1992-07-20	Nec Corp	キャッシュ記憶装置
US5510973A (en) *	1991-08-15	1996-04-23	Fujitsu Limited	Buffer storage control system
JPH05143449A (ja) *	1991-11-22	1993-06-11	Fujitsu Ltd	主記憶データ書込制御方法
JP2868141B2 (ja) *	1992-03-16	1999-03-10	株式会社日立製作所	ディスクアレイ装置
US5678040A (en) *	1993-10-29	1997-10-14	Motorola, Inc.	Method for managing a hierarchical design transaction
US5860149A (en) *	1995-06-07	1999-01-12	Emulex Corporation	Memory buffer system using a single pointer to reference multiple associated data
US5915265A (en) *	1995-12-22	1999-06-22	Intel Corporation	Method and apparatus for dynamically allocating and resizing the dedicated memory in a shared memory buffer architecture system
JPH09237162A (ja) *	1996-02-23	1997-09-09	Hewlett Packard Co <Hp>	走査型データ記憶システム、及びその針摩耗管理方法、媒体摩耗管理方法、並びに残存寿命表示装置
US5924115A (en) *	1996-03-29	1999-07-13	Interval Research Corporation	Hierarchical memory architecture for a programmable integrated circuit having an interconnect structure connected in a tree configuration
US6029237A (en) *	1997-10-08	2000-02-22	Dell Usa, L.P.	Method for simulating the presence of a diskette drive in a NetPC computer that contains only a hard disk drive
JP2014006807A (ja) *	2012-06-26	2014-01-16	Fujitsu Ltd	演算処理装置、キャッシュメモリ制御装置及びキャッシュメモリの制御方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4208716A (en) *	1978-12-11	1980-06-17	Honeywell Information Systems Inc.	Cache arrangement for performing simultaneous read/write operations
US4293910A (en) *	1979-07-02	1981-10-06	International Business Machines Corporation	Reconfigurable key-in-storage means for protecting interleaved main storage
JPS5619575A (en) *	1979-07-25	1981-02-24	Fujitsu Ltd	Data processing system having hierarchy memory
JPS5694567A (en) *	1979-12-28	1981-07-31	Fujitsu Ltd	Busy control system for buffer memory
US4407015A (en) *	1980-11-26	1983-09-27	Burroughs Corporation	Multiple event driven micro-sequencer
US4439829A (en) *	1981-01-07	1984-03-27	Wang Laboratories, Inc.	Data processing machine with improved cache memory management
CA1187198A (en) *	1981-06-15	1985-05-14	Takashi Chiba	System for controlling access to channel buffers
US4493026A (en) *	1982-05-26	1985-01-08	International Business Machines Corporation	Set associative sector cache

1983
- 1983-05-16 JP JP58085351A patent/JPS59213084A/ja active Granted
1984
- 1984-05-04 EP EP19840303047 patent/EP0125855B1/de not_active Expired - Lifetime
- 1984-05-04 CA CA000453619A patent/CA1218753A/en not_active Expired
- 1984-05-04 DE DE8484303047T patent/DE3485487D1/de not_active Expired - Fee Related
- 1984-05-09 KR KR8402493A patent/KR890003688B1/ko not_active IP Right Cessation
- 1984-05-10 AU AU27887/84A patent/AU551435B2/en not_active Ceased
- 1984-05-14 ES ES532492A patent/ES532492A0/es active Granted
- 1984-05-15 BR BR8402299A patent/BR8402299A/pt not_active IP Right Cessation
1989
- 1989-10-17 US US07/423,588 patent/US5097414A/en not_active Expired - Fee Related

Also Published As

Publication number	Publication date
KR890003688B1 (en)	1989-09-30
CA1218753A (en)	1987-03-03
JPS59213084A (ja)	1984-12-01
AU2788784A (en)	1984-11-22
EP0125855A3 (en)	1988-05-25
AU551435B2 (en)	1986-05-01
ES8503868A1 (es)	1985-03-01
KR840008849A (ko)	1984-12-19
EP0125855B1 (de)	1992-01-29
ES532492A0 (es)	1985-03-01
JPS6215896B2 (de)	1987-04-09
BR8402299A (pt)	1984-12-26
US5097414A (en)	1992-03-17
EP0125855A2 (de)	1984-11-21

Legal Events

Date	Code	Title	Description
1993-03-04	8364	No opposition during term of opposition
2002-07-18	8339	Ceased/non-payment of the annual fee

Publication	Publication Date	Title
DE3485487D1 (de)	1992-03-12	Steuerungssystem fuer pufferspeicher.
DE3484992D1 (de)	1991-10-10	Puffersteuersystem.
DE3381857D1 (de)	1990-10-11	Speichersystem.
DE3382111D1 (de)	1991-02-21	Cache-speichersystem.
NO166019C (no)	1991-05-15	Hukommelses-system.
DE3483662D1 (de)	1991-01-10	Antiblockierregelsystem.
DE3586563T2 (de)	1993-02-25	Regelsystem fuer beschleunigung-verlangsamung.
DE3481093D1 (de)	1990-02-22	Verteiltes bussteuerungssystem.
DE3485562D1 (de)	1992-04-16	Speicher-subsystem.
DE3484419D1 (de)	1991-05-16	Fifo-speichersystem.
DE3482512D1 (de)	1990-07-19	Steuermechanismus fuer mehrprozessorsystem.
DE3481298D1 (de)	1990-03-15	Antiblockierregelsystem.
DE3780673D1 (de)	1992-09-03	Kontrollsystem fuer flockungsmittelzugabe.
DE3478881D1 (en)	1989-08-10	Buffer storage system
DE3484147D1 (de)	1991-04-04	Rechnersystem.
DE3482895D1 (de)	1990-09-13	Automatisches lesesystem fuer peripherie-steuerungsgeraet.
DE3874481T2 (de)	1993-01-28	Kontrolleinrichtung fuer pufferspeicher.
DE3484536D1 (de)	1991-06-06	Anzeigesteuersystem.
DE3381476D1 (de)	1990-05-23	Pufferspeichersteuerungsanordnung.
EP0145594A3 (en)	1988-07-27	Buffer storage control system
DE3481788D1 (de)	1990-05-03	Addier/substrahiersystem fuer gleitkommazahlen.
DE3583737D1 (de)	1991-09-12	Kontrollsystem fuer aufgezeichnete informationen.
FI843713L (fi)	1985-03-23	Meddelandeorienterad avbrytningsmekanism foer multiprocessor system.
DK129884A (da)	1984-03-27	Datastyresystem
NO151754C (no)	1985-05-29	Systemforskaling.