DE3486161D1 - Datenverarbeitungssystem mit datenkohaerenz. - Google Patents

Datenverarbeitungssystem mit datenkohaerenz.

Info

Publication number
DE3486161D1
DE3486161D1 DE8484309014T DE3486161T DE3486161D1 DE 3486161 D1 DE3486161 D1 DE 3486161D1 DE 8484309014 T DE8484309014 T DE 8484309014T DE 3486161 T DE3486161 T DE 3486161T DE 3486161 D1 DE3486161 D1 DE 3486161D1
Authority
DE
Germany
Prior art keywords
data
processing system
coherence
data processing
data coherence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Revoked
Application number
DE8484309014T
Other languages
English (en)
Other versions
DE3486161T2 (de
Inventor
Steven J Frank
J Scott Merritt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Recognition International Inc
Original Assignee
Recognition International Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=24266291&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE3486161(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Recognition International Inc filed Critical Recognition International Inc
Publication of DE3486161D1 publication Critical patent/DE3486161D1/de
Application granted granted Critical
Publication of DE3486161T2 publication Critical patent/DE3486161T2/de
Anticipated expiration legal-status Critical
Revoked legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S707/00—Data processing: database and file management or data structures
    • Y10S707/99951—File or database maintenance
    • Y10S707/99952—Coherency, e.g. same view to multiple users
DE84309014T 1983-12-30 1984-12-21 Datenverarbeitungssystem mit Datenkohärenz. Revoked DE3486161T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06567233 US4622631B1 (en) 1983-12-30 1983-12-30 Data processing system having a data coherence solution

Publications (2)

Publication Number Publication Date
DE3486161D1 true DE3486161D1 (de) 1993-07-15
DE3486161T2 DE3486161T2 (de) 1993-09-30

Family

ID=24266291

Family Applications (1)

Application Number Title Priority Date Filing Date
DE84309014T Revoked DE3486161T2 (de) 1983-12-30 1984-12-21 Datenverarbeitungssystem mit Datenkohärenz.

Country Status (4)

Country Link
US (1) US4622631B1 (de)
EP (1) EP0149355B1 (de)
JP (1) JPH0658660B2 (de)
DE (1) DE3486161T2 (de)

Families Citing this family (186)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60143718A (ja) * 1983-12-30 1985-07-30 Dainippon Screen Mfg Co Ltd 工程看視方法
US4847804A (en) * 1985-02-05 1989-07-11 Digital Equipment Corporation Apparatus and method for data copy consistency in a multi-cache data processing unit
US4941088A (en) * 1985-02-05 1990-07-10 Digital Equipment Corporation Split bus multiprocessing system with data transfer between main memory and caches using interleaving of sub-operations on sub-busses
ATE80480T1 (de) * 1985-02-05 1992-09-15 Digital Equipment Corp Vorrichtung und verfahren zur zugriffsteuerung in einer mehrcachespeicherdatenverarbeitungsanordnung.
US4775955A (en) * 1985-10-30 1988-10-04 International Business Machines Corporation Cache coherence mechanism based on locking
US4763244A (en) * 1986-01-15 1988-08-09 Motorola, Inc. Paged memory management unit capable of selectively supporting multiple address spaces
US4785395A (en) * 1986-06-27 1988-11-15 Honeywell Bull Inc. Multiprocessor coherent cache system including two level shared cache with separately allocated processor storage locations and inter-level duplicate entry replacement
US4885680A (en) * 1986-07-25 1989-12-05 International Business Machines Corporation Method and apparatus for efficiently handling temporarily cacheable data
US4853846A (en) * 1986-07-29 1989-08-01 Intel Corporation Bus expander with logic for virtualizing single cache control into dual channels with separate directories and prefetch for different processors
CH670715A5 (de) * 1986-10-03 1989-06-30 Bbc Brown Boveri & Cie
CH672816A5 (de) * 1986-10-03 1989-12-29 Pantex Stahl Ag
US4843542A (en) * 1986-11-12 1989-06-27 Xerox Corporation Virtual memory cache for use in multi-processing systems
US5045996A (en) * 1986-11-12 1991-09-03 Xerox Corporation Multiprocessor cache memory housekeeping
GB2200483B (en) * 1987-01-22 1991-10-16 Nat Semiconductor Corp Memory referencing in a high performance microprocessor
AU598101B2 (en) * 1987-02-27 1990-06-14 Honeywell Bull Inc. Shared memory controller arrangement
JPH0221342A (ja) * 1987-02-27 1990-01-24 Hitachi Ltd マルチプロセッサシステム及びマルチプロセッサシステムにおける論理キャッシュメモリのアクセス方法
US4827406A (en) * 1987-04-01 1989-05-02 International Business Machines Corporation Memory allocation for multiple processors
US4829422A (en) * 1987-04-02 1989-05-09 Stellar Computer, Inc. Control of multiple processors executing in parallel regions
US4954944A (en) * 1987-04-23 1990-09-04 Nec Corporation Cache control circuit in cache memory unit with unit for enabling to reduce a read access time for cache memory
US5201040A (en) * 1987-06-22 1993-04-06 Hitachi, Ltd. Multiprocessor system having subsystems which are loosely coupled through a random access storage and which each include a tightly coupled multiprocessor
JPH0831061B2 (ja) * 1987-07-24 1996-03-27 株式会社日立製作所 バツフア制御方式
EP0312764A3 (de) * 1987-10-19 1991-04-10 International Business Machines Corporation Datenprozessor mit mehrfachen Ausführungseinheiten zur parallelen Ausführung von mehreren Befehlsklassen
US5251308A (en) * 1987-12-22 1993-10-05 Kendall Square Research Corporation Shared memory multiprocessor with data hiding and post-store
US5055999A (en) 1987-12-22 1991-10-08 Kendall Square Research Corporation Multiprocessor digital data processing system
US5335325A (en) * 1987-12-22 1994-08-02 Kendall Square Research Corporation High-speed packet switching apparatus and method
US5761413A (en) * 1987-12-22 1998-06-02 Sun Microsystems, Inc. Fault containment system for multiprocessor with shared memory
US5282201A (en) * 1987-12-22 1994-01-25 Kendall Square Research Corporation Dynamic packet routing network
US5226039A (en) * 1987-12-22 1993-07-06 Kendall Square Research Corporation Packet routing switch
US5341483A (en) * 1987-12-22 1994-08-23 Kendall Square Research Corporation Dynamic hierarchial associative memory
CA1320003C (en) * 1987-12-22 1993-07-06 Steven J. Frank Interconnection system for multiprocessor structure
US5822578A (en) * 1987-12-22 1998-10-13 Sun Microsystems, Inc. System for inserting instructions into processor instruction stream in order to perform interrupt processing
ATE109910T1 (de) * 1988-01-20 1994-08-15 Advanced Micro Devices Inc Organisation eines integrierten cachespeichers zur flexiblen anwendung zur unterstützung von multiprozessor-operationen.
US4977498A (en) * 1988-04-01 1990-12-11 Digital Equipment Corporation Data processing system having a data memory interlock coherency scheme
EP0343567A3 (de) * 1988-05-25 1991-01-09 Hitachi, Ltd. Mehrprozessoranordnung und Cache-Speichervorrichtung zur Verwendung in dieser Anordnung
JPH01302444A (ja) * 1988-05-31 1989-12-06 Toshiba Corp 論理アドレスキャッシュ制御方式
DE68924306T2 (de) * 1988-06-27 1996-05-09 Digital Equipment Corp Mehrprozessorrechneranordnungen mit gemeinsamem Speicher und privaten Cache-Speichern.
US5317716A (en) * 1988-08-16 1994-05-31 International Business Machines Corporation Multiple caches using state information indicating if cache line was previously modified and type of access rights granted to assign access rights to cache line
US4928225A (en) * 1988-08-25 1990-05-22 Edgcore Technology, Inc. Coherent cache structures and methods
US5029070A (en) * 1988-08-25 1991-07-02 Edge Computer Corporation Coherent cache structures and methods
GB8823077D0 (en) * 1988-09-30 1988-11-09 Int Computers Ltd Data processing apparatus
US5027270A (en) * 1988-10-11 1991-06-25 Mips Computer Systems, Inc. Processor controlled interface with instruction streaming
US4965717A (en) * 1988-12-09 1990-10-23 Tandem Computers Incorporated Multiple processor system having shared memory with private-write capability
US5202972A (en) * 1988-12-29 1993-04-13 International Business Machines Corporation Store buffer apparatus in a multiprocessor system
US5222217A (en) * 1989-01-18 1993-06-22 International Business Machines Corporation System and method for implementing operating system message queues with recoverable shared virtual storage
US5222224A (en) * 1989-02-03 1993-06-22 Digital Equipment Corporation Scheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor system
US5210848A (en) * 1989-02-22 1993-05-11 International Business Machines Corporation Multi-processor caches with large granularity exclusivity locking
US5097532A (en) * 1989-03-03 1992-03-17 Compaq Computer Corporation Circuit for enabling a cache using a flush input to circumvent a late noncachable address input
US5210847A (en) * 1989-05-19 1993-05-11 Compaq Computer Corporation Noncacheable address random access memory
CA2019300C (en) * 1989-06-22 2001-06-12 Kendall Square Research Corporation Multiprocessor system with shared memory
US5182805A (en) * 1989-07-14 1993-01-26 Ncr Corporation Method and system for determining copy-on-write condition
US5230070A (en) * 1989-09-08 1993-07-20 International Business Machines Corporation Access authorization table for multi-processor caches
JPH0697449B2 (ja) * 1989-09-20 1994-11-30 株式会社日立製作所 多重化共有メモリ制御方法、多重化共有メモリシステムおよび共有メモリ拡張方法
DE58909135D1 (de) * 1989-09-29 1995-04-27 Siemens Ag Kommunikationssystem für miteinander verbundene speicherprogrammierbare Steuerungen.
JPH0666056B2 (ja) * 1989-10-12 1994-08-24 甲府日本電気株式会社 情報処理システム
US5301290A (en) * 1990-03-14 1994-04-05 International Business Machines Corporation Method for minimizing lock processing while ensuring consistency among pages common to local processor caches and a shared external store
US5289585A (en) * 1990-03-26 1994-02-22 Siemens Nixdorf Informationssysteme Ag Multiprocessor system having a system bus for the coupling of several processing units with appertaining private cache memories and a common main memory
US5197139A (en) * 1990-04-05 1993-03-23 International Business Machines Corporation Cache management for multi-processor systems utilizing bulk cross-invalidate
US5247648A (en) * 1990-04-12 1993-09-21 Sun Microsystems, Inc. Maintaining data coherency between a central cache, an I/O cache and a memory
US5297269A (en) * 1990-04-26 1994-03-22 Digital Equipment Company Cache coherency protocol for multi processor computer system
EP0458516B1 (de) * 1990-05-25 1997-11-05 AT&T Corp. Busanordnung für Speicherzugriff
US5249284A (en) * 1990-06-04 1993-09-28 Ncr Corporation Method and system for maintaining data coherency between main and cache memories
US5029209A (en) * 1990-06-13 1991-07-02 The Boeing Company Pseudorandom, iterative method and apparatus for automatically creating addresses
US5263144A (en) * 1990-06-29 1993-11-16 Digital Equipment Corporation Method and apparatus for sharing data between processors in a computer system
US5155843A (en) * 1990-06-29 1992-10-13 Digital Equipment Corporation Error transition mode for multi-processor system
US5404483A (en) * 1990-06-29 1995-04-04 Digital Equipment Corporation Processor and method for delaying the processing of cache coherency transactions during outstanding cache fills
US5251310A (en) * 1990-06-29 1993-10-05 Digital Equipment Corporation Method and apparatus for exchanging blocks of information between a cache memory and a main memory
US5404482A (en) * 1990-06-29 1995-04-04 Digital Equipment Corporation Processor and method for preventing access to a locked memory block by recording a lock in a content addressable memory with outstanding cache fills
JP3009430B2 (ja) * 1990-07-09 2000-02-14 キヤノン株式会社 プロセッサおよびそのキャッシュメモリ制御方法
DE69130967T2 (de) * 1990-08-06 1999-10-21 Ncr Int Inc Rechnerspeicheranordnung
US5530941A (en) * 1990-08-06 1996-06-25 Ncr Corporation System and method for prefetching data from a main computer memory into a cache memory
US5483645A (en) * 1990-10-26 1996-01-09 Advanced Micro Devices, Inc. Cache access system for multiple requestors providing independent access to the cache arrays
US5291442A (en) * 1990-10-31 1994-03-01 International Business Machines Corporation Method and apparatus for dynamic cache line sectoring in multiprocessor systems
CA2051222C (en) * 1990-11-30 1998-05-05 Pradeep S. Sindhu Consistent packet switched memory bus for shared memory multiprocessors
JPH04291446A (ja) * 1990-12-05 1992-10-15 Ncr Corp スケーラブルメモリ帯域を備えた緊密結合型多重プロセッサ
US5249283A (en) * 1990-12-24 1993-09-28 Ncr Corporation Cache coherency method and apparatus for a multiple path interconnection network
JPH04353947A (ja) * 1991-02-13 1992-12-08 Hewlett Packard Co <Hp> メモリページ特性タグ付けシステム
US5490261A (en) * 1991-04-03 1996-02-06 International Business Machines Corporation Interlock for controlling processor ownership of pipelined data for a store in cache
US5313609A (en) * 1991-05-23 1994-05-17 International Business Machines Corporation Optimum write-back strategy for directory-based cache coherence protocols
JPH04367963A (ja) * 1991-06-15 1992-12-21 Hitachi Ltd 共有記憶通信方法
CA2078310A1 (en) * 1991-09-20 1993-03-21 Mark A. Kaufman Digital processor with distributed memory system
CA2078312A1 (en) 1991-09-20 1993-03-21 Mark A. Kaufman Digital data processor with improved paging
US5313647A (en) * 1991-09-20 1994-05-17 Kendall Square Research Corporation Digital data processor with improved checkpointing and forking
CA2078315A1 (en) * 1991-09-20 1993-03-21 Christopher L. Reeve Parallel processing apparatus and method for utilizing tiling
GB2260429B (en) * 1991-10-11 1995-05-24 Intel Corp Versatile cache memory
US5301298A (en) * 1991-10-11 1994-04-05 Intel Corporation Processor for multiple cache coherent protocols
US5335333A (en) * 1991-10-29 1994-08-02 Intel Corporation Guess mechanism for faster address calculation in a pipelined microprocessor
US5504913A (en) * 1992-05-14 1996-04-02 Apple Computer, Inc. Queue memory with self-handling addressing and underflow
US5355471A (en) * 1992-08-14 1994-10-11 Pyramid Technology Corporation Multiprocessor cache coherency tester that exercises the coherency logic exhaustively and also detects errors in a processor using an automatic CPU sort
JP2819982B2 (ja) * 1993-03-18 1998-11-05 株式会社日立製作所 範囲指定可能なキャッシュ一致保証機能を有するマルチプロセッサシステム
US5347514A (en) * 1993-03-26 1994-09-13 International Business Machines Corporation Processor-based smart packet memory interface
US5490279A (en) * 1993-05-21 1996-02-06 Intel Corporation Method and apparatus for operating a single CPU computer system as a multiprocessor system
US5504874A (en) * 1993-09-29 1996-04-02 Silicon Graphics, Inc. System and method of implementing read resources to maintain cache coherency in a multiprocessor environment permitting split transactions
JP2634141B2 (ja) * 1994-01-19 1997-07-23 インターナショナル・ビジネス・マシーンズ・コーポレイション マルチプロセッサ・システム
US5905997A (en) * 1994-04-29 1999-05-18 Amd Inc. Set-associative cache memory utilizing a single bank of physical memory
US5577226A (en) * 1994-05-06 1996-11-19 Eec Systems, Inc. Method and system for coherently caching I/O devices across a network
DE69535409T2 (de) * 1994-06-29 2007-11-08 Intel Corp., Santa Clara Prozessor, das das systembusrecht in einem erweiterbaren multiprozessor-rechnersystem anzeigt
US5559987A (en) * 1994-06-30 1996-09-24 Digital Equipment Corporation Method and apparatus for updating a duplicate tag status in a snoop bus protocol based computer system
JPH08185359A (ja) * 1994-10-31 1996-07-16 Toshiba Corp メモリサブシステム
US5895496A (en) * 1994-11-18 1999-04-20 Apple Computer, Inc. System for an method of efficiently controlling memory accesses in a multiprocessor computer system
USRE38514E1 (en) 1994-11-18 2004-05-11 Apple Computer, Inc. System for and method of efficiently controlling memory accesses in a multiprocessor computer system
DE69621263T2 (de) * 1995-01-23 2002-12-19 Compaq Computer Corp Verteilter Datencachespeicher für Multiprozessorsystem mit Cachespeicher
US5819306A (en) * 1995-02-14 1998-10-06 General Magic Shadow mechanism for a modifiable object oriented system
JP3872118B2 (ja) * 1995-03-20 2007-01-24 富士通株式会社 キャッシュコヒーレンス装置
US5787476A (en) * 1995-05-05 1998-07-28 Silicon Graphics, Inc. System and method for maintaining coherency of virtual-to-physical memory translations in a multiprocessor computer
US5594863A (en) * 1995-06-26 1997-01-14 Novell, Inc. Method and apparatus for network file recovery
EP0839353B1 (de) * 1995-07-20 2001-09-26 Novell, Inc. Transaktionssynchronisierung in einem netz abtrennbarer rechner
AU6500596A (en) 1995-07-20 1997-02-18 Novell, Inc. Transaction log management in a disconnectable computer and network
JPH09223118A (ja) * 1996-02-14 1997-08-26 Oki Electric Ind Co Ltd スヌープキャッシュメモリ制御システム
US5829033A (en) * 1996-07-01 1998-10-27 Sun Microsystems, Inc. Optimizing responses in a coherent distributed electronic system including a computer system
JP3269967B2 (ja) * 1996-04-24 2002-04-02 株式会社日立製作所 キャッシュコヒーレンシ制御方法、および、これを用いたマルチプロセッサシステム
US5892970A (en) 1996-07-01 1999-04-06 Sun Microsystems, Inc. Multiprocessing system configured to perform efficient block copy operations
US5805839A (en) * 1996-07-02 1998-09-08 Advanced Micro Devices, Inc. Efficient technique for implementing broadcasts on a system of hierarchical buses
US5796605A (en) * 1996-07-02 1998-08-18 Sun Microsystems, Inc. Extended symmetrical multiprocessor address mapping
US5878434A (en) * 1996-07-18 1999-03-02 Novell, Inc Transaction clash management in a disconnectable computer and network
US5717897A (en) * 1996-09-09 1998-02-10 Unisys Corporation System for coordinating coherency of cache memories of multiple host computers of a distributed information system
US6128711A (en) * 1996-11-12 2000-10-03 Compaq Computer Corporation Performance optimization and system bus duty cycle reduction by I/O bridge partial cache line writes
US5893161A (en) * 1996-11-12 1999-04-06 Hewlett-Packard Co. Method for allocating ownership of portions of memory in a coherent memory system
US6078997A (en) * 1996-12-09 2000-06-20 Intel Corporation Directory-based coherency system for maintaining coherency in a dual-ported memory system
US6148375A (en) * 1998-02-13 2000-11-14 International Business Machines Corporation Hierarchical bus simple COMA architecture for shared memory multiprocessors having a bus directly interconnecting caches between nodes
US6286081B1 (en) * 1998-05-19 2001-09-04 Advanced Micro Devices, Inc. Mechanism for ensuring data coherency during sequential readings of portions of data that changes with time
US6678838B1 (en) * 1999-08-23 2004-01-13 Advanced Micro Devices, Inc. Method to track master contribution information in a write buffer
US7233998B2 (en) * 2001-03-22 2007-06-19 Sony Computer Entertainment Inc. Computer architecture and software cells for broadband networks
US7516334B2 (en) * 2001-03-22 2009-04-07 Sony Computer Entertainment Inc. Power management for processing modules
US6526491B2 (en) * 2001-03-22 2003-02-25 Sony Corporation Entertainment Inc. Memory protection system and method for computer architecture for broadband networks
US6826662B2 (en) * 2001-03-22 2004-11-30 Sony Computer Entertainment Inc. System and method for data synchronization for a computer architecture for broadband networks
US7231500B2 (en) * 2001-03-22 2007-06-12 Sony Computer Entertainment Inc. External data interface in a computer architecture for broadband networks
US7017012B2 (en) * 2002-06-20 2006-03-21 Sun Microsystems, Inc. Distributed storage cache coherency system and method
US9110853B2 (en) * 2003-03-10 2015-08-18 Oracle America, Inc. Computer system with multiple classes of device IDs
US8224639B2 (en) 2004-03-29 2012-07-17 Sony Computer Entertainment Inc. Methods and apparatus for achieving thermal management using processing task scheduling
US8243737B2 (en) * 2009-03-23 2012-08-14 Lsi Corporation High speed packet FIFO input buffers for switch fabric with speedup and retransmit
US8869151B2 (en) 2010-05-18 2014-10-21 Lsi Corporation Packet draining from a scheduling hierarchy in a traffic manager of a network processor
US8489791B2 (en) 2010-03-12 2013-07-16 Lsi Corporation Processor bus bridge security feature for network processors or the like
US8910168B2 (en) 2009-04-27 2014-12-09 Lsi Corporation Task backpressure and deletion in a multi-flow network processor architecture
US8935483B2 (en) * 2009-04-27 2015-01-13 Lsi Corporation Concurrent, coherent cache access for multiple threads in a multi-core, multi-thread network processor
US8547878B2 (en) 2010-05-18 2013-10-01 Lsi Corporation Modularized scheduling engine for traffic management in a network processor
US8868889B2 (en) * 2010-03-12 2014-10-21 Lsi Corporation Instruction breakpoints in a multi-core, multi-thread network communications processor architecture
US8638805B2 (en) 2010-05-18 2014-01-28 Lsi Corporation Packet draining from a scheduling hierarchy in a traffic manager of a network processor
US9300597B2 (en) 2009-04-27 2016-03-29 Intel Corporation Statistics module for network processors in virtual local area networks
US8619787B2 (en) 2010-05-18 2013-12-31 Lsi Corporation Byte-accurate scheduling in a network processor
US8837501B2 (en) 2010-05-18 2014-09-16 Lsi Corporation Shared task parameters in a scheduler of a network processor
US8949582B2 (en) 2009-04-27 2015-02-03 Lsi Corporation Changing a flow identifier of a packet in a multi-thread, multi-flow network processor
US9444757B2 (en) 2009-04-27 2016-09-13 Intel Corporation Dynamic configuration of processing modules in a network communications processor architecture
US8869150B2 (en) 2010-05-18 2014-10-21 Lsi Corporation Local messaging in a scheduling hierarchy in a traffic manager of a network processor
US8761204B2 (en) 2010-05-18 2014-06-24 Lsi Corporation Packet assembly module for multi-core, multi-thread network processors
US8407707B2 (en) * 2009-05-18 2013-03-26 Lsi Corporation Task queuing in a network communications processor architecture
US8943507B2 (en) * 2009-04-27 2015-01-27 Deepak Mital Packet assembly module for multi-core, multi-thread network processors
US8321385B2 (en) * 2010-03-12 2012-11-27 Lsi Corporation Hash processing in a network communications processor architecture
US8499137B2 (en) * 2010-03-12 2013-07-30 Lsi Corporation Memory manager for a network communications processor architecture
US8949500B2 (en) 2011-08-08 2015-02-03 Lsi Corporation Non-blocking processor bus bridge for network processors or the like
US8869156B2 (en) 2010-05-18 2014-10-21 Lsi Corporation Speculative task reading in a traffic manager of a network processor
US8949578B2 (en) 2009-04-27 2015-02-03 Lsi Corporation Sharing of internal pipeline resources of a network processor with external devices
US9160684B2 (en) 2009-04-27 2015-10-13 Intel Corporation Dynamic updating of scheduling hierarchy in a traffic manager of a network processor
US9218290B2 (en) 2009-04-27 2015-12-22 Intel Corporation Data caching in a network communications processor architecture
US8505013B2 (en) * 2010-03-12 2013-08-06 Lsi Corporation Reducing data read latency in a network communications processor architecture
US8683221B2 (en) 2010-05-18 2014-03-25 Lsi Corporation Configurable memory encryption with constant pipeline delay in a multi-core processor
US8615013B2 (en) 2010-05-18 2013-12-24 Agere Systems Llc Packet scheduling with guaranteed minimum rate in a traffic manager of a network processor
US8705531B2 (en) 2010-05-18 2014-04-22 Lsi Corporation Multicast address learning in an input/output adapter of a network processor
US8910171B2 (en) * 2009-04-27 2014-12-09 Lsi Corporation Thread synchronization in a multi-thread network communications processor architecture
US8677075B2 (en) 2010-05-18 2014-03-18 Lsi Corporation Memory manager for a network communications processor architecture
US8848723B2 (en) 2010-05-18 2014-09-30 Lsi Corporation Scheduling hierarchy in a traffic manager of a network processor
US8873550B2 (en) 2010-05-18 2014-10-28 Lsi Corporation Task queuing in a multi-flow network processor architecture
US9183145B2 (en) 2009-04-27 2015-11-10 Intel Corporation Data caching in a network communications processor architecture
US8515965B2 (en) 2010-05-18 2013-08-20 Lsi Corporation Concurrent linked-list traversal for real-time hash processing in multi-core, multi-thread network processors
US8843682B2 (en) 2010-05-18 2014-09-23 Lsi Corporation Hybrid address mutex mechanism for memory accesses in a network processor
US8537832B2 (en) * 2010-03-12 2013-09-17 Lsi Corporation Exception detection and thread rescheduling in a multi-core, multi-thread network processor
US9461930B2 (en) 2009-04-27 2016-10-04 Intel Corporation Modifying data streams without reordering in a multi-thread, multi-flow network processor
US8565250B2 (en) 2010-05-18 2013-10-22 Lsi Corporation Multithreaded, superscalar scheduling in a traffic manager of a network processor
US9727508B2 (en) 2009-04-27 2017-08-08 Intel Corporation Address learning and aging for network bridging in a network processor
US8576862B2 (en) 2010-05-18 2013-11-05 Lsi Corporation Root scheduling algorithm in a network processor
US8539199B2 (en) * 2010-03-12 2013-09-17 Lsi Corporation Hash processing in a network communications processor architecture
US8874878B2 (en) 2010-05-18 2014-10-28 Lsi Corporation Thread synchronization in a multi-thread, multi-flow network communications processor architecture
US8917738B2 (en) 2009-04-27 2014-12-23 Lsi Corporation Multicasting traffic manager in a network communications processor architecture
US8514874B2 (en) * 2010-03-12 2013-08-20 Lsi Corporation Thread synchronization in a multi-thread network communications processor architecture
US9152564B2 (en) 2010-05-18 2015-10-06 Intel Corporation Early cache eviction in a multi-flow network processor architecture
US9755947B2 (en) 2010-05-18 2017-09-05 Intel Corporation Hierarchical self-organizing classification processing in a network switch
US9485200B2 (en) 2010-05-18 2016-11-01 Intel Corporation Network switch with external buffering via looparound path
US9065761B2 (en) 2011-07-25 2015-06-23 Intel Corporation Packet reassembly processing
US9304923B2 (en) * 2013-03-12 2016-04-05 Arm Limited Data coherency management
US8997210B1 (en) * 2013-10-11 2015-03-31 Advanced Micro Devices, Inc. Leveraging a peripheral device to execute a machine instruction
KR102482516B1 (ko) 2016-11-29 2022-12-29 에이알엠 리미티드 메모리 어드레스 변환
US10831673B2 (en) 2017-11-22 2020-11-10 Arm Limited Memory address translation
US10929308B2 (en) 2017-11-22 2021-02-23 Arm Limited Performing maintenance operations
US10866904B2 (en) * 2017-11-22 2020-12-15 Arm Limited Data storage for multiple data types
FR3078176B1 (fr) * 2018-02-19 2020-02-28 IFP Energies Nouvelles Systeme et procede de prediction d'un phenomene physique et/ou chimique au moyen d'un segment de memoire partage
US11138111B2 (en) * 2018-09-12 2021-10-05 Apple Inc. Parallel coherence and memory cache processing pipelines
CN115599459B (zh) * 2022-12-13 2023-04-07 成都启英泰伦科技有限公司 一种跨电源域多处理器运行装置及其通信方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4141067A (en) * 1977-06-13 1979-02-20 General Automation Multiprocessor system with cache memory

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EP0149355B1 (de) 1993-06-09
EP0149355A3 (en) 1987-09-23
US4622631B1 (en) 1996-04-09
JPH0658660B2 (ja) 1994-08-03
US4622631A (en) 1986-11-11
EP0149355A2 (de) 1985-07-24
DE3486161T2 (de) 1993-09-30
JPS60237552A (ja) 1985-11-26

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