DE3577022D1 - Ic-chipstruktur mit kompensation der durch die verdrahtung verursachten kapazitiven last. - Google Patents

Ic-chipstruktur mit kompensation der durch die verdrahtung verursachten kapazitiven last.

Info

Publication number
DE3577022D1
DE3577022D1 DE8585114667T DE3577022T DE3577022D1 DE 3577022 D1 DE3577022 D1 DE 3577022D1 DE 8585114667 T DE8585114667 T DE 8585114667T DE 3577022 T DE3577022 T DE 3577022T DE 3577022 D1 DE3577022 D1 DE 3577022D1
Authority
DE
Germany
Prior art keywords
compensation
capacitive load
chip structure
wiring capacitive
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8585114667T
Other languages
English (en)
Inventor
Edward Francis Culican
Pritzlaff, Jr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3577022D1 publication Critical patent/DE3577022D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11801—Masterslice integrated circuits using bipolar technology
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00376—Modifications for compensating variations of temperature, supply voltage or other physical parameters in bipolar transistor circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE8585114667T 1984-12-03 1985-11-19 Ic-chipstruktur mit kompensation der durch die verdrahtung verursachten kapazitiven last. Expired - Fee Related DE3577022D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/677,618 US4774559A (en) 1984-12-03 1984-12-03 Integrated circuit chip structure wiring and circuitry for driving highly capacitive on chip wiring nets

Publications (1)

Publication Number Publication Date
DE3577022D1 true DE3577022D1 (de) 1990-05-10

Family

ID=24719455

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585114667T Expired - Fee Related DE3577022D1 (de) 1984-12-03 1985-11-19 Ic-chipstruktur mit kompensation der durch die verdrahtung verursachten kapazitiven last.

Country Status (5)

Country Link
US (1) US4774559A (de)
EP (1) EP0186769B1 (de)
JP (1) JPS61135225A (de)
CA (1) CA1229428A (de)
DE (1) DE3577022D1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5111276A (en) * 1985-03-19 1992-05-05 National Semiconductor Corp. Thick bus metallization interconnect structure to reduce bus area
JP2606845B2 (ja) * 1987-06-19 1997-05-07 富士通株式会社 半導体集積回路
US5223733A (en) * 1988-10-31 1993-06-29 Hitachi, Ltd. Semiconductor integrated circuit apparatus and method for designing the same
US5136357A (en) * 1989-06-26 1992-08-04 Micron Technology, Inc. Low-noise, area-efficient, high-frequency clock signal distribution line structure
US5206529A (en) * 1989-09-25 1993-04-27 Nec Corporation Semiconductor integrated circuit device
US5068715A (en) * 1990-06-29 1991-11-26 Digital Equipment Corporation High-power, high-performance integrated circuit chip package
JP3027990B2 (ja) * 1991-03-18 2000-04-04 富士通株式会社 半導体装置の製造方法

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3379584A (en) * 1964-09-04 1968-04-23 Texas Instruments Inc Semiconductor wafer with at least one epitaxial layer and methods of making same
US3555294A (en) * 1967-02-28 1971-01-12 Motorola Inc Transistor-transistor logic circuits having improved voltage transfer characteristic
US3562547A (en) * 1967-04-17 1971-02-09 Ibm Protection diode for integrated circuit
US3488564A (en) * 1968-04-01 1970-01-06 Fairchild Camera Instr Co Planar epitaxial resistors
US3513365A (en) * 1968-06-24 1970-05-19 Mark W Levi Field-effect integrated circuit and method of fabrication
US3610951A (en) * 1969-04-03 1971-10-05 Sprague Electric Co Dynamic shift register
US3631309A (en) * 1970-07-23 1971-12-28 Semiconductor Elect Memories Integrated circuit bipolar memory cell
US3656004A (en) * 1970-09-28 1972-04-11 Ibm Bipolar capacitor driver
JPS5435474B2 (de) * 1973-03-26 1979-11-02
JPS50142128A (de) * 1974-05-07 1975-11-15
JPS60953B2 (ja) * 1977-12-30 1985-01-11 富士通株式会社 半導体集積回路装置
US4200811A (en) * 1978-05-11 1980-04-29 Rca Corporation Frequency divider circuit
US4249193A (en) * 1978-05-25 1981-02-03 International Business Machines Corporation LSI Semiconductor device and fabrication thereof
US4278897A (en) * 1978-12-28 1981-07-14 Fujitsu Limited Large scale semiconductor integrated circuit device
US4295149A (en) * 1978-12-29 1981-10-13 International Business Machines Corporation Master image chip organization technique or method
US4346343A (en) * 1980-05-16 1982-08-24 International Business Machines Corporation Power control means for eliminating circuit to circuit delay differences and providing a desired circuit delay
JPS57160143A (en) * 1981-03-27 1982-10-02 Fujitsu Ltd Semiconductor device
US4417159A (en) * 1981-08-18 1983-11-22 International Business Machines Corporation Diode-transistor active pull up driver
JPS5844743A (ja) * 1981-09-10 1983-03-15 Fujitsu Ltd 半導体集積回路
US4489417A (en) * 1982-11-24 1984-12-18 International Business Machines Corporation Multi-level communication circuitry for communicating digital signals between integrated circuits
US4584653A (en) * 1983-03-22 1986-04-22 Fujitsu Limited Method for manufacturing a gate array integrated circuit device

Also Published As

Publication number Publication date
CA1229428A (en) 1987-11-17
EP0186769B1 (de) 1990-04-04
EP0186769A2 (de) 1986-07-09
JPH0518462B2 (de) 1993-03-12
JPS61135225A (ja) 1986-06-23
EP0186769A3 (en) 1988-09-07
US4774559A (en) 1988-09-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee