DE3673270D1 - Verfahren und geraet zur durchfuehrung von datenleseoperationen mit veraenderlicher laenge. - Google Patents
Verfahren und geraet zur durchfuehrung von datenleseoperationen mit veraenderlicher laenge.Info
- Publication number
- DE3673270D1 DE3673270D1 DE8686304504T DE3673270T DE3673270D1 DE 3673270 D1 DE3673270 D1 DE 3673270D1 DE 8686304504 T DE8686304504 T DE 8686304504T DE 3673270 T DE3673270 T DE 3673270T DE 3673270 D1 DE3673270 D1 DE 3673270D1
- Authority
- DE
- Germany
- Prior art keywords
- carrying
- variable length
- out data
- data reading
- reading operations
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/750,377 US4703418A (en) | 1985-06-28 | 1985-06-28 | Method and apparatus for performing variable length data read transactions |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3673270D1 true DE3673270D1 (de) | 1990-09-13 |
Family
ID=25017624
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8686304504T Expired - Lifetime DE3673270D1 (de) | 1985-06-28 | 1986-06-12 | Verfahren und geraet zur durchfuehrung von datenleseoperationen mit veraenderlicher laenge. |
Country Status (5)
Country | Link |
---|---|
US (1) | US4703418A (de) |
EP (1) | EP0208430B1 (de) |
JP (1) | JPH0752418B2 (de) |
CA (1) | CA1259422A (de) |
DE (1) | DE3673270D1 (de) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4851991A (en) * | 1987-02-24 | 1989-07-25 | Digital Equipment Corporation | Central processor unit for digital data processing system including write buffer management mechanism |
AU622626B2 (en) * | 1987-06-03 | 1992-04-16 | Sony Corporation | Method of processing data |
US4998198A (en) * | 1988-04-07 | 1991-03-05 | Tandem Computers Incorporated | Dynamic burst control for data transfers |
US5251303A (en) * | 1989-01-13 | 1993-10-05 | International Business Machines Corporation | System for DMA block data transfer based on linked control blocks |
US5255371A (en) * | 1990-04-02 | 1993-10-19 | Unisys Corporation | Apparatus for interfacing a real-time communication link to an asynchronous digital computer system by utilizing grouped data transfer commands |
IL96808A (en) | 1990-04-18 | 1996-03-31 | Rambus Inc | Introductory / Origin Circuit Agreed Using High-Performance Brokerage |
US6751696B2 (en) | 1990-04-18 | 2004-06-15 | Rambus Inc. | Memory device having a programmable register |
US6324120B2 (en) | 1990-04-18 | 2001-11-27 | Rambus Inc. | Memory device having a variable data output length |
JPH0520263A (ja) * | 1991-07-15 | 1993-01-29 | Nec Corp | データ転送制御装置 |
US5379381A (en) * | 1991-08-12 | 1995-01-03 | Stratus Computer, Inc. | System using separate transfer circuits for performing different transfer operations respectively and scanning I/O devices status upon absence of both operations |
US5444853A (en) * | 1992-03-31 | 1995-08-22 | Seiko Epson Corporation | System and method for transferring data between a plurality of virtual FIFO's and a peripheral via a hardware FIFO and selectively updating control information associated with the virtual FIFO's |
US5517670A (en) * | 1992-12-30 | 1996-05-14 | International Business Machines Corporation | Adaptive data transfer channel employing extended data block capability |
US6122717A (en) * | 1996-06-17 | 2000-09-19 | Integrated Device Technology, Inc. | Methods and apparatus for a memory that supports a variable number of bytes per logical cell and a variable number of cells |
US6802022B1 (en) | 2000-04-14 | 2004-10-05 | Stratus Technologies Bermuda Ltd. | Maintenance of consistent, redundant mass storage images |
US6886171B2 (en) | 2001-02-20 | 2005-04-26 | Stratus Technologies Bermuda Ltd. | Caching for I/O virtual address translation and validation using device drivers |
US6766413B2 (en) | 2001-03-01 | 2004-07-20 | Stratus Technologies Bermuda Ltd. | Systems and methods for caching with file-level granularity |
US6971043B2 (en) | 2001-04-11 | 2005-11-29 | Stratus Technologies Bermuda Ltd | Apparatus and method for accessing a mass storage device in a fault-tolerant server |
EP1591906A1 (de) * | 2004-04-27 | 2005-11-02 | Texas Instruments Incorporated | Effiziente Datenübertragung von einem ASIC zu einem host unter Verwendung von DMA |
US20060259657A1 (en) * | 2005-05-10 | 2006-11-16 | Telairity Semiconductor, Inc. | Direct memory access (DMA) method and apparatus and DMA for video processing |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4038642A (en) * | 1976-04-30 | 1977-07-26 | International Business Machines Corporation | Input/output interface logic for concurrent operations |
JPS54530A (en) * | 1977-06-03 | 1979-01-05 | Hitachi Ltd | Reference control unit of memory |
JPS5455132A (en) * | 1977-10-12 | 1979-05-02 | Toshiba Corp | Input-output control system |
JPS586173B2 (ja) * | 1978-01-20 | 1983-02-03 | 株式会社日立製作所 | チャネル制御方式 |
JPS57113162A (en) * | 1980-12-29 | 1982-07-14 | Fujitsu Ltd | High-speed external storage device |
US4644463A (en) * | 1982-12-07 | 1987-02-17 | Burroughs Corporation | System for regulating data transfer operations |
-
1985
- 1985-06-28 US US06/750,377 patent/US4703418A/en not_active Expired - Lifetime
-
1986
- 1986-06-09 JP JP61133591A patent/JPH0752418B2/ja not_active Expired - Lifetime
- 1986-06-12 DE DE8686304504T patent/DE3673270D1/de not_active Expired - Lifetime
- 1986-06-12 EP EP86304504A patent/EP0208430B1/de not_active Expired
- 1986-06-12 CA CA000511442A patent/CA1259422A/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
US4703418A (en) | 1987-10-27 |
EP0208430A1 (de) | 1987-01-14 |
JPH0752418B2 (ja) | 1995-06-05 |
EP0208430B1 (de) | 1990-08-08 |
CA1259422A (en) | 1989-09-12 |
JPS623362A (ja) | 1987-01-09 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: HEWLETT-PACKARD CO. (N.D.GES.D.STAATES DELAWARE), |
|
8327 | Change in the person/name/address of the patent owner |
Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, TE |