DE3686453T2 - Verfahren zum herstellen einer duennen halbleiterschicht. - Google Patents

Verfahren zum herstellen einer duennen halbleiterschicht.

Info

Publication number
DE3686453T2
DE3686453T2 DE8686106713T DE3686453T DE3686453T2 DE 3686453 T2 DE3686453 T2 DE 3686453T2 DE 8686106713 T DE8686106713 T DE 8686106713T DE 3686453 T DE3686453 T DE 3686453T DE 3686453 T2 DE3686453 T2 DE 3686453T2
Authority
DE
Germany
Prior art keywords
producing
semiconductor layer
thin semiconductor
thin
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686106713T
Other languages
English (en)
Other versions
DE3686453D1 (de
Inventor
John Robert Abernathey
Jerome Brett Lasky
Larry Alan Nesbit
Thomas Oliver Sedgwick
Scott Richard Stiffler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3686453D1 publication Critical patent/DE3686453D1/de
Publication of DE3686453T2 publication Critical patent/DE3686453T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
DE8686106713T 1985-06-24 1986-05-16 Verfahren zum herstellen einer duennen halbleiterschicht. Expired - Fee Related DE3686453T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/747,746 US4601779A (en) 1985-06-24 1985-06-24 Method of producing a thin silicon-on-insulator layer

Publications (2)

Publication Number Publication Date
DE3686453D1 DE3686453D1 (de) 1992-09-24
DE3686453T2 true DE3686453T2 (de) 1993-03-18

Family

ID=25006451

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686106713T Expired - Fee Related DE3686453T2 (de) 1985-06-24 1986-05-16 Verfahren zum herstellen einer duennen halbleiterschicht.

Country Status (5)

Country Link
US (1) US4601779A (de)
EP (1) EP0207272B1 (de)
JP (1) JPH0834174B2 (de)
CA (1) CA1218762A (de)
DE (1) DE3686453T2 (de)

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US5024723A (en) * 1990-05-07 1991-06-18 Goesele Ulrich M Method of producing a thin silicon on insulator layer by wafer bonding and chemical thinning
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DE69226687T2 (de) * 1991-10-16 1999-04-15 Sony Corp Verfahren zur Herstellung einer SOI-Struktur mit einem DRAM
JP2602597B2 (ja) * 1991-12-27 1997-04-23 信越半導体株式会社 薄膜ｓｏｉ基板の製造方法
DE69333619T2 (de) * 1992-01-30 2005-09-29 Canon K.K. Herstellungsverfahren für Halbleitersubstrate
US5213986A (en) * 1992-04-10 1993-05-25 North American Philips Corporation Process for making thin film silicon-on-insulator wafers employing wafer bonding and wafer thinning
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US5413679A (en) * 1993-06-30 1995-05-09 The United States Of America As Represented By The Secretary Of The Navy Method of producing a silicon membrane using a silicon alloy etch stop layer
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US5488012A (en) * 1993-10-18 1996-01-30 The Regents Of The University Of California Silicon on insulator with active buried regions
US5399231A (en) * 1993-10-18 1995-03-21 Regents Of The University Of California Method of forming crystalline silicon devices on glass
US5395481A (en) * 1993-10-18 1995-03-07 Regents Of The University Of California Method for forming silicon on a glass substrate
US5414276A (en) * 1993-10-18 1995-05-09 The Regents Of The University Of California Transistors using crystalline silicon devices on glass
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US5455193A (en) * 1994-11-17 1995-10-03 Philips Electronics North America Corporation Method of forming a silicon-on-insulator (SOI) material having a high degree of thickness uniformity
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US5985728A (en) * 1995-09-01 1999-11-16 Elantec Semiconductor, Inc. Silicon on insulator process with recovery of a device layer from an etch stop layer
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Also Published As

Publication number Publication date
JPH0834174B2 (ja) 1996-03-29
US4601779A (en) 1986-07-22
JPS61296709A (ja) 1986-12-27
EP0207272A3 (en) 1988-04-20
CA1218762A (en) 1987-03-03
EP0207272B1 (de) 1992-08-19
EP0207272A2 (de) 1987-01-07
DE3686453D1 (de) 1992-09-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee